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A Practical Computer Architecture Education with RISC-V and TL-Verilog
... In the past decades, much academic effort in Computer Architecture courses has focused on developing pedagogical methods using software tools for hardware performance simulation [3,4]. Students are often motivated by the hands-on nature of these types of engineering tools [5,6]. ...
... Simulation tools are useful for modeling real systems. They are often desirable and necessary to allow students to study systems that are impractical to design and implement given the time and resources available [6]. Other advantages include low cost and immediate availability at any location, such as the student's residence. ...
... Carefully planned practical assignments in a laboratory setting should help students develop confidence in their technical abilities [6]. However, the teaching methodology based on simulating hardware operation can establish ideas in the minds of students that are misleading. ...
Problem statement. In the Computer Architecture course of Computer Science and Engineering undergraduate programs , there are often labs with simulation tools. This teaching method can give students misleading ideas about how hardware works because they are observing the behavior of a computer program, not the real hardware. In addition, the financial investment required to use real and non-reconfigurable equipment in a performance-oriented Computer Architecture course is relatively high. Methodology. This paper proposes a set of hands-on laboratory experiments for undergraduate students enrolled in a Computer Architecture course focused on performance evaluation of RISC-V architecture computers. The most prominent feature of these labs is the multiple reconfiguration of a single real FPGA-based board. All FPGA configurations build soft system-on-chip computers based on Nios V processors. Main findings. The methodology proposed here has been used in the training of more than 1,000 computer science students for more than 10 years. We have observed that this methodology allows: all students to interact with a hardware system that is more realistic than the one modeled by simulators, each student to interact with multiple system-on-chip computers of very different architectures without having to change physical equipment, and that low-cost hardware can be used for Computer Architecture labs where performance evaluation is an important pedagogical goal. Principal conclusion. This method of teaching gives students a more realistic understanding of computer architecture than teaching with hardware simulators. In addition, by using reconfigurable hardware, the lab infrastructure is less costly than using various non-reconfigurable hardware.
... Many authors have made contributions to the study of educational platforms for teaching RISC-V architectures [1][2][3][4][5][6][7][8][9][10]. Sallar et al. [11] believes that the availability of a modern, accessible, and FPGA-friendly RISC-V RTL implementation together with a corresponding Virtual Prototypes (by using emulators) configuration would be very beneficial for the academic community to stimulate further research and for educational purposes, as proposed in their MicroRV32 framework presented in Figure 1. ...
This work introduces a novel custom-designed 16-bit RISC-V processor, intended for educational purposes and for use in low-resource equipment. The implementation, despite providing registers of 16 bits, is based on RV32E RISC-V ISA, but with some key differences like a reduced instruction set that is optimized for embedded systems, the removal of floating-point instructions, reduced register count, and modified data types. These changes enable the processor to operate efficiently in resource-constrained environments while still maintaining assembly-level compatibility with the standard RISC-V architecture. The educational aspects of this project are also a key focus. By working on this project, students can gain hands-on experience with digital logic design, Verilog programming, and computer architecture. The project also includes tools and scripts to help students transform assembly code into binary format, making it easier for them to test and verify their designs. Additionally, the project’s open-source nature allows for collaboration and the sharing of knowledge among students and researchers worldwide.
Student-centered learning has been discovered as the most effective pedagogy for teaching and learning science process skills and content. However, in some difficult curriculum, use of student-centered learning pedagogy only for enhancement of engineering student skills has its drawback. This paper presents a back-and-forth based pedagogy integrated with the student-centered learning for engineering and computer science student curriculum enhancement in Computer Architecture course. In the back-and-forth based learning, course materials are logically decomposed into interconnected pieces. The previous section will be frequently reviewed by the instructor later, on a back and forth basis, while some assignments are assigned to students for enhancement of their learning quality. A series of well-prepared review problems, examples, and assignments were assigned to students to cover various previous topics in this course, which assist in student learning enhancement of hardware and programming skills in Computer Architecture course. Satisfactory performance was evaluated by various milestone review sessions, assignments, in-class exercises, exams and other activities. Results of learning outcomes and assessment indicate that this integrated learning pedagogy is effective and efficient in student learning and improving the quality of computer design and organization.
Computer architecture lies at the intersection of electrical engineering, digital design, compiler design, programming language theory and high-performance computing. It is considered a foundational segment of an electrical and computer engineering education. RISC-V is a new and open ISA that is gaining significant traction in academia. Despite it being used extensively in research, more RISC-V-based tools need to be developed in order for RISC-V to gain greater adoption in computer organization and computer architecture classes. To that end, we present the BRISC-V Platform, a design space exploration tool which offers: (1) a web-based RISC-V simulator, which compiles C and executes assembly within the browser, and (2) a web-based generator of fully-synthesizable, highly-modular and parametrizable hardware systems with support for different types of cores, caches, and network-on-chip topologies. We illustrate how we use these tools in teaching computer organization and computer architecture classes, and describe the structure of these classes.
High-level synthesis raises the design abstraction level and allows rapid generation of optimized RTL hardware for performance, area, and power requirements. This article gives an overview of state-of-the-art HLS techniques and tools.
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- A Salman
Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering
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- S Conry
- J L A Hughes
- L Weidong
- L Junlin
- A Mcgettrick
Verilator and SystemPerl
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RISC-V ABIs Specification, Document Version 1.0
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- J Clarke
MIPS pipeline processor models repository
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Stevehoover - Overview
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