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Multi-Gate In-Plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs
Abstract
Nano electro-mechanical systems (NEMS) based combinational logic circuits have garnered attention as possible replacements for electronic logic systems in safety critical environments where conditions make the use of electronics non-ideal. The principal advantages of NEMS are the inherent near zero leakage current and ability to operate in harsh conditions where substantial parasitic field effects are present. In this work, we design and experimentally demonstrate NEMS based logic gates which utilize multi-gate relays, designed to actuate when input signals are applied to all gate terminals simultaneously. This design enables signal propagation through a single relay for NAND, NOR, and NOT gates with any number of inputs, eliminating variations of output resistance and capacitance, which affect the output generation time. Furthermore, these devices are fabricated using a conventional process requiring only one lithography step. These devices can be utilized to produce all primary logic functions. The proposed platform exclusively uses relay structures based on straight cantilevers, favoring a complementary logic, and allowing for the aforementioned improvements over current designs. The relay structures are optimized using a procedure based on COMSOL simulations. The efficacy of the logic gate designs, and corresponding optimization procedures are validated through a series of electrical tests on fabricated 3-input NAND gate structures utilizing a multi-gate relay. The tests show successful operation for input voltages ranging from 62 and 74 V thus confirming that the approach put forth in this paper can effectively constitute NEMS based complementary logic circuits, while fulfilling all constituent input and output requirements. 2023-0125
... Besides these applications, M/NEMS based combinational logic circuits have garnered attention as possible replacements for electronic logic systems in safety critical environments such as nuclear reactors, particle accelerators, and satellites where conditions make the use of electronics non-ideal [2,3]. In addition to fixed electrodes with sub-micron separations, these devices commonly incorporate flexible electrodes with even narrower controllable gaps from few 100 s to 10 s of nm down to zero nm to facilitate their operation [2,[4][5][6]. In M/NEMS devices, electrostatic forces are usually harnessed to drive mechanical action. ...
... However, simple designs utilizing flexible electrodes such as those in NEMS cantilevers can overcome these fabrication issues and enable accurate measurements. Another advantage of the flexible electrode is that it can be precisely positioned using electrostatic actuation force [2,5] ensuring a well controllable and tunable gap between electrodes. It should also be noted that despite being a crucial material extensively used in M/NEMS devices [2,5,6,12], the arc discharge voltage for Pt electrodes at nanometer-scale separation has not been reported to date. ...
... Another advantage of the flexible electrode is that it can be precisely positioned using electrostatic actuation force [2,5] ensuring a well controllable and tunable gap between electrodes. It should also be noted that despite being a crucial material extensively used in M/NEMS devices [2,5,6,12], the arc discharge voltage for Pt electrodes at nanometer-scale separation has not been reported to date. ...
A thorough understanding of arc discharge mechanism as well as determination of arc discharge voltage at the nanometer scale remains challenging due to the complexities associated with electrode preparation and precisely maintaining nanoscale separations in experiments. This work addresses this challenge through a novel approach by accurately measuring electric breakdown/discharge voltages between Pt-coated Si electrodes with separations ranging from ∼5 nm to 370 nm using a combination of fixed and flexible nano-electrodes while inherently creating an ideal environment to mitigate the effect of mechanical vibrations on the measurement results. For separations of 10, 100, and 300 nm, the corresponding discharge voltages are ∼15, 75, and 160 V, respectively, with the apparent electric field for the 10 nm separation exceeding 1.5 GV m⁻¹. The results acquired from the investigated electrode configuration closely resembling the laterally actuated nanoelectromechanical system (NEMS) cantilever relays reveals strong agreement with NEMS relay breakdown characteristics, emphasizing the importance of arc discharge considerations while designing micro/nano electromechanical devices. Furthermore, deliberately applied arc discharge is shown to provide electrode nano-welding for realization of configurable NEMS circuits.
... Microelectromechanical systems (MEMS) devices such as pressure sensors [6] , logic gates made from laterally actuated cantilever relay [7] , and micromirrors [8] , to name a few, are composed of components between 1 and 100 microns in size. These devices and many others [9], [10], [11] have become a staple in the microelectronics industry with the Bosch process being an invaluable tool towards their production. ...
... This change is extremely small and can be attributed to a change in bottling. In a particular process window, as the temperature reduces below a threshold, the etch profile transitions from a positive taper angle to a negative taper 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A c c e p t e d M a n u s c r i p t Journal XX (XXXX) XXXXXX B. Horstmann et al. 7 angle. The reason for this is an interplay between ion bombardment, temperature, and chemical reactions. ...
Cryogenic deep reactive ion etching (Cryo DRIE) of silicon has become an enticing but challenging process utilized in front-end fabrication for the semiconductor industry. This method, compared to the Bosch process, yields vertical etch profiles with smoother sidewalls not subjected to scalloping, which are desired for many microelectromechanical systems (MEMS) applications. Smoother sidewalls enhance electrical contact by ensuring more conformal and uniform sidewall coverage, thereby increasing the effective contact area without altering contact dimensions. The versatility of the Cryo DRIE process allows for customization of the etch profiles by adjusting key process parameters such as table temperature, O2 percentage of the total gas flow rate (O2 + SF6), RF bias power and process pressure. In this work, we undertake a comprehensive study of the effects of Cryo DRIE process parameters on the trench profiles in the structures used to define cantilevers in MEMS devices. Experiments were performed with an Oxford PlasmaPro 100 Estrelas ICP-RIE system using positive photoresist SPR-955 as a mask material. Our findings demonstrate significant influences on the sidewall angle, etch rate and trench shape due to these parameter modifications. Varying the table temperature between −80 °C and −120 °C under a constant process pressure of 10 mTorr changes the etch rate from 3 to 4 μm min⁻¹, while sidewall angle changes by ∼2°, from positive (<90° relative to the Si surface) to negative (>90° relative to the Si surface) tapering. Altering the O2 flow rate with constant SF6 flow results in a notable 10° shift in sidewall tapering. Furthermore, SPR-955 photoresist masks provide selectivity of 46:1 with respect to Si and facilitates the fabrication of MEMS devices with precise dimension control ranging from 1 to 100 μm for etching depths up to 42 μm using Cryo DRIE. Understanding the influence of each parameter is crucial for optimizing MEMS device fabrication.
Nano/microelectromechanical systems (N/MEMS) based complementary logic circuits offer a physically robust alternative to conventional CMOS control systems, which are able to function in environments unsuitable for transistor devices. In this work we demonstrate novel, configurable, complementary logic circuits comprised entirely of relays at both NEMS and MEMS scale, which are capable of fulfilling all primary logic functions. Lifetime testing of the fabricated devices revealed two key failure modes: contact degradation and welding of high voltage cantilevers, both of which are caused by the charging and discharging of unwanted parasitic capacitances inherent to complementary relay structures. Devices are consequently damaged by high transient current and arc discharge between contacts. Several solutions are proposed and implemented to mitigate these issues, including minimization of unwanted capacitances, optimization of metallization scheme, introduction of intermediate operation cycles intended to increase time between state changes, and prevention of welding by preemptively charging capacitors to an intermediate voltage. To this effect, a detailed study of lifetimes for both single cantilevers and logic gate structures is presented comparing a variety of metallization schemes using Pt, Ti, TiN, and W, including their multilayer combinations. These varied optimization methods yielded single cantilever lifetimes of 1.74 billion cycles on average for devices with a Ti adhesion layer, a Pt primary layer, and a W surface layer to increase durability. Using the same metallization scheme, complementary logic structures achieved 0.6 million cycles on average. These results demonstrate the viability of robust N/MEMS based complementary logic circuits for safety critical control applications. 2024-0203
This chapter provides a comprehensive analysis of nanoelectromechanical systems (NEMS) switches as highly efficient switching devices. It explores the development of early automatic systems to modern silicon-based technologies. It highlights the advantages of NEMS switches over conventional semiconductor devices, highlighting features like low-power consumption, high ON-current, and ideal subthreshold slope. The chapter delves into various actuation mechanisms, fabrication techniques, and discusses development challenges such as scalability and integration. The text also explores the capabilities of NEMS switches in terms of energy efficiency, precision sensing, and improved performance in communication. It highlights the significant impact these switches can have on nanoelectronics.
We measure the stiction force using in-plane electrostatically actuated Si nanoelectromechanical cantilever relays with Pt contacts. The average current-dependent values of the stiction force, ranging from 60 nN to 265 nN, were extracted using the I DS vs V GS hysteresis curves, the cantilever displacement information from finite element method (Comsol Multiphysics) simulations, and the force distribution determined using an analytical model. It is shown that the stiction force is inversely and directly proportional to the contact resistance (R c) and drain-source current (I DS), respectively. Using the dependence of the stiction force on the contact current, we demonstrate the tuning of the voltage hysteresis for the same relay from 8 V to 36 V (equivalent to a stiction force of 70 nN to 260 nN, respectively). We attribute the stiction force primarily to the metallic bonding force, which shows a strong dependence on the contact current.
This study empirically investigates the influences of several parameters on surface morphology and etch rate in a high-aspect-ratio silicon etching process. Two function formulas were obtained, revealing the relationship between the controlled parameters and the etching results. All the experiments were conducted on an inductively coupled plasma system, using a Bosch process. The tested trenches’ width ranged from 15 to 1500 µm and their depth ranged from 50 to 500 µm, which covers nearly all the typical sizes of micromechanical devices in practical applications. The controlled parameters are etching chamber pressure, bias power, and gas flow rate. The parameters of surface morphology include sidewall angle, surface roughness, and sidewall condition. We tested how the controlled parameters can influence the surface morphology and etch rate and formulated assumptions to explain those relationships. Meanwhile, we utilized linear regression to obtain experiential function formulas of the relationships among etch depth, structure width, etching time, and passivation time, with a correlation coefficient higher than 0.99. Using these formulas, 12-µm-wide and 377-µm-deep (aspect ratio 31.4) trenches with sidewall angles of 89° were achieved. Additionally, this experience was applied as a critical structure in a gas turbine structure system.
This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.
While experiment, simulation, and theory all show that the gas breakdown voltage decreases linearly with gap distance for microscale gaps at atmospheric pressure due to the contribution of field emitted electrons, the continuing reduction in device size motivates a more fundamental understanding of gas breakdown scaling for nanoscale gaps. In this study, we measure current–voltage curves for electrodes with different emitter widths for 20–800 nm gaps at atmospheric pressure to measure breakdown voltage and assess electron emission behavior. The breakdown voltage [Formula: see text] depends more strongly on effective gap distance [Formula: see text] than the ratio of the emitter width to the gap distance. For 20 and 800 nm gaps, we measure [Formula: see text] V and [Formula: see text] V. Independent of emitter width, [Formula: see text] decreases linearly with decreasing [Formula: see text] for [Formula: see text] nm; for [Formula: see text] nm, [Formula: see text] decreases less rapidly with decreasing [Formula: see text] which may correspond to a change in the field enhancement factor for smaller gaps. While gas breakdown usually proceeds directly from field emission, as for microscale gaps, some cases exhibit space-charge contribution prior to the transition to breakdown, as demonstrated by orthodoxy tests. Applying nexus theory, we determine that the range of [Formula: see text] studied is close to the transitions between field emission and space-charge-limited current in vacuum and with collisions, necessitating a coupled theoretical solution to more precisely model the electron emission behavior. Implications on device design and an overall assessment of the dependence of emission and breakdown on gap distance are also discussed.
This manuscript focuses on Nano-Electro-Mechanical (NEM) relays with electrostatic actuation for advanced logic and memory applications. The use of Nano-Electro-Mechanical relays was recently proposed for digital logic circuits in order to overcome the fundamental energy-efficiency limitations that mainstream CMOS technology is currently facing. The cumulated benefits of essentially Zero Off-State current and ultimately abrupt DC switching characteristics enable alleviating the power-performance trade-off as the supply voltage VDD is reduced. Additionally, for some particular switch designs (e.g. free of dielectric layers), an increased resistance to ionizing radiations is also anticipated, making such components valuable for defense or aerospace applications.However, NEM relays have intrinsic limitations in terms of integration density, endurance and operation frequency. Therefore, rather than considering them as technology that could replace MOSFETs, we adopt an intermediate approach that consists in using NEM relays as a complement to CMOS circuits (e.g.: buffers, non-volatile elements for SRAM and CAM), which can be fabricated in a 3D co-integration scheme. This approach mitigates the area penalty issue.The thesis explores the strength and the weakness of NEMS relays and identifies applications for which hybrid NEMS/CMOS circuits are potentially interesting.This work includes the manufacturing of prototype devices designed to be proof of concept for the identified applications. At first, NV NEM relays design and dimensioning through modelling and simulations was performed. Then NV NEM/CMOS circuits were validated trough simulations. This was followed by the tapeout and the process integration of monolithically co-integrated NEMS above CMOS. After wafer processing the devices were electrically characterized.This all-inclusive works allows identifying some crucial challenges that NEMS relays still have to face.
In dry plasma silicon etching, it is desired to have a high etching rate, a high etching selectivity to mask material, a vertical or controllable sidewall profile, and a smooth sidewall. Since the standard Bosch process (switching between SF6 and C4F8 gases) leads to a wavy/rough sidewall profile, the nonswitching pseudo-Bosch process is developed to give a smooth sidewall needed for nanostructure fabrication. In the process, SF6 and C4F8 gases are introduced to the chamber simultaneously. Here, the authors show that by introducing a periodic oxygen (O2) plasma cleaning step, that is, switching between SF6/C4F8 etching and O2 cleaning, the silicon etching rate can be significantly improved (by up to ∼55%, from 139 to 216 nm/min) without any adverse effect. This is mainly because O2 plasma can remove the fluorocarbon polymer passivation layer at the surface. The etching and cleaning step durations were varied from 5 s to 40 min and from 0 to 60 s, respectively. The fastest etching rates were obtained when the cleaning step takes roughly 10% of the total etching time.
Microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS) switches are of interest for applications ranging from radio frequency (RF) communication circuitry to power surge protection to low power computing. Reliable operation of the switch contacts is critical. Many researchers have investigated the effect of different materials on reliability, but little work has been reported on the effects of process conditions. In this study, the effects of the angle of deposition incidence, the microstructure, the interface adhesion, the base pressure, and the process transferability have been evaluated in Pt-coated MEMS switches. Among them, base pressure attained prior to deposition was most important, while an interaction between electrode geometry and film microstructure was also identified to play a role. A lower base pressure (2•10⁻⁶ Torr) improved cycle count significantly while a higher base pressure (8•10⁻⁶ Torr) resulted in low cycle counts (10⁶ or less). Failure analysis indicated surface wear due to damage at a corner junction, where films deposited at different angles of deposition incidence meet. Mass spectroscopy analysis detected higher carbon content in Pt films with high base pressure. This suggests that grain boundaries weakened by impurity segregation exacerbated the geometric effect. Switches tested in a follow-up experiment, in which the base pressure was 5•10⁻⁷ Torr, again resulted in high cycle counts (330•10⁶), reinforcing the importance of achieving low base pressure in improving the mechanical reliability of the corner junction.
This paper presents the design, fabrication, and evaluation of electrostatically driven nanoelectromechanical (NEM) switches and logical gates, including NAND and NOR gates. The conformal deposition of tungsten (W) on high aspect ratio structures is investigated by selective W chemical vapor deposition (CVD) as an electrical contact material. The switching characteristics of the NEM switches, as well as their pull‐in voltages, are evaluated. Logical gates, including NAND and NOR gates, are formed by the four NEM switches consisting of four cantilevers, two input ports, two source ports, and an output. Devices are successfully fabricated by a combination of an electron beam lithography, a deep reactive ion etching, and a selective W CVD. The truth table operations for the NAND and NOR gates are examined and demonstrated in this paper.
This work reports a TiN coated contact implemented in a vertically actuated SiGe-based Nano-Electro-Mechanical (NEM) relay. It is shown that covering the bottom of the movable SiGe beam (the armature) with a TiN layer in the contact region will improve the contact performance of the relay with lowering the on-resistance, R ON , by around 4 orders of magnitude and by enhancing the number of switching cycles without degradation. This NEM relay provides an optimal combination of small motional volume (∼0.02µm 3 ) and long mechanical lifetime (> 10 10 in vacuum). Furthermore, with a total contact area of 0.01µm 2 (among the smallest reported so far), an on-resistance of ∼1MΩ has been achieved.
In this study, mechanical analysis of the air-gap breakdown with free spherical metal particle is conducted in a DC uniform field to address the problem of metal-particle pollution in DC gas insulation. The criterion and spacing of micro-discharge between the particle and electrode is calculated based on the analysis of electric-field distortion with a lifting particle by using the streamer theory. The gas-breakdown equation that considers the effects of free particle is modified with the new concept of equivalent radius, and the different breakdowns triggered by various sizes of aluminum or copper particles are analyzed in ramp voltages. Different states of particle lifting, direct breakdown, or moving breakdown are also considered. The concept of risky radius is also proposed. The breakdown process is observed using a high-speed camera, and the model is verified through experiments. The breakdown voltage of the moving particle is lower than the still particle's. Three breakdown regimes in the DC uniform field triggered by free metal particles were defined, among which the lifting-voltage breakdown occurs only when the particle is close to the upper electrode for the first time. The breakdown voltage showed a minimum value when the particle moved nearer to the risky radius. The proposed research provides fundamental basis in evaluating the dangerous level of free conducting particles within DC GIL as to improve the insulation design.
Since mechanical switches (relays) have zero off-state leakage and perfectly abrupt ON/OFF switching behavior, in principle they can be operated with a very small voltage swing and overcome the energy efficiency limit of CMOS technology. This paper discusses recent developments to address the remaining technical challenges for fully realizing the promise of ultra-low-power mechanical computing.
In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies.
Profile control in polysilicon etching with SF6/O2 and NF3/O2 gas mixtures has been explored as a function of feed gas composition, power, pressure and total flow.Polysilicon appears to etch anisotropically under certain anomalous combinations of these parameters, such as high power/dilute etchant gas composition, low power/high etchant gas composition and high power/high etchant gas composition.Very rapid etch rates (3.5 μm/min) and anisotropic etching were obtained simultaneously in SF6/O2 mixtures at 250 mtorr.In order to provide a rational for explaining these anomalies, a kinetic model for these plasmas has been developed which couples electron impact events in the plasma to gas-phase chemistry and surface reactions of the etching process.Peculiarities in the electron energy distribution function (EEDF) of these gas mixtures, determined by Boltzmann calculations, appear related to the anisotropy under dilute conditions.However, anisotropic etching observed at 250 mtorr and rich SF6 gas mixtures appears more related to anomalies in power deposition to the discharge, possibly including wave interactions or resonant processes.Comparisons between computer simulations and experimental results are presented.
This paper reports the design optimization of lateral nanoelectromechanical (NEM) relays for sub 1V actuation by COMSOL simulation with various materials and structures. Measured actuation voltages from fabricated relays showed good matching with simulation.
This paper presents techniques for designing nanoelectromechanical relay-based logic circuits using six-terminal relays that behave as universal logic gates. With proper biasing, a compact 2-to-1 multiplexer can be implemented using a single six-terminal relay. Arbitrary combinational logic functions can then be implemented using well-known binary decision diagram (BDD) techniques. Compared to a CMOS-style implementation using four-terminal relays, the BDD-based implementation can result in lower area without major impact on performance metrics such as delay, and energy (when the relays are scaled to small dimensions). Although it is possible to implement any combinational circuit with a single mechanical delay, the relay count can be significantly reduced for complex logic functions by allowing multiple mechanical delays.
Laterally actuated polycrystalline silicon nanoelectromechanical (NEM) relays with enhanced electrical properties are presented. Due to surface oxidation of polysilicon in room ambient conditions, the relays have a high contact resistance (> 1 GΩ) that requires high drain bias (3-5 V) to break through. The addition of a platinum sidewall coating reduces the on-resistance and the required drain bias to as low as 3 kΩ and 0.1 V, respectively. The platinum coating's stability is demonstrated by two tests: first, a contact-and-hold test where the relay passes current (~1μA) for up to 155 min and, second, a hot cycling test where the relay survives for over 10
8
cycles . The NEMS relays are simulated using finite-element analysis, and the models are verified against experimental tests. Furthermore, the relays are configured and tested as a 2 : 1 multiplexer to show their potential as a digital logic component.
The differences between Cl2 and F-based dry etching are compared in this article. Inductively coupled plasma sources have been used to generate plasmas using both Cl2 and SF6/C4F8 chemistries. Trenches etched using Cl2 suffered less aspect ratio dependent etching effects because the trenches can be etched at a much lower pressure than with F-based gases. A 1.4 μm wide, 65 μm deep trench can be obtained with an aspect ratio of 46 in 12 h. The average Si etch rate was 90 nm/min and the selectivity to electroplated Ni was 23. The sidewall was vertical and smooth and the trench openings were nearly the same width before and after etching. Adjacent trenches with 0.14 μm mask opening and 2 μm line width were etched using these two etching technologies. With Cl2 etching, a wider 0.25 μm trench opening, due to the mask erosion effect, with a depth of 5.6 μm was obtained in 50 min. However, the 0.33 μm undercut increased the trench opening to 0.8 μm for 10.7 μm deep trenches after the F-based etching for 55 min. The Si etch rate in a large open area using F-based etching was 1818 nm/min, which is much faster than 201 nm/min when Cl2 etching was used. However, the Si etch rate, 112 nm/min for Cl2- nf> and 195 nm/min for F-based gases, was similar when the trench opening was decreased to submicrometer dimensions. This shows that the Cl2 etching provides better dimension and profile control with comparable Si etch rate to F-based etching when etching submicrometer trenches. The loading effect using Cl2 chemistry is less than with F-based etching. The Si etch rate was 1.74 μm/min for ∼100% Si exposed area and 3.68 μm/min when the exposed Si area was ∼0% in F-based etching. Scalloping, which is a periodic undercut near the top of the sidewalls, disappeared when using an electroplated Ni mask. The size and period of the scalloped features decreased as the Si exposed area and etch time increased. © 2000 American Vacuum Society.
In this paper, we introduced for the first time the energy-reversible complementary nanoelectromechanical (ER CNEM) logic gates and demonstrated their superiority over the conventional relays in terms of voltage, energy, and reliability. The ER CNEM logic a promising candidate for low standby and low operating power applications.
Nanoelectromechanical (NEM) switches are similar to conventional semiconductor switches in that they can be used as relays, transistors, logic devices and sensors. However, the operating principles of NEM switches and semiconductor switches are fundamentally different. These differences give NEM switches an advantage over semiconductor switches in some applications--for example, NEM switches perform much better in extreme environments--but semiconductor switches benefit from a much superior manufacturing infrastructure. Here we review the potential of NEM-switch technologies to complement or selectively replace conventional complementary metal-oxide semiconductor technology, and identify the challenges involved in the large-scale manufacture of a representative set of NEM-based devices.
This paper reports on the modeling, fabrication, and testing of cantilever- and parallel plate-based laterally actuated platinum-coated polysilicon nanoelectromechanical (NEM) relays. The polysilicon acts as the structural layer, while the platinum serves as a conducting contact material, as well as a local routing layer. The two-part cantilever design utilizes a source made of a compliant beam in series with a stiff bridged perimeter electrode to reduce the secondary pull-in of the source to the gate. The parallel-plate-based relay also uses stiffened electrodes in addition to serpentine structures that reduce the actuation voltage. Overdrive gate voltage in excess of 100% without failure and sharp release of the relay from output are achieved for polysilicon relays with 50nm platinum coating and 500nm actuation gap.
The operation and performance of complementary nanoelectromechanical (CNEM) logic gates are investigated. NEMS structures featuring dimensions 2 to 3 orders of magnitude smaller than the present MEMS relays are considered. Various metals are benchmarked to silicon as the cantilever beam material. We show that the CNEM inverters featuring laterally actuated beams, 10 nm gap and low density materials such as Si or Al can achieve nanosecond pull-in delay and sub-0.1 fJ switching energy at VDD = 1.5 V while occupying an area as small as 0.03 mum2.
Plasma etching of Si in SF
- H M Anderson
- B K Smith
- R W Light