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Benchmarking Measurement-Based Large-Signal FET Models
for GaN HEMT Devices
Abstract — This paper compares the accuracy and attributes
of measurement-based large-signal FET models in the context of
GaN HEMT modeling. We compare three FET models that have
been implemented within PathWave Advanced Design System. In
particular, the benefits and drawbacks of using neural networks
to model the I-V and Q-V relations in a general way are
analyzed. This is done by characterizing a 150 nm gate length
8x50 µm GaN-on-SiC HEMT and extracting the respective FET
models based on DC-IV, small-signal, and large-signal data in
the device’s operating range. The three models are validated
and benchmarked at different operating conditions and higher
frequencies than their extraction frequency to show how neural
network technology can serve as a powerful tool for the accurate
modeling of thermal and trapping effects of GaN HEMTs.
Keywords — GaN HEMT, device modeling, linearity, neural
networks, thermal effects, trapping effects.
I. INTRODUCTION
In recent years, Gallium Nitride (GaN) technology has
become an appealing solution for various RF/mm-Wave
applications due to its ability to provide higher output power
than conventional III-V (e.g., Gallium Arsenide) and Silicon
semiconductors [1]. Nonetheless, GaN high-electron-mobility
transistors (HEMTs) are far from reaching their theoretically
achievable performance due to thermal and trapping effects,
which limit the output power, efficiency, and linearity, all of
which are critical performance metrics in power amplifiers
(PAs). The nonidealities found in existing commercial GaN
HEMT foundry processes make the design of GaN MMICs
a challenging task. As such, the ability to accurately model
these nonidealities has become increasingly important in the
design of high-power GaN MMICs at mm-wave frequencies
to reduce the number of design iterations.
For GaN technology to be readily adopted, an accurate
nonlinear large-signal model that captures thermal and trapping
effects is necessary to simulate DC, S-parameters, and
nonlinear figures of merit (FoMs) such as AM-AM/AM-PM
distortion, intermodulation distortion, EVM, and ACPR.
Measurement-based large-signal FET models are a particularly
attractive solution as they can capture the nonidealities (e.g.,
thermal and trapping effects) present in the device without
relying on physics-based equations. They are particularly
useful when good measurement data is available and it is not
possible to obtain a physics-based model of the device in use
[2]. In the present work, three measurement-based FET models
are validated and benchmarked in the context of GaN HEMT
modeling. These three models have been natively implemented
within PathWave Advanced Design System (ADS). All three
models are extracted and validated using the same data set,
which includes DC, S-parameter, and large-signal NVNA data
(although only two of the models require DC and S-parameter
data to be fully extracted).
The flow of this paper is organized as follows: Section
II introduces the three models used in this work. Section III
shows and describes the measurement data used to extract and
construct all three GaN HEMT models. The validation data to
benchmark all three models are shown in Section IV. Lastly,
Section V summarizes the paper.
II. MEASUREMENT-BASED MODELS
Several types of measurement-based models have been
implemented in the literature. These include empirical models
(e.g., fitting closed-form solutions to measurement data),
table-based models with spline interpolation, and neural
network-based models. In the present work, we evaluate three
models implemented natively in PathWave ADS. The first
model is a table-based model that is constructed from DC
and S-parameters [3]. The second model is based on neural
networks – it uses the non-quasi-static dynamics framework
of the first model along with neural networks to construct a
model with smoother constitutive relations (e.g., I-V and Q-V
relations) [4]. The third model is a neural network-based model
that is based on DC, small-signal, and large-signal NVNA data
taken at two different temperatures [5], [6]. All three models
are described in more detail below.
A. The Root Model
The Root model is a measurement-based table-driven
model that computes the state functions of measured raw
data and stores the values of these functions in tables, which
are then interpolated using built-in spline functions during
simulation [3]. A key advantage of the Root model is the
simplicity of the model extraction and generation procedure
since it only requires DC, S-parameters, and parasitic elements
to generate the model. However, a limitation of this model
is the interpolation from spline functions when generated
from noisy data. In such a scenario, the spline functions will
interpolate the noise in the data, leading to reduced accuracy
at lower amplitude signal levels in nonlinear simulations [4].
B. The NeuroFET Model
To solve the limitations of the Root Model, NeuroFET
replaces the spline functions with neural networks to
Rafael Perez Martinez*#, Masaya Iwamoto#, Jianjun Xu#, Philipp Pahl#, Srabanti Chowdhury*
*Department of Electrical Engineering, Stanford University, USA
#Keysight Laboratories, Keysight Technologies Inc., USA
{rafapm, srabanti}@stanford.edu
1
0 1 2 3 4 5
VDS (V)
0
135
270
405
540
675
810
945
JD(mA/mm)
(a)
VDS (V)
0 125 250 375 500
JD (mA/mm)
0
25
50
75
100
125
150
VDS = 20 V WG= 8x50 µm
fmax
fT
fT/fmax (GHz)
JD(mA/mm)
(b)
Fig. 1. Measured (a) ID-VDcharacteristics and (b) fT/fmax of seven
different 8x50 µm GaN-on-SiC devices from the same die. The error bars
denote the standard deviation and the lines show the average values.
generate constitutive relations that are smooth, infinitely
differentiable, and uniform approximations of the desired
device characteristics [4]. Similar to the Root Model,
NeuroFET employs the same framework/concepts, data, and
model generation infrastructure [7]. The main difference
between these models is that the model’s constitutive relations
are expressed analytically using bias-dependent functions
obtained from neural networks instead of using a table-based
approach along with interpolation. Therefore, the simulation
accuracy is improved at lower power levels, which is vital
when trying to simulate linearity metrics such as the output
third-order intercept point (OIP3).
C. The DynaFET Model
The third model explored is the DynaFET model, which
incorporates large-signal nonlinear vector network analyzer
(NVNA) data to account for nonlinear dynamic effects such
as thermal and trapping effects. When paired with DC and
S-parameter data, NVNA data provides valuable information
such as detailed large-signal waveforms which aid nonlinear
circuit modeling compared to models with data limited only
to DC and S-parameters [5], [6]. To fully extract this model,
measurement data at two or more different temperatures
are required. Similar to NeuroFET, DynaFET is a neural
network-based model, where the objective of the training
procedure is to identify constitutive relations such as the
gate/drain currents and charges. As such, DynaFET can be
thought of as a global solution that predicts DC, S-parameters,
large-signal nonlinearities (e.g., distortion, load-pull, and
PAE), and long-term memory effects without the need for
application-specific model tuning. One limitation of this model
is that it is inaccurate for FET switch designs since the model’s
formulation (e.g., trap definitions/calculations) does not apply
to switch applications. As such, the model primarily targets
PA applications [5], [6].
III. GANHEMTCHARACTERIZATION
The device chosen for the extraction of the three models
is a 150 nm gate length 8x50 µm GaN-on-SiC HEMT. Seven
different devices with the same geometry were measured
and characterized at room temperature (i.e., T = 25C) to
account for any variability in drain current (ID) and unity
PNA-X
DUT
Bias Tee Bias Tee
Cou pler Cou pler
Synchronized
Bias Suppl ies
PA
0.001 – 1 GHz
50 W
PA
0.08 – 1 GHz
150 W
Comb Gen.
Comb Gen.
Splitter
Rear Panel: 10 MHz Ref
DUT Pl ane
Fig. 2. Measurement setup for active source injection characterization with a
temperature-controlled wafer chuck and driving amplifiers to boost the internal
sources of NVNA.
0 5 10 15 20 25 30
VDS (V)
0
150
300
450
600
750
900
0 5 10 15 20 25 30
V
DS
(V)
-20
-15
-10
-5
0
Measured
DynaFET
NeuroFET
Root
(a)
(b)
JD(mA/mm)
JG(μA/mm)
VDS (V)
VG= -3 V to 0 V
Fig. 3. Measured and simulated (a) IDand (b) IGas a function of VDS at
room temperature for DynaFET, NeuroFET, and Root models. VGS is swept
from -3 V to 0 V.
current (fT) and unity power gain frequencies (fmax) as
seen in Fig. 1. The error bars denote the standard deviation
at each bias, while the lines show the average values. The
device with the average performance was then chosen as the
“golden device” for model extraction. Large-signal NVNA
measurements were taken at two different temperatures (T =
25C and 55C), various input power levels (ranging from
small-signal to large-signal conditions), and load impedances
(using active load pull) for a fundamental frequency of 100
MHz. This frequency was chosen as it is fast enough to
capture the transistor response in a low nanosecond regime
(i.e., 10-100x faster than pulsed IV measurements) while at the
same time supporting data collection up to the 20th harmonic.
The data acquisition was done using an automated, adaptive,
large-signal data acquisition software application, which is
part of the NVNA nonlinear measurement system [8]. The
hardware configuration for this setup is shown in Fig. 2.
Following the data acquisition of the large-signal NVNA
data, broadband S-parameters were measured from 50 MHz to
25 GHz for various bias conditions for model validation and
2
S21/14
S11 S22
14·S12
Measured
DynaFET
NeuroFET
Root
Fig. 4. Measured and simulated broadband S-parameters from 50 MHz to 25
GHz at VDS = 20 V and VGS = -2 V.
parasitic extraction. In particular, S-parameters were measured
under pinched-off and Cold FET conditions for parasitic
extraction (e.g., R/L’s) as well as an array of HEMTs with
different geometries for parasitic capacitance identification
via linear regression using the method described in [2]. The
thermal resistance of the GaN HEMT was also measured using
the method described in [9] as this parameter is needed for the
extraction of the DynaFET model.
Lastly, DC and S-parameter data for a fixed frequency
of 3.7 GHz with a DC power compliance of 5.5 W/mm
were taken as the last step for two different temperatures (T
= 25C and 55C) since any extreme operating conditions
can stress the device and change its characteristics. The DC
validation results for all three models are shown in Fig.
3. Excellent agreement between measured and simulated ID
and gate current (IG) is observed for all three models. It is
important to mention that the DynaFET extraction package has
a feature to add extrapolated data to account for self-heating
effects in the IV characteristics. Such a feature was applied
to the training data for extraction of both the NeuroFET and
DynaFET models, whereas the Root Model only used the raw
measured data. All three models were constructed using the
same data set, e.g., Root Model and NeuroFET using DC and
S-parameter data at room temperature, and DynaFET using
DC, S-parameter data, and large-signal data at 25C and 55C.
IV. BENCHMARKING AND MODEL VALIDATION
The measured and simulated S-parameters for the three
models at T = 25C are in good agreement over the entire
frequency and bias range where the model was extracted. For
the intended application bias point, the Root model was able to
achieve the best result, followed by the DynaFET model which
shows a few discrepancies for S12, and then NeuroFET, which
was slightly inaccurate for S12 and S21. This is shown in Fig.
4 for one bias point of interest (i.e., VDS = 20 V and VGS
= -2 V). However, outside the intended application point, the
Root model was less accurate, while DynaFET showed better
accuracy over the entire bias range.
-10 -5 0 5 10 15 20 25 30 35
Pout (dBm)
0
2.5
5
7.5
10
12.5
15
Measured
DynaFET
NeuroFET
Root
Gain (dB)
Pout (dBm)
f = 10 GHz
VDS = 20 V
VGS = -2 V
Fig. 5. Measured and simulated single-tone CW sweep gain versus output
power at 10 GHz under a 50 ⌦environment. The device was biased at VDS
= 20 V and VGS = -2 V.
-25 -20 -15 -10 -5 0 5 10
Pin (dBm)
-100
-80
-60
-40
-20
0
20
40
Measured
DynaFET
NeuroFET
Root
Pout (dBm)
Pin (dBm)
f = 10 GHz
Δf = 10 MHz
ZS= ZL= 50 Ω
1st
3rd
5th
Noise Floor
Fig. 6. Measured and simulated two-tone intermodulation nonlinear results
showcasing fundamental, third, and fifth-order intermodulation products for
f=10 GHz and f = 10 MHz under a 50 ⌦environment. The device was
biased at VDS = 20 V and VGS = -2 V.
Most importantly, large-signal nonlinear measurements
were performed to validate and benchmark the accuracy of
the three models. Fig. 5 shows the measured and simulated
continuous wave (CW) large-signal single-tone stimulus for a
frequency of 10 GHz under a 50 ⌦environment. All three
models predict the gain with good accuracy at low to medium
power levels. It is noted that the DynaFET model does a better
job of predicting the high-power-level regime of the device
(gain compression), whereas the Root and NeuroFET models
struggle to predict the compression characteristics of the device
at high power levels.
Two-tone intermodulation nonlinear measurements were
also performed to validate and benchmark each model’s
capacity to simulate and quantify intercept points (e.g, OIP3).
This measurement was done for a center frequency (fc) of
10 GHz with a frequency spacing (f) of 10 MHz under
a 50 ⌦environment and is shown in Fig. 6. It is observed
that the NeuroFET model predicts the device’s large-signal
intermodulation characteristics with better accuracy at all
power levels followed by DynaFET, and lastly the Root model.
The Root model shows poor accuracy at low power levels
as expected due to the interpolation issue from the spline
functions. Moreover, OIP3was measured as a function of
current density as shown in Fig. 7. The NeuroFET model
shows good agreement between measured and simulation data.
It is observed that the DynaFET model over-predicts OIP3at
0 50 100 150 200 250 300 350 400
JD (A/mm)
0
10
20
30
40
50
60
Measured DynaFET NeuroFET Root
f = 10 GHz, Δf = 10 MHz
VDS = 20 V
JD(mA/mm)
OIP3(dBm)
Fig. 7. Measured and simulated OIP3as a function of current density for
f=10 GHz and f = 10 MHz under a 50 ⌦environment.
low current density and underpredicts OIP3at high current
densities. Lastly, the Root Model predicts accurately OIP3at
low current densities. It is worth noting that the input power
level for which OIP3was extracted for the Root model was
much higher due to the inaccuracies at low power levels.
In terms of model accuracy, there exists a trade-off
between data acquisition complexity, extraction/training time,
and intended circuit applications. While all three models
were extracted using the same data set, both the Root and
NeuroFET models only require DC and S-parameter data
at room temperature as opposed to DC, S-parameter, and
NVNA data at two different temperatures for the DynaFET
model. This implies that it is not strictly necessary to have a
temperature-controlled chuck or an NVNA to extract the Root
and NeuroFET models. Most importantly, for the DynaFET
model to be extracted successfully, the device under test (DUT)
should be able to withstand (i.e., not degrade significantly)
strenuous large-signal stimuli under different loads as this data
acquisition process can take several hours or days. As such,
devices that have not been qualified to be “reliable” are not
good candidates for the DynaFET model. The training time
needed to extract the neural network-based models varies for
the NeuroFET and DynaFET models. With modern computing
resources, the NeuroFET model takes 2-3 hours to fully train
with IDtaking the longest. DynaFET takes a much longer time
(12-24 hours) due to the immense amount of NVNA data. On
the other hand, a Root model can be extracted in a matter of
seconds.
Lastly, amplifier applications that strictly require nonlinear
simulation results at high power levels will benefit greatly
from the DynaFET model. In addition, DynaFET is expected
to perform better under different load impedances as the model
was extracted using large-signal NVNA for a variety of load
impedances based on previous work shown [6]. However,
a good alternative for applications that require low-noise
amplifiers (LNAs), or switching applications are well-suited
using NeuroFET since the model’s formulation covers the
operating region for FET switch designs, and it also has
it captures with good accuracy the intermodulation products
under a 50 ⌦environment, which is needed for intercept point
simulations. The Root model can be used to check the accuracy
of the extrinsic parasitics for NeuroFET or DynaFET due to
its fast extraction time.
V. C ONCLUSION
This works provides a comparison of the accuracy and
attributes of three measurement-based large-signal FET models
natively implemented in ADS, specifically in relation to GaN
HEMT modeling. We test this by characterizing a 150 nm
gate length 8x50 µm GaN-on-SiC HEMT and extracting
three FET models from DC-IV, small-signal, and large-signal
data under the device’s operating range. The benefits and
drawbacks of each model are discussed and it is found that
DynaFET provides the best solution to large-signal GaN
PA design as it is able to capture trapping/thermal effects
in mature/reliably-qualified devices. NeuroFET is shown to
be a good alternative for LNAs and switches since the
model’s formulation also applies to FET switching applications
and it captures with good accuracy two-tone intermodulation
simulations. Both neural network-based models demonstrate
the effectiveness of neural network technology in the modeling
of GaN MMICs.
ACKNOWLEDGMENT
This work was supported in part by the Stanford Graduate
Fellowship (SGF). The authors are grateful to S. Cochran, E.
Schmidt, D. Root, and Keysight Technologies management for
their support.
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