Conference Paper

Design and implementation of high-performance CMOS D/A converter

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Abstract

In this paper we present the design and implementation of a high-performance digital-to-analog converter in a 3.3-V 0.6-um digital CMOS process. To reduce glitch energy and maintain speed and small chip area, we combine segmentation and binary weighting, as well as clock all the input data before driving bit switches and equalize the delay for all the circuit blocks. We also present a new layout style, which enhances matching and further reduces glitch energy. Measurement results are also included

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... There are publications on DACs [4][5][6][7][8][9][10][11][12][13], however most publications are focused on improving the static performance [4][5][6]. Some have reported the dynamic performance of DACs [7][8][9][10][11]. ...
... There are publications on DACs [4][5][6][7][8][9][10][11][12][13], however most publications are focused on improving the static performance [4][5][6]. Some have reported the dynamic performance of DACs [7][8][9][10][11]. In recent measurements we had an SFDR larger than 65dBc for a 10-bit 1.5V CMOS DAC [10]. ...
... Notice, that segmentation of MSBs can be used to reduce glitch energy [3,10,11]. However, this will not affect the modelling in this paper. ...
Article
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Digital-to-analog converters are crucial building blocks for telecommunication applications. For this kind of applications, the traditional static performance requirements do not apply. The dynamic performance is of the greatest importance. This paper discusses the aspects of the performance of CMOS digital-to-analog converters and models the influence of non-idealities of circuit components (such as output impedance, mismatch, circuit noise, etc.) on the frequency-domain performance. Both deterministic and stochastic effects are modeled. The purpose of this modeling is to provide an insightful design guide for high dynamic performance CMOS digital-to-analog converters.
... This is the role of the fourth block of the RMS-to-DC converter circuit. There are many methods to implement a current-mode DAC [53][54] [55]. Here, we apply the 8-bit binary-weighted currentsteering DAC in Fig. 3.11 to maintain circuit simplicity. ...
... The general structure of a binary weighted current-steering DAC is shown in Fig. 2-2 and discussed in [56,66]. The switches are controlled by the input bits, , where , and is the number of bits. ...
Chapter
In this chapter, we have discussed the design and implementation of current-steering DACs for wideband applications. Different structures have been outlined and for high-speed and high-resolution applications we have found the segmented DAC structure to be most suitable. A key design issue is to find the proper number of bits encode into a thermometer code or if multi-segmented structures are needed. We have shown how the performance of the converter depends on errors in the layout by comparing two similar DACs and highlighted the importance of high frequency poles in the output impedance of the unit current sources. We have shown that it is possible to reach an SFDR of over 75 dBc in a standard 3.3 V digital CMOS process and an SFDR of 65 dBc with a single 1.5-V supply voltage.
Chapter
In this chapter we have presented some of the basic DAC architectures that are suitable for high-speed and high-resolution applications. We have also outlined some possible techniques for implementation, such as the charge-redistribution, current-steering, etc. As a guidance, we have summarized a number of reported performances of DACs that are suitable for higher-speed applications in an overviewing figure and table.
Article
This paper describes a 3.3V-65MHz 12 BIT CMOS current-mode DAC designed with a 8 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch has been employed. The simulation results of the designed DAC show a conversion rate of 65MHz, a power dissipation of 71.7mW, a DNL of ?? 0.2LSB and an INL of ?? 0.8LSB with a single power supply of 3.3V for a 0.6ssm n-well CMOS technology.
Conference Paper
The influence of matching and output impedance on the performance of wideband current-steering DACs has been discussed. Both mathematical, simulated, and measured results was presented. Formulas and considerations were verified with simulations and measurements. A faster prediction of the performance using Matlab models can be achieved by using the error modeling. An SFDR larger than 74 dBc was measured at a sample frequency of 5 MHz. By reducing internal capacitance, simple improvement of matching, and reducing wire resistance, an SFDR improvement of 6-24 dB was found
Conference Paper
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In telecommunication applications the digital-to-analog converter is a crucial building block. For this kind of application dynamic performance, rather than static performance, is of the greatest importance. This paper discusses the aspects of the dynamic performance of digital-to-analog converters and models the influence of non-ideal components (such as output impedance, mismatch, circuit noise, etc.) on the dynamic performance. The purpose of this modelling is to provide a design guidance for high dynamic performance digital-to-analog converters
Article
Describes a DAC chipset developed specifically for telecommunication applications. The DAC chipset is implemented in Ericsson's in-house 0.6-micron CMOS process and operates on a supply voltage ranging from 1.5 V to 5 V with the number of bits ranging from 10 to 14 bits, and data rate from 50 Msamples/s@1.5 V to over 100 Msamples/s@5 V
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This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS converter. Matlab is used as a behavior-level simulator. In telecommunications applications, the frequency-domain parameters are of the greatest importance. Therefore, the characterization of the device and its performance is determined by frequency parameters such as the signal-to-noise ratio, spurious-free dynamic range, multitone power ratio, etc. In this paper, we show how these frequency-domain parameters are affected when mismatch errors and finite output impedance are applied to a current-steering CMOS DAC. We discuss how static performance is affected when changing the size of the errors and fundamental circuit parameters. The impact of dynamic errors such as glitches, slewing, and bit skew is discussed. Measurement results from 14-bit DACs are also shown to illustrate the correlation with the modeling
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A low-power, small-area, 10-bit D/A converter for cell-based IC and its design method are presented. An analytical design method which minimizes power dissipation and cell area of a current-cell D/A converter taking process variation into account is proposed. A 10-bit, 500-kHz D/A converter was implemented using the proposed method. A low power dissipation of 9.7 mW, a small area of 1.31 mm2, and a differential non-linearity of ±1/8 LSB has been achieved using a 0.8-μm CMOS process
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This paper describes the design, integrated circuit realization, and experimental characterization of a high-speed programmable interface system combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lines, with programmable delay length, together with four high-speed steering-current D/A converters with independent digitally-programmable gains. A demonstration prototype chip has been fabricated in a 1.2-μm digital CMOS technology. At 54 MHz conversion rate and digital delay lines clocked at 18 MHz, it consumes 115 mW for a full-scale output current of 13.3 mA at 5 V supply
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In order to achieve monotonicity and a high-speed performance, a current-cell matrix configuration and a parallel decoding circuit with one-stage latches have been used. A deglitching circuit has been introduced in the decoding stages to guarantee a low glitch energy. P-channel devices used as current sources ensure a low noise level and a ground-referenced voltage output in a doubly terminated 75-Ω transmission line. Experimental results have shown that the maximum conversion rate is 130 MHz and the integral and differential linearity errors are less than 0.5 LSB. The maximum glitch energy is 50 pS-V. The DAC has been developed in a 1-μm digital/analog CMOS technology. The entire circuit dissipates 150 mW at a 130-MHz conversion rate while operating from a single 5-V power supply
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A 10-b binary-weighted D/A digital-to-analog converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8-μm double-metal CMOS technology and the chip area is 0.4 mm2. This particular converter was realized by constructing the bit currents through a careful combination of unit current sources and by limiting the driving voltage on the gates of the current switches