In this paper we present the design and implementation of a
high-performance digital-to-analog converter in a 3.3-V 0.6-um digital
CMOS process. To reduce glitch energy and maintain speed and small chip
area, we combine segmentation and binary weighting, as well as clock all
the input data before driving bit switches and equalize the delay for
all the circuit blocks. We also present a new layout style, which
enhances matching and further reduces glitch energy. Measurement results
are also included