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Securing AES Designs Against Power Analysis Attacks: A Survey
Abstract
With the advent of Internet of Things (IoT), the call for hardware security has been seriously demanding due to the risks of side-channel attacks from adversaries. Advanced Encryption Standard (AES) is the de facto security standard for such applications and needs to ensure a low power, low area and moderate throughput design apart from providing high security to these devices. Substitution-box (S-box), being the core component of AES, has always drawn the attention of the cryptographic community. A chronological development of the S-box over a period of 20-years since the inception of AES is presented. This paper provides the first comprehensive review of the state-of-the-art S-box design techniques, identifying current advancements and analysing their impact on gate count, area, maximum frequency of operation, throughput and power. The other goal of the survey is to study the countermeasures designed for AES to protect it against side-channel attacks. In particular, we consider the power analysis attacks, and the countermeasures are investigated in terms of their security metrics and design overheads, such as area, power, and performance. The countermeasures are based on hiding or masking approaches depending on their design principle. Similar to the S-box survey, a chronological development of the countermeasures since the discovery of power analysis attacks in 1999, is presented. Finally, we suggest some open research gaps and possible direction of research in terms of S-box and countermeasure designs.
... and is projected to reach 1 trillion users by 2025 [3], [4]. IoT devices are categorized into architecture layers concerning the restrained proficiency of their computational power, memory utilization, and internal storage. ...
... This work extends the lightweight AES implementation for FPGA and ASIC in the available literature [58], which discusses only general security parameters. In addition, 70% of IoT devices undergo data attacks [19], which address Side-Channel Analysis (SCA) fault attacks, with a particular focus on the chronological development of successful intentional SCA and DFA attacks performed on AES implementations in FPGA and ASIC hardware, unlike [4], which covers unintentional SCA power analysis attacks (PAA). The passive-natured SCA relies on environmental observations, such as power consumption or electromagnetic emissions, and typically requires specialized setups for effective monitoring. ...
... Singha et al. [4] discussed SCA-based power analysis attack (PAA) on AES general hardware with hiding-and masking-based countermeasures. In addition, this paper presents a chronological discussion of AES S-Box optimization designs categorized as low-area, high-speed, lowpower, and efficient. ...
With the increasing interconnectivity of devices, the Internet of Things (IoT) has revolutionized the industry and daily life. However, the proliferation of IoT devices has also increased security risks, necessitating robust protection mechanisms for sensitive data and critical infrastructure. The Advanced Encryption Standard (AES) remains the benchmark for securing IoT systems while balancing low power consumption, minimal area usage, and moderate throughput with high security. This paper offers a comprehensive review of the latest lightweight AES architectural designs, including optimizations to the Substitution Box (S-Box), Sub-Bytes, Shift Rows, Mix Columns, and Add Round Key steps, assessing their impact on gate count, area, maximum frequency, power consumption, and throughput in field programable gate arrays (FPGA) and Application-specific integrated circuit (ASIC) implementations. In addition, this study addresses vulnerabilities in lightweight AES cryptographic hardware to side-channel attacks (SCA), specifically focusing on Differential Fault Analysis (DFA). Furthermore, the analysis explored fault scenarios, rounds, and injection positions to evaluate fault severity. Countermeasures to DFA are reviewed, emphasizing fault detection methods, error detection levels, protection positions, and associated design overheads such as area, frequency, and throughput penalties, with special consideration for resource-constrained IoT devices. This study identifies critical gaps in lightweight AES and security challenges while discussing countermeasures that balance security with design efficiency. Finally, this study provides valuable insights for finding research directions to strengthen the robustness of AES in lightweight IoT environments.
... The warp scheduler rapidly switches between warps to cover extended latency operations. The GPU programming model exposes fine-grained data parallelism via languages like CUDA and OpenCL [6]. Kernels specify the computation, while launch configurations map threads to coordinate parallel execution. ...
... The implications of these side channels are far-reaching, enabling adversaries to steal secrets from computations co-resident via GPU simultaneous multithreading. As authors in [6] summarise, attackers can break application isolation, extract AES keys, and leak data across virtual machines in cloud environments. Such demonstrated attacks highlight the need for robust defences to GPU architectures. ...
... The selection of the S-box should be taken wisely for area-efficient AES designs [40], [10], [41], as the S-box contributes to the majority of the area. Singha et al. [42] provide a literature survey of numerous S-box designs based on various design techniques like normal basis, polynomial basis, and LUT-based. The LUT-based Sbox is commonly used in AES designs because of its ease of implementation, but it occupies a humongous area, making these designs unsuitable for resource-constrained IoT devices. ...
With the advancement of IoT edge devices, the threat to sensitive data processed at these devices is increasing. This research aims to enhance processor’s built-in resilience against power analysis attacks (PAA) by expanding pipeline stages, employing diverse pipeline techniques, and integrating additional features. The paper proposes 32-bit RISC-V core micro-architectures with inbuilt cryptographic capabilities, extending the RISC-V ISA with custom AES instructions to reduce energy consumption, code size, and encryption time compared to software AES solutions. An area-efficient 128-bit, 12-clock AES based on the Masoleh S-box is integrated into the RISC-V core, resulting in low area and power overheads. Two cores are presented: Core1, a 3-stage pipelined core with a software pause, and Core2, a 4-stage pipelined core with a hardware pause for securing data with AES instructions. Despite their vulnerabilities, the integration of AES with RISC-V architecture significantly improves their intrinsic resilience against PAA. This work analyses the vulnerability and improvement in intrinsic resilience of these cores to side-channel attacks, the impact of hardware versus software pause and the effect of pipeline stages on security metrics. The proposed designs are validated on a Xilinx Basys3 FPGA and developed in UMC 65 nm technology node. Power traces generated during AES encryption are extracted using Synopsys PrimeTime PX and analyzed with a MATLAB power attack model to successfully recover all key bytes. Core1 and Core2 achieved higher throughput of 2.02× and 2.83×, respectively, than the Arm CryptoCell312. Core2’s added circuits for hardware pause and increased number of pipeline stages significantly boost performance and enhance security against power attacks, with only a modest increase in area and power consumption.
... Since the release of the AES standard [14], the optimization of this circuit gained particular interest from researchers, because it is the most expensive in terms of area and critical delay among all the operations of the AES algorithm. All the main works typically converge on solutions based on field arithmetic [19,20] instead of solutions based on Look-up Tables (LUTs), because they lead to more compact and more efficient implementations on standard-cell technologies. Anyway, in recent years the trend inverted for FPGA implementations thanks to technological advances on these devices [21], and we opted for this last. ...
In the last decades, the space sector has been the subject of significant technological improvements and investments from both government agencies and private companies, generating an increase in data rates and volumes of exchanged data. Accordingly, the security threats and the number of documented cyberattacks have grown. In order to meet the requirements of space applications, the Consultative Committee for Space Data Systems (CCSDS) has issued and maintained a series of reports and recommendations over the years, including a set of standards aimed at efficiently exploiting the communication channels. In this work, we present the implementation of an Advanced Encryption Standard – Galois/Counter Mode (AES-GCM) core on space-grade FPGAs, that is compliant with the latest CCSDS security standards and outperforms the state-of-the-art in terms of resource efficiency.
... The Advanced Encryption Standard (AES) [1] was released by the National Institute of Standards and Technology (NIST) and represents the de-facto standard for symmetric-key encryption, also because of its efficiency and performance [2]. Indeed, it is employed in several application fields such as High-Performance Computing [3,4] and Automotive Security [5], and it is going to be used in the coming decades because of its resistance against Post-Quantum Cryptography [6]. ...
The Advanced Encryption Standard (AES) is widely accepted as the de-facto standard for symmetric-key encryption, and it is going to be used in the coming decades because of its resistance against Post-Quantum Cryptography. For this reason, it is the subject of many research works, and almost all converge on the usage of composite/tower fields for the hardware implementation of the S-box, the most expensive circuit in terms of both area and critical delay. Anyway, the debate is still open on applying isomorphic fields also to the other AES algorithm operations. In the attempt to give an answer, it is analyzed the application of the two approaches to the most recent and performing solutions from the state-of-the-art with the synthesis of the corresponding circuits on a 7 nm standard-cell technology. In addition, the presented work constitutes also a guideline for implementing hardware AES modules that execute all operations over composite/tower fields.
Cryptography is an essential part of every device involved in the IoT since it ensures the protection of the data against adversaries. The software and hardware implementations of cryptographic algorithms have unwanted leakages that can be leveraged to extract the secret key of the device by a type of attack, namely side-channel attack. This work explores a two-share threshold implementation-based AES hardware accelerator, which is the most efficient technique to withstand first-order power analysis attack with reasonable overhead. The developed ASIC is targeted to work at a frequency of 50 MHz and taped out using semiconductor laboratory 180 nm technology.
Profiled side-channel analysis presents a significant risk to embedded devices in Internet of Things (IoT). Typically, a single trace is insufficient to successfully key recovery in practical scenarios. It still requires several traces based on Bayes’ posterior probability. In this paper, we introduce a chosen-plaintext strategy into the deep learning-based profiled attacks to improve the attack efficiency. Firstly, we present a general strategy to profile the leakage model by exploiting the sensitivity analysis and clustering analysis. The leakage model derived from Deep Neural Network is to characterize the leakage of the target algorithm. Secondly, we propose an adaptive chosen-plaintext method in the deep learning-based attack, transforming the conditional probability distribution of the leakage into the entropy of the key candidates under the profiled leakage model. Finally, we evaluate the efficiency of the attack by practical measurements. The results demonstrate that the proposed method requires fewer traces to retrieve the key of AES on devices of different types, e.g., Smartcard, FPGA, and ARM. Moreover, our attack improves the attack efficiency on masked implementations.
Side-channel analysis attacks have become the primary method for exploiting the vulnerabilities of cryptographic devices. Therefore, focusing on countermeasures to enhance the security level of these implementations evolves even more urgently. This article proposes a time-based hiding countermeasure by using spread-spectrum signals. In our RISC-V system on chip (SoC), cryptographic accelerators are given by random dynamic frequency-hopping signals. We found 223 available parameter sets for a Xilinx Mixed-Mode Clock Manage primitive in spread spectrum mode and achieved better effectiveness in the occupied bandwidth (OBW) metric. The mixed mode clock managers (MMCMs) output signal and the range of frequencies within the spread will be changed randomly, resulting in multiple clocks for individual encryption. The effectiveness of this proposal is demonstrated by conducting realistic side-channel attacks (SCAs) and state-of-the-art leakage assessment methodologies on the well-known data encryption standard, i.e., the Advanced Encryption Standard (AES) accelerator. Even though we used up to five million power traces, the test results show that our defense can stand up to a regular correlation power analysis (CPA) attack as well as alignment preprocessing methods, like CPA attacks that use a sliding window or an amplitude peak location algorithm. Furthermore, the
t
-test methodology cannot detect any first-order information leakage in five million traces; meanwhile, the deep learning leakage assessment (DLLA) requires nearly one million power traces in the training test to detect leakage points.
Advanced Encryption Standard’s (AES) vulnerabilities surfaced with Power Side Channel Attacks (PSCA). Enhancing security by adding extra countermeasure circuitry introduces significant hardware overheads, which are impractical for resource-constrained Internet of Things (IoT) edge devices. This study proposes an alternative approach, focusing on the AES design itself to enable lightweight countermeasures. Targeting the SubBytes round operation as the vulnerable point, the operation is split across different clock cycles to minimize side-channel information leakage. We investigated 12-clock, 22-clock, 42-clock, 82-clock, and 162-clock AES designs among which the 82-clock version stands out as the optimal choice, providing efficient hardware resource utilization. Evaluation using hardware security metrics, such as Measurements To Disclose (MTD) and Signal-to-Noise Ratio (SNR), confirms its superior security and reduced information leakage compared to other designs. Power traces for attacks are generated on both Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) platforms, maintaining a consistent 16 MHz design frequency with traces sampled at 1 GSa/s.
To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this convergence poses a significant security challenge, as adversaries can exploit it to extract unauthorized information, compromise system performance, and obtain secret keys. Meanwhile, traditional CMOS features have limitations in addressing hardware vulnerabilities and security threats, so promising post-silicon technologies offer potential solutions. Beyond-CMOS technologies offer avenues to fortify hardware security through distinct physical properties and nontraditional computing paradigms. These advancements bolster authentication processes, enhance key generation mechanisms, ensure hardware integrity and fortify resilience against side-channel attacks, hardware Trojans and quantum-resistant cryptography in securing hardware systems. This article provides a detailed review of hardware security, encompassing the identification and mitigation of threats, the implementation of robust countermeasures, the utilization of innovative primitives, countermeasures, various methodologies and distinct features offered by emerging technologies to resist hardware threats.Moreover, strategies to address challenges, explore future directions, and outline plans for achieving further research outcomes have been put forth in this field.
Deep Reinforcement Learning (DRL) has numerous applications in the real world thanks to its ability to achieve high performance in a range of environments with little manual
oversight. Despite its great advantages, DRL is susceptible to adversarial attacks, which precludes its use in real-life critical systems and applications (e.g., smart grids, traffic controls, and autonomous vehicles) unless its vulnerabilities are addressed
and mitigated. To address this problem, we provide a comprehensive survey that discusses emerging attacks on DRL-based systems and the potential countermeasures to defend against these attacks. We first review the fundamental background on DRL and present emerging adversarial attacks on machine learning techniques. We then investigate the vulnerabilities that an adversary can exploit to attack DRL along with state-of-the-art countermeasures to prevent such attacks. Finally, we highlight open issues and research challenges for developing solutions to deal with attacks on DRL-based intelligent systems.
In this paper we consider various methods and techniques to find the smallest circuit realizing a given linear transformation on n input signals and m output signals, with a constraint of a maximum depth, maxD, of the circuit. Additional requirements may include that input signals can arrive to the circuit with different delays, and output signals may be requested to be ready at a different depth. We apply these methods and also improve previous results in order to find hardware circuits for forward, inverse, and combined AES SBoxes, and for each of them we provide the fastest and smallest combinatorial circuits. Additionally, we propose a novel technique with “floating multiplexers” to minimize the circuit for the combined SBox, where we have two different linear matrices (forward and inverse) combined with multiplexers. The resulting AES SBox solutions are the fastest and smallest to our knowledge.
Hardware masked AES designs usually rely on Boolean masking and perform the computation of the S-box using the tower-field decomposition. On the other hand, splitting sensitive variables in a multiplicative way is more amenable for the computation of the AES S-box, as noted by Akkar and Giraud. However, multiplicative masking needs to be implemented carefully not to be vulnerable to first-order DPA with a zero-value power model. Up to now, sound higher-order multiplicative masking schemes have been implemented only in software. In this work, we demonstrate the first hardware implementation of AES using multiplicative masks. The method is tailored to be secure even if the underlying gates are not ideal and glitches occur in the circuit. We detail the design process of first- and second-order secure AES-128 cores, which result in the smallest die area to date among previous state-of-the-art masked AES implementations with comparable randomness cost and latency. The first- and second-order masked implementations improve resp. 29% and 18% over these designs. We deploy our construction on a Spartan-6 FPGA and perform a side-channel evaluation. No leakage is detected with up to 50 million traces for both our first- and second-order implementation. For the latter, this holds both for univariate and bivariate analysis.
Canright S-box has been known as the most compact S-box design since its introduction back in CHES’05. Boyar-Peralta proposed logic-minimization heuristics that could reduce the gate count of Canright S-box from 120 gates to 113 gates, however synthesis results did not reflect much improvement. In CHES’15, Ueno et al. proposed an S-box that has a slightly higher area, but significantly faster than the previous designs, hence it was the most efficient (measured by area×delay) S-box implementation to date. In this paper, we propose two new designs for the AES S-box. One design has a smaller implementation area than both Canright and the 113-gate S-boxes. Hence, our first design is the smallest AES S-box to date, breaking the 13 years implementation record of Canright. The second design is faster and smaller than the Ueno S-box. Hence, our second design is both the fastest and the most efficient S-box design to date. While doing so, we also propose new logicminimization heuristics that outperform the previous algorithms of Boyar-Peralta. Finally, we conduct an exhaustive evaluation of each and every block in the S-box circuit, using both structural and behavioral HDL modeling, to reach the optimum synergy between theoretical algorithms and technology-supported optimization tools. We show that involving the technology-supported CAD tools in the analysis results in several counter-intuitive results.
In vehicular networks, Radio frequency (RF) jamming attacks are considered as a major threat to the availability of control channel. In particular, vehicles may not be able to receive control messages from roadside units (RSUs) due to persistent interference in the control channel, which may claim human lives and result in significant economic losses. In this paper, a cooperative anti-jamming beamforming scheme is proposed to address the control channel jamming problems in vehicular networks. This scheme utilizes spatial diversity provided by the multi-antenna RSU and relay vehicles to improve the transmission reliability of downlink control messages. In addition, to address the additive effects of the jamming signals and the inter-group interference, the relay selection problem and the beamformer design problem are jointly considered, which is modeled as a mixed integer nonlinear programming (MINLP) problem. Then, we address this challenging problem by relaxing it into a series of convex sub-problems via the semi-determined relaxation (SDR) and convex-concave process (CCP) methods, and then propose to solve these convex sub-problems iteratively. The simulation results show that our proposed method convergences rapidly, and compared to the benchmark schemes, significant performance gains can be observed.
This article demonstrates enhanced power (P) and electromagnetic (EM) side-channel analysis (SCA) attack resistance of standard (unprotected) 128-bit advanced encryption standard (AES) engines with parallel (P-AES, 128-bit) and serial (S-AES, 8-bit) datapaths and a 128-bit SIMON engine with the bit-serial (1-bit) datapath by an on-die security-aware all-digital low-dropout (DLDO) regulator. The proposed DLDO improves SCA resistance using control-loop-induced perturbations in a nominal DLDO, enhanced by a random switching noise injector (SNI) by power-stage control and a randomized reference voltage (R-VREF) generator coupled with all-digital clock modulation (ADCM). SCA performed on the measured power/EM signatures acquired from a 130-nm CMOS testchip demonstrates up to 25x reduction in test vector leakage assessment (TVLA) leakage for P-AES and 3579x, 2182x, and 500x increase in minimum-traces-to-disclose (MTD) 80% of the subkeys for P-AES, S-AES, and SIMON cores, respectively, with respect to correlation power analysis (CPA) and correlation EM analysis (CEMA).
Computationally-secure cryptographic algorithms implemented on a physical platform leak significant "side-channel" information through their power supplies. Correlational power attack is an efficient power side-channel attack (SCA) technique, which analyzes the statistical correlation between the estimated and the measured supply current traces to extract the secret key. The existing power SCA countermeasures are mainly based on reducing the SNR of the leaked information, power balancing, or gate-level masking, each of which introduces significant power, area or performance overheads, which calls for an efficient generic countermeasure. This paper presents ASNI: Attenuated Signature Noise Injection, which is an energy-efficient generic countermeasure, and shows SCA resistance on the AES-128 encryption as an application. ASNI uses a shunt low-drop-out (LDO) regulator to suppress the AES current signature by >200$x in the supply current traces. The shunt LDO has been fabricated and validated in 130 nm CMOS technology. System-level implementation of the ASNI, with the AES-128 core operating at 40 MHz, shows that the system remains secure even after 1 M encryptions, with ~ 25x reduction in power overhead compared to that of noise addition alone.
Side-channel attacks represent a powerful category of attacks against cryptographic devices. Still, side-channel analysis for lightweight ciphers is much less investigated than for instance for AES. Although intuition may lead to the conclusion that lightweight ciphers are weaker in terms of side-channel resistance, that remains to be confirmed and quantified. In this paper, we consider various side-channel analysis metrics which should provide an insight on the resistance of lightweight ciphers against side-channel attacks. In particular, for the non-profiled scenario we use the theoretical confusion coefficient and empirical optimal distinguisher. Our study considers side-channel attacks on the first, the last, or both rounds simultaneously. Furthermore, we conduct a profiled side-channel analysis using various machine learning attacks to recover 4-bit and 8-bit intermediate states of the cipher. Our results show that the difference between AES and lightweight ciphers is smaller than one would expect, and even find scenarios in which lightweight ciphers may be more resistant. Interestingly, we observe that the studied 4-bit S-boxes have a different side-channel resilience, while the difference in the 8-bit ones is only theoretically present.
With the advancement of technology in the last few decades, leading to the widespread availability of miniaturized sensors and internet-connected things (IoT), security of electronic devices has become a top priority. Side-channel attack (SCA) is one of the prominent methods to break the security of an encryption system by exploiting the information leaked from the physical devices. Correlational power attack (CPA) is an efficient power side-channel attack technique, which analyses the correlation between the estimated and measured supply current traces to extract the secret key. The existing countermeasures to the power attacks are mainly based on reducing the SNR of the leaked data, or introducing large overhead using techniques like power balancing. This paper presents an attenuated signature AES (AS-AES), which resists SCA with minimal noise current overhead. AS-AES uses a shunt low-drop-out (LDO) regulator to suppress the AES current signature by 400x in the supply current traces. The shunt LDO has been fabricated and validated in 130 nm CMOS technology. System-level implementation of the AS-AES along with noise injection, shows that the system remains secure even after 50K encryptions, with 10x reduction in power overhead compared to that of noise addition alone. \c{opyright} 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Structured query language (SQL) has emerged as one of the most used databases, serving an array of Internet-of-Things (IoTs)-enabled services including web-transactions, grid networks, industrial activity log and proactive decision systems, smart-home, financial transactions, business communication etc. With high pace increase in SQL-driven IoT applications, the threat of SQL-injection attacks (SQLIAs) at the middleware layer has increased significantly. To address such issues, machine learning-based SQLIA-prediction systems are proposed; however, majority of the existing methods are found limited in terms of intrusion detection accuracy because of their complete-reliance on structural features and inferior learning model(s). On the contrary, intruders these days intrude the system by mimicking the normal queries and hence confuses most of the classical learning-based methods. To alleviate such problems, this article emphasizes on exploiting semantic features along with the state-of-art highly robust computing environment. We proposed a robust semantic query-featured ensemble learning model for SQLIA prediction. Unlike classical (query's) template-matching or term-assessment-based methods, our proposed SQLIA-prediction model exploits latent semantic features from large SQL-queries to train an ensemble learning model that classifies each query as the normal query or the SQLIA query. Functionally, it performs preprocessing over large set of SQL-queries using count-vectorizer and stopping word removal. Subsequently, it applies Word2Vec feature extraction method over each query using continuous bag of words (CBOW) and N-skip gram (SKG) algorithms, which obtained CBOW and SKG semantic features from each SQL-query. The extracted features were processed for data resampling so as to alleviate the problem of class-imbalance and skewness. To alleviate redundant computation, two feature selection algorithms named Mann-Whitney significance predictor test and principal component analysis were applied over the resampled features. Moreover, to eliminate over-fitting and convergence problem, Min-Max normalization was performed over the selected features which were later processed for learning using a state-of-art robust heterogeneous ensemble learning model. Unlike standalone classifier-based SQLIA, the proposed learning-model employed a set of nine base classifiers designed to serve maximum voting ensemble-based prediction. The proposed ensemble-learning method classified each SQL-query as the normal-query or the SQLIA-query. Simulation results affirmed superiority of the proposed SQLIA prediction model in terms of accuracy (98%), F-Score (0.989), AUC (0.999) signifying its efficacy toward real-world SQL-driven IoT-ecosystems.
This article investigates secure consensus of linear multiagent systems under event-triggered control subject to a scaling deception attack. Different from probabilistic models, a sequential scaling attack is considered, in which specific attack properties, such as the attack duration and frequency, are defined. Moreover, to alleviate the utilization of communication resources, distributed static and dynamic event-triggered control protocols are proposed and analyzed, respectively. This article aims at providing a resilient event-triggered framework to defend a kind of sequential scaling attack by exploring the relationship among the attack duration and frequency, and event-triggered parameters. First, the static event-triggered control is studied, and sufficient consensus conditions are derived, which impose constraints on the attack duration and frequency. Second, a state-based auxiliary variable is introduced in the dynamic event-triggered scheme. Under the proposed dynamic event-triggered control, consensus criteria involving triggering parameters, attack constraints, and system matrices are obtained. It proves that the Zeno behavior can be excluded. Moreover, the impacts of the scaling factor, triggering parameters, and attack properties are discussed. Finally, the effectiveness of the proposed event-triggered control mechanisms is validated by two examples.
A side-channel attack (SCA) hardened AES-128 and RSA crypto-processor in 14-nm CMOS with measured resistance to correlation power/electromagnetic analysis (CPA/CEMA) in both time and frequency domains is demonstrated. While previously reported linear low-dropout regulators (LDOs) offer improvements in minimum-time-to-disclose (MTD) of extracted key bytes in the time domain, their transformations are less effective against frequency-domain attacks. This article describes a non-linear digital LDO (NL-DLDO) with control loop randomizations that bolster SCA resistance in the frequency domain. The NL-DLDO cascaded with an AES engine augmented with arithmetic countermeasures enables
improvement in MTD, with no CPA/CEMA/DNN attacks detected after 1-B encryptions, with 8% power and 10% area overheads incurred by arithmetic techniques. The RSA-4K crypto-processor implements exponent magnitude and timing randomizations along with dynamic memory addressing to mitigate time- and frequency-domain attacks. The countermeasures enable
suppression in means separation in current/EM magnitudes from 3.1 mV to
, reducing attacker’s accuracy to an ineffective random guess classification, while limiting area and performance overheads to < 0.05% and 3.25%, respectively.
Mathematically secure cryptographic algorithms, when implemented on a physical substrate, leak critical “side-channel” information, leading to power and electromagnetic (EM) analysis attacks. Circuit-level protections involve switched capacitor, buck converter, or series low-dropout (LDO) regulator-based implementations, each of which suffers from significant power, area, or performance tradeoffs and has only achieved a minimum traces to disclosure (MTD) of
10M
till date. Utilizing an in-depth white-box model, this work, for the first time, focuses on signature suppression in the current domain, which provides an
enhancement in MTD, leading to orders of magnitude improvement in both power and EM side-channel analysis (SCA) immunities. Using a combination of current-domain “signature attenuation” (CDSA) along with local lower level metal routing, the critical correlated information in the crypto current is significantly suppressed before it reaches the supply pin. Especially, to prevent the EM leakage from its source (metal layers carrying the correlated crypto current acting as antennas), this work embraces lower level metal routing of the CDSA embedding the crypto-IP so that the signature becomes highly suppressed before it passes through the higher metal layers (which radiates significantly) to connect to the external pin. The 65-nm CMOS test chip contains both protected and unprotected parallel AES-256 implementations, running at a clock frequency of 50 MHz. Test vector leakage assessment (TVLA) on the protected CDSA-AES, demonstrated with on-chip measurements for the first time, shows that the higher level metal layers leak significantly more compared with the lower level metal routing. Correlational power and EM analysis (CPA/CEMA) attacks on the unprotected implementation were able to extract the secret key within
8k
and
12k
traces, respectively, while the protected CDSA-AES could not be broken even after
1B
encryptions for both power and EM SCA, evaluated both in the time and frequency domains, showing an improvement of
over the prior state-of-the-art countermeasures with comparable power and area overheads.
Small-footprint implementations of the advanced encryption standard (AES) algorithm are of interest in resource-constrained applications like Internet of Things (IoT). Symmetries in AES allow the datapath to be scaled down to the S-Box width of 8 bits, but the ShiftRows operation leads to a potential data hazard that must be avoided. The common method for resolving the ShiftRows hazard wastes power by moving data through a sequence of pipelined registers. We present in this article a novel 8-bit AES architecture that solves data movement inefficiencies by renaming registers and saves clock power with a single state update per AES round. We then extend register renaming to include microarchitectural randomization to mitigate susceptibility to side-channel attacks, which are a concern especially for low power implementations of AES. We fabricate and evaluate our designs in a commercial 16-nm FinFET technology. Testchip measurements show that the register renaming architecture encrypts data at 0.55 pJ/bit at nominal voltage, a 2.2x improvement over a state-of-the-art reference 8-bit design implemented in the same technology. Side-channel evaluation indicates that the randomized variant of register renaming significantly reduces vulnerability to differential power analysis (DPA).
Aimed at improving the resistance against power analysis attacks, a systematic and architectural design approach for multicore processors is proposed in this article and is demonstrated in an eight-core prototype platform with low performance overhead and hardware cost. In order to introduce randomness in both the time dimension and the amplitude dimension and make realignment extremely difficult, the proposed multicore platform leverages several methods together, such as random task scheduling (RTS), random insertion of operations (RIO), and frequency and phase randomization (FPR). Moreover, a power state monitoring and control (PSMC) scheme is proposed to defend against power analysis attacks by keeping enough background noises. A test chip of the proposed multicore processor is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS LP technology and can operate at up to 800 MHz with a 1.2-V supply. The Advanced Encryption Standard (AES) algorithm with these randomization methods is implemented on the processor. Measurement results show that the correlation power analysis (CPA) attacks and the power analysis attacks based on convolutional neural networks (CNNs) are unsuccessful even with 2,000,000 power traces when all the countermeasures are used.
Cryptographic circuits such as advanced encryption standard (AES) are vulnerable to correlation power analysis (CPA) side-channel attacks (SCAs), where an adversary monitors chip supply current signatures or electromagnetic (EM) emissions to decipher the value of embedded keys. This article describes an all-digital, fully synthesizable SCA-resistant 16-b serial AES-128 hardware accelerator fabricated in 14-nm CMOS, occupying 4900
. Randomized byte-order shuffling through heterogeneous Sboxes, linear masked MixColumns, and dual-rail AddRoundKey circuits enable: 1) 9.2
lower correlation between current signatures and hamming distance (HD)/hamming weight (HW) power models compared to an unprotected AES implemented in 14-nm CMOS; 2) 2.3
attenuation of a correlation ratio for correct key guesses; 3) 839-Mb/s encryption throughput with 11-mW total power consumption measured at 750 mV, 25 °C; 4) peak energy efficiency of 390 Gbps/W measured at an energy optimal point of 290 mV, 25 °C, representing an overhead of 23% over the unprotected AES engine; 5) < 1% performance impact compared to unprotected AES; 6) >1200
improvement in minimum-traces-to-disclosure (MTD) over an unprotected AES accelerator, with no successful CPA attacks observed after 12M encryptions; and 7) >1100
improvement in test vector leakage assessment (TVLA) metric in power and EM time- and frequency-domain analyses.
Hardware countermeasure of side channel attack (SCA) becomes necessary to protect crypto circuits. Many countermeasures endured large area and power consumption. We propose a SCA-resistant methodology based on machine learning, which compensates the Hamming distance (HD) probability of the intermediate data directly. By making the HD probabilities unable to be distinguished from correct and incorrect sub-keys, it provides resistance to SCA. Optimum HD redistribution is obtained by a machine learning algorithm and then sent to the compensation circuit. Applied in an Advanced Encryption Standard (AES)-128 circuit, the whole compensated circuit is implemented on a 28-nm CMOS process. The experimental results show that it resists correlation-based SCA with 1.5 million traces, corresponding to 446
improvements of measures to disclosure compared with a nonprotected AES circuit. In addition, it has no impact on the frequency and throughput rate, and its power overhead of 38% and area overhead of 36% are relatively low, making it suitable for resource-constrained encryption circuits.
Memory resistor or memristor is the forth fundamental circuit element that has attained considerable attention due to its unique characteristics and possible extensive applications in future generation nanoscale circuits and systems. In this brief, the contribution that memristor-based circuits may offer to the evolution of cryptographic hardware and embedded systems is discussed. Specifically, it will be shown how memristor-based implementation of security algorithms can mitigate the danger of differential power analysis attacks (DPA) at the technology level with lower cost and energy compared to conventional existing algorithmic countermeasure techniques. A 128-bit Advanced Encryption Standard (AES) cryptoprocessor was designed and implemented in both CMOS and hybrid CMOS/memristor technology. The robustness of the CMOS-based implementation against power analysis attacks was evaluated on Side-Channel Attack User Reference Architecture (SAKURA-GII) while the nanoscale counterpart system was evaluated by using a customized simulation and attack environment which was developed for extracting power traces using Synopsys and Cadence tools along with a DPA attack software implemented in MATLAB. It was observed that hybrid CMOS/memristor-based implementation provides considerable improvement over implementation with regular CMOS architectures in terms of energy consumption and attack tolerance and demonstrates good potential in mitigating DPA attacks without having to apply costly countermeasures such as masking or hiding.
Composite fields are used for implementing the AES SBox when compact and side-channel resistant constructions are required. The prior art has investigated efficient implementations of such SBoxes for ASIC platforms. On FPGAs however, due to the considerably different structure compared to ASICs, these implementations perform poorly. In this paper, we revisit composite field AES SBox implementations for FPGAs. We show how design choices and optimizations can be made to better suit the granular look-up tables (LUTs) that are present in modern FPGAs. We investigate 2880 SBox constructions and show that about half of them are better than the state-of-the-art composite field implementation. Our best SBox implementation is 18% smaller compared to the state-of-the-art implementation on an FPGA.
This paper demonstrates the improved power and electromagnetic (EM) side-channel attack (SCA) resistance of 128-bit Advanced Encryption Standard (AES) engines in 130-nm CMOS using random fast voltage dithering (RFVD) enabled by integrated voltage regulator (IVR) with the bond-wire inductors and an on-chip all-digital clock modulation (ADCM) circuit. RFVD scheme transforms the current signatures with random variations in AES input supply while adding random shifts in the clock edges in the presence of global and local supply noises. The measured power signatures at the supply node of the AES engines show upto 37
reduction in peak for higher order test vector leakage assessment (TVLA) metric and upto 692
increase in minimum traces required to disclose (MTD) the secret encryption key with correlation power analysis (CPA). Similarly, SCA on the measured EM signatures from the chip demonstrates a reduction of upto 11.3
in TVLA peak and upto 37
increase in correlation EM analysis (CEMA) MTD.
The AES combined S-box/inverse S-box is a single construction
that is shared between the encryption and decryption data
paths of the AES. The currently most compact implementation of the
AES combined S-box/inverse S-box is Canright’s design, introduced
back in 2005. Since then, the research community has introduced
several optimizations over the S-box only, however the combined Sbox/inverse
S-box received little attention. In this paper, we propose
a new AES combined S-box/inverse S-box design that is both smaller
and faster than Canright’s design. We achieve this goal by proposing
to use new tower field and optimizing each and every block inside the
combined architecture for this field. Our complexity analysis and ASIC
implementation results in the CMOS STM 65nm and NanGate 15nm
technologies show that our design outperforms the counterparts in terms
of area and speed.
This paper demonstrates an integrated inductive voltage regulator (IVR) for improving power side-channel-attack (PSCA) resistance of 128-bit Advanced Encryption Standard (AES-128) engines. An inductive IVR is shown to transform the current signatures generated by an encryption engine. Furthermore, an all-digital circuit block, referred to as the loop-randomizer, is introduced to randomize the IVR transformations. A 130-nm test-chip with an inductive IVR with 11.6-nH inductance, 3.2-nF capacitance, and 125-MHz switching frequency is used to drive two different architectures of AES-128 engine: high performance and low power. The measurements demonstrate that the IVR with loop randomizer eliminates information leakage while incurring only 3% overhead in performance and 5% overhead in power over a baseline IVR-AES system. Moreover, while a key-byte can be extracted for the standalone high-performance and low-power AES (LP-AES) with only 5000 and 1000 measurements, respectively, the proposed IVR inhibits key extraction even with 500,000 measurements.
Hardware Trojan detection has emerged as a critical challenge to ensure security and trustworthiness of integrated circuits. A vast majority of research efforts in this area has utilized side-channel analysis for Trojan detection. Functional test generation for logic testing is a promising alternative but it may not be helpful if a Trojan cannot be fully activated or the Trojan effect cannot be propagated to the observable outputs. Side-channel analysis, on the other hand, can achieve significantly higher detection coverage for Trojans of all types/sizes, since it does not require activation/propagation of an unknown Trojan. However, they have often limited effectiveness due to poor detection sensitivity under large process variations and small Trojan footprint in side-channel signature. In this paper, we address this critical problem through a novel side-channel-aware test generation approach, based on a concept of Multiple Excitation of Rare Switching (MERS), that can significantly increase Trojan detection sensitivity. The paper makes several important contributions: i) it presents in detail a scalable statistical test generation method, which can generate high-quality testset for creating high relative activity in arbitrary Trojan instances; ii) it analyzes the effectiveness of generated testset in terms of Trojan coverage; and iii) it describes two judicious reordering methods that can further tune the testset and greatly improve the side channel sensitivity. Simulation results demonstrate that the tests generated by MERS can significantly increase the Trojans sensitivity, thereby making Trojan detection effective using sidechannel analysis. IEEE
Power analysis attacks (PAAs), a class of side-channel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a register-transfer level (RTL) countermeasure to increase the security of cryptographic devices against PAAs. We exploit the SDRR in a conventional advanced encryption standard (AES)-128 architecture, improving the immunity of the cryptographic hardware to the state-of-the-art PAAs. In the AES-128 exploiting SDRR, the combinational path evaluates random data throughout the entire clock cycle, and the interleaved processing of random and real data ensures the protection of both combinational and sequential logics. Our technique does not require the duplication of the combinational path to process the random data, thus limiting area overhead, unlike previous RTL countermeasures. The proposed approach is validated by means of PAAs based on real measurements on a field-programmable gate array implementation and on a 65-nm CMOS prototype chip. The protected implementation shows a strongly reduced correlation coefficient for the correct key, and more than three orders of magnitude increase in the measurements to disclosure with respect to the unprotected AES-128.
Leakage of information through the power supply current has become a major factor in logic design. In this paper, a low cost and simple to employ design methodology dubbed pseudoasynchronous is presented. This design style combines the security advantages of asynchronous circuits with the ease of synchronous circuit design. Randomization and data-dependencies (DD) are utilized to hide information leakage from the current dissipation, and hence making the critical synchronization of power supply current traces hard to do. In addition, randomization and DD are utilized for both time-domain hiding of information leakage during the active region (dynamic currents) and for amplitude-domain hiding of information leakage during the static-region (leakage currents). The main advantages of this new approach are low area cost, reduced signal, and increased noise. Circuit-level analyses show that it is harder to exploit the information leakage from internal signals of the proposed design than from CMOS-based synchronous designs or other forms of time-domain hiding countermeasures.
Energy-efficient countermeasures to side-channel attacks are required for Internet of Things hardware. This paper proposes a special hiding technique for the substitution operation in block ciphers, which equalizes the power consumption of a circuit by appropriate feedforward compensation and is called power-aware hiding (PAH). A hybrid application configuration, in which PAH is applied to the S-boxes while the left linear operations are protected with a general masking method, is proposed as well. This solution not only has higher energy efficiency but can also be implemented automatically in a semicustom manner. The Advanced Encryption Standard VLSI adopting this solution was implemented and manufactured in 180-nm technology as a demonstration. The implementation issues regarding the countermeasures are discussed in this paper. Testing shows that the chip has a throughput up to 1.175 Gb/s with 18.1-mW power consumption and its number of measurements to disclosure is 13.4 million.
Area minimization is one of the main efficiency criterion for lightweight encryption primitives. While reducing the implementation data path is a natural strategy for achieving this goal, Substitution-Permutation Network (SPN) ciphers are usually hard to implement in a bit-serial way (1-bit data path). More generally, this is hard for any data path smaller than its Sbox size, since many scan flip-flops would be required for storage, which are more area-expensive than regular flip-flops.
A false key-based advanced encryption standard (AES) technique is proposed to prevent the stored secret key leaking from the substitution-box under correlation power analysis (CPA) attacks without significant power and area overhead. Wave dynamic differential logic (WDDL)-based XOR gates are utilized during the reconstruction stage to hide the intermediate data that may be highly correlated with the false key. After applying the false key and designing the reconstruction stage with the WDDL, the minimum measurement-to-disclose value for the proposed lightweight masked AES engine implementation becomes over 150 million against CPA attacks. As compared to an unprotected AES engine, the power, area, and performance overhead of the proposed AES implementation is negligible.
A 128-bit Advanced Encryption Standard (AES) core targeted for high-performance security applications is fabricated in a 65nm CMOS technology. A novel charge-recovery logic family, called Bridge Boost Logic (BBL), is introduced in this design to achieve switching-independent energy dissipation for an intrinsic high resistance against Differential Power Analysis (DPA) attacks. Based on measurements, the AES core achieves a throughput of 16.90Gbps and power consumption of 98mW, exhibiting 720x higher DPA resistance and 30% lower power than its conventional CMOS counterpart at the same clock frequency.
First-order and high-order correlation-power-analysis attacks have been shown to be a severe threat to cryptographic devices. As such, they serve as a security measure for evaluation and comparison of security-oriented implementations. When properly designed, data-dependent delays can be used as a barrier to these attacks. This paper introduces a security-oriented delay assignment algorithm for mitigating single and multibit attacks. The algorithm enables a reduction of the correlation between the processed data and the consumed current by utilizing the data-dependent delays as a source of correlated noise. This is done while minimizing the area overhead, propagation time, and power. We show that for the same security level this new algorithm provides X2 and X6 more area efficiency, and X1.5 and X2.25 higher frequencies than a permuted path delay assignment and random embedding of delay elements.
This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of encryption engines. We propose security aware design modes for low passive FIVR to improve robustness of an encryption-engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used to attack a 128-bit AES engine synthesized in 130nm CMOS. The original design requires ~250 Measurements to Disclose (MTD) the 1st byte of key; but with security-aware FIVR, the CPA was unsuccessful even after 20,000 traces. We present a reversibility based threat model for the FIVR-based protection improvement and show the robustness of security aware FIVR against such threat.