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Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD Layout Data
in the CAD-Linked EB Test System
Katsuyoshi MIURA Koji NAKAMAE Hiromu FUJIOKA
Department of Information Systems Engineering, Faculty of Engineering,
Osaka University
Yamada-Oka 2-1, Suita, Osaka, 565 Japan
Tel: +81-6-879-7813 Tel: +81-6-879-7811 +81-6-879-7810
Fax: +81-6-879-7812 Fax: +81-6-879-7812 +81-6-876-4599
e-mail: miura@ise.eng.osaka-u.ac.jp e-mail:nakamae@ise.eng.osaka-u.ac.jp e-mail: fujioka@ise.eng.osaka-u.ac.jp
Abstract—A previous hierarchical fault tracing method for
combinational circuits which requires only CAD layout data in the
CAD-linked electron beam test system is expanded as applicable
to sequential circuits. The characteristics in the method remains
unchanged that allows us to trace a fault hierarchically from the
top level cell to the lowest primitive cell and from the primitive
cell to the transistor-level circuit in a consistent manner indepen-
dently of circuit functions. The applied results to the CAD layouts
of some sequential CMOS benchmark circuits show our superi-
ority to the guided-probe method where circuit logical functions
are first extracted from the CAD layout data and then the guided-
probe testing is executed.
I. INTRODUCTION
The electron beam (EB) test system linked to the CAD
database [1] has been widely used for testing VLSIs. Through
the fault localization process by using the method such as the
guided probe diagnosis [2], [3] with the CAD-linked EB test
system, a gate-level fault or a cell-level fault is determined. On
the other hand, the performance faults such as the delay fault
have become a serious issue [4]. In order to search the cause of
the performance fault, it becomes necessary to trace the fault
in the lowest level of the circuit, that is, in the transistor-level
unlike the gate-level. In the CAD-linked EB test system, the
CAD schematic or netlist and the mask layout data should be
mutually linked. However, in order to prepare the CAD data
and get the correspondence between the schematic or netlist
and the mask layout, a great deal of labor is required.
To deal with the situation described above, we have pro-
posed a hierarchical fault tracing method for a hierarchically
structured CAD layout data of combinational circuits [5], [6],
[7]. The method needs only CAD layout data: the tedious tasks
for CAD linkage is greatly reduced. In the method, a fault is
traced hierarchically from the top level cell to the transistor-
level circuit in a consistent manner independently of the circuit
function, as extracting circuit data successively.
Usually, VLSI includes some sequential circuits which con-
tain memory elements and feedback lines. The output of the
sequential circuit is a function of the present state and the in-
put. To determine the output, one needs to know the present
state of the memory elements and the logic values at the feed-
back lines. Thus, a fault in a sequential circuit is not detected
within one time frame by simply applying an input vector and
observing the output [8].
In this paper, we expand our previous hierarchical fault trac-
ing method for combinational circuits as applicable to such se-
quential circuits. Then the expanded method is applied to the
CAD layouts of some sequential CMOS benchmark circuits
and compared with the guided-probed method where circuit
logical functions are first extracted from the CAD layout data
and then the guided-probe testing [9] is executed.
II. OVERVIEW OF PREVIOUS HIERARCHICAL FAULT TRACING
FOR COMBINATIONAL CIRCUIT
The previous hierarchical fault tracing method for combina-
tional circuits uses an integrated algorithm that combines a suc-
cessive circuit extraction from hierarchically structured CAD
layout data and a hierarchical fault tracing for the combina-
tional circuit [5], [6], [7].
The fault tracing system consists of a device under test
(DUT), a good device to acquire reference waveforms, an LSI
tester to stimulate these devices, an EB tester to observe an in-
ternal behavior, and a control program.
The procedure of the hierarchical fault tracing is as follows.
At first, one of faulty external output pins specified by an LSI
tester is selected to be a start point for tracing. The start point
is on the top level cell. Next, partial circuit data around the
start point are extracted from CAD layout of the top level cell.
Then the interconnection to be measured is specified. The sig-
nal waveform on the interconnection is measured with the EB
tester and is compared with the reference waveform. When the
signal is faulty, the fault tracing proceeds upstream until all the
upstream interconnections have good signal waveform. Other-
wise, the faulty area is specified at the top level. If the pointed
faulty area includes a cell, the fault tracing proceeds to the next
lower level inside the cell. Repeating the procedure described
above, the faulty tracing level goes down. Finally, the fault is
localized in the transistor-level.
ASP-DAC ’97
0-89791-851-7$5.00 1997 IEEE
We use two kind of labels called DC PATH LABEL and MEA-
SURED LABEL in the fault tracing algorithm. The DC PATH
LABELs are put on the interconnections and the devices which
constitute a DC path (an ELEMENTARY PATH) in order to
make the fault tracing proceeds to the upstream. The DC path
is defined as a path which connects a starting interconnection
to the power supplies VDD and VSS or to an output terminal of
a cell instance. The MEASURED LABELs are put on the inter-
connections that have been tested in order to avoid measuring
the same interconnection again.
III. HIERARCHICAL FAULT TRACING FOR SEQUENTIAL
CIRCUITS
In the sequential circuits, a faulty signal may propagate
through the same circuit node multiple times because of mem-
ory elements and some feedback lines: this requires to allow us
to test the same circuit node more than once at different times.
The means of solving this problem will be discussed in III-A.
To determine the output of the sequential circuit, one needs
to know the present state of the memory elements as well as the
logic values at the feedback lines. It follows that the fault in the
sequential circuit can not be detected within one time frame by
simply applying an input vector and observing the output [8]:
the test of the sequential circuit results in a long test sequence.
Thus the less number of probing is desirable because of a long
tracing time due to a long test sequence. Reduction of probing
points will be treated in III-B.
A. Additional information on DC PATH LABELs and MEA-
SURED LABELs
Our previous fault tracing method prevents us from testing
the same circuit node again. Let us take a circuit shown in
Fig. 1 as an example. Interconnections are labeled 1, 2,
111
,
and 12. Arrows indicate the faulty signal flow. Boxes are flip-
flops. We start fault tracing at the interconnection 8. After the
DC PATH LABELs are put on the interconnections 8 and 2 and
the MOS transistors along the DC path drawn by thick lines in
Fig. 1, fault tracing proceeds to the interconnection 2. Next,
the DC PATH LABELs are put on the interconnection 1 and 12.
When the fault tracing proceeds to the interconnection 12, the
DC PATH LABEL labeling and the fault tracing proceed to the
interconnection 11,
111
, 10, 9, and reach at the interconnection
1
7911
4
FF FF
2
3
5
6
8
10 12
Fig. 1.Example of the fault tracing on the same circuit nodes at different
times. The arrows indicate the faulty signal flow. The thick and gray lines
show the DC paths in the first and second tracings, respectively.
7. At the next step, the fault tracing must proceed to the inter-
connection 1 through the interconnection 2. The MEASURED
LABEL previously placed on the interconnection 2, however,
put a stop to further fault tracing. There is also a problem on
the DC PATH LABEL. When fault tracing proceeds to the in-
terconnection 7, the DC PATH LABEL labeling is carried out.
The DC PATH LABELs have to be put on the interconnections
and the MOS transistors along the path drawn by gray line in
Fig. 1. On the interconnections 2 and 8 and the MOS transis-
tors along the path drawn by thick line in Fig. 1, however, the
DC PATH LABELs have been already placed. If new DC PATH
LABELs are put over the old ones, the fault tracing may pro-
ceed to a wrong path, that is, to the interconnections 5, 6 and
8. In order to trace a fault along the correct path, we add the
depth number of the fault tracing to the DC PATH LABEL and
permit that the DC PATH LABELs are overlapped if their depth
numbers differ from each other. The depth number indicates
the distance from the primary output, that is, the start node of
the fault tracing on the traced path. The depth number is 1
at the beginning of the fault tracing, and is incremented when
the fault tracing proceeds through the gate electrode of a MOS
transistor and through a cell instance.
In order to permit the interconnection to be measured again,
if the tracing time is different, we add an information about the
tracing time to the MEASURED LABEL. In addition, the result
of the waveform comparison (Good or Faulty) is recorded in
the MEASURED LABEL to make the fault tracing efficient.
B. Reduction of probing points
In the sequential circuit, the less number of probing is desir-
able because of a long tracing time due to a long test sequence.
When the same circuit is traced in the second time, making use
of the previous information about the extracted circuit data, the
tracing path and depth and the propagation delay can much im-
prove the efficiency of the fault tracing. The extracted circuit
data is recorded in the circuit data structure [6]. The traced path
and depth and the propagation delay can be found from the DC
PATH LABEL and the MEASURED LABEL.
We apply the binary search algorithm to the second tracing at
the same circuit node. Let us take a circuit shown in Fig. 2 as an
example. The interconnections are labeled 1, 2,
111
, and 8. The
numbers in parentheses attached to labels 1 to 6 are the depth
numbers. The arrows indicate the faulty signal flow. We start
the fault tracing at the interconnection 6. When the fault tracing
1(6) 2(5) 3(4) 4(3) 5(2)
6(1, 7)
78
Fig. 2.Example of the second tracing for the feedback lines. In the second
tracing, only the interconnections 3, 2, 7 and 8 are measured.
proceeds to the interconnection 6 through the interconnections
5, 4,
111
, and 1, a MEASURED LABEL has already been placed
on the interconnection 6. Thus we know that the feedback line
is formed through the interconnection 6.
Withthe aid ofthe binary search algorithm, the interconnec-
tion 3 which is centered on the tracing path is tested at first. The
measurement period of the interconnection 6 is advanced by the
signal propagation delay between the interconnections 3 and 6
which can be calculated from the data recorded in the MEA-
SURED LABELs. When the interconnection 3 is faulty, again
the binary search is applied to a left half ofthe path. Divisions
are repeated until the cell with an unmeasured faulty input 8 is
specified. From the interconnection 8, the usual back tracing
is performed. In this fault tracing method, measurements are
carried out only log2(
D
2
0
D
1) times, where
D
1and
D
2are
the depth numbers put on the interconnection 6 at the first time
and at the second time, respectively.
C. Global flow of the hierarchical fault tracing
Fig. 3 shows the global flow of the hierarchical fault tracing
in the sequential circuit. Circles labeled A, B, C and D indicate
the processes. Arrows labeled a, b,
111
, and g are the conditions
to turn to another process. At first, go to the process A in which
a back tracing is carried out. This process includes sub pro-
cesses of selection of the upstream interconnection, decision
of the measurement period, practice of the waveform measure-
ment and the waveform comparison, and descent of the hierar-
chy.
When the fault tracing meets an unmeasurable interconnec-
tion [5] (the condition a), go to the process B. In this process,
measurable upstream interconnections are tested. If a faulty
waveform is acquired (the condition b), then return to the pro-
cess A. Otherwise (the condition c), go to the process C where a
forward tracing to the last faulty interconnection is carried out.
Then return to the process A (the condition d). When the fault
tracing meets the interconnection on which a faulty waveform
has been already acquired (the condition e), go to the process D
where the second tracing at the same circuit node is performed.
When the second tracing process is finished (the condition f),
then return to the process A. When good waveforms are ac-
Second tracing
a. There is an
unmeasurable
interconnection.
Test measurable
upstream
interconnections
c. Good
g. All good in
transistor level.
Forward tracing
Back tracing
e. There is an interconnection
on which a faulty signal has
been already acquired.
Start
A
B
C
End
d. Forward tracing
is completed.
f. Second tracing
is completed.
b. Faulty D
Fig. 3.The global flow of the hierarchical fault tracing in the sequential
circuit. Circles labeled A, B, C and D, indicate the processes. Arrows labeled
a, b,
111
, and g are the conditions to turn to another process.
quired on all upstream interconnections in the transistor-level
(the condition g), then the fault tracing is completed.
IV. APPLICATION
We have implemented our expanded hierarchical fault trac-
ing method in the C language on a UNIX workstation where
the layout data in GDS-II format is available. We applied the
method to the CAD layouts of randomly selected five circuits
in the ISCAS’89 sequential benchmark circuit set[10] as shown
in Table 1. The layouts were made by using the CMOS3 cell
library [11]. On each layout, we randomly generated a perfor-
mance fault [4] ten times. The assumed performance fault is
that the signal delay lies outside of a specified range due to the
insufficient drive capability of the MOS transistor. The test pat-
tern sequence was generated to propagate the faulty signal due
to the performance fault to primary outputs.
Figs. 4(a) and (b) show the CAD layout and the gate-level
schematic of the sequential benchmark circuit s27. Fig. 5
shows the transistor- level schematic of the cell “L” included
in Fig. 4(b). The transistor M564 is assumed faulty. The ex-
panded hierarchical fault tracing method was applied to the
CAD layout shown in Fig. 4(a). The executed result is shown
in Table 1. Each “measure” row in the table contains the prob-
ing point number, the interconnection number, the measure-
ment period and the waveform comparison result. In case of
faulty, the period in which the faulty signal is detected is also
recorded as [208, 228], where the unit of time is ns. The row
10 shows the suggested faulty cell. Rows from 13 to 15 sug-
gest the names of a possible faulty interconnection and MOS
transistors. These results are shown in the crosshatched region
(a)
101
98
100
30 99
90
91
29
25
94
92
93
28
96
95 15
86
97
88
A
C
M
B
D
E
F
G
H
I
J
K
L
(b)
Fig. 4.CAD layout (a) and the gate-level schematic (b) of the sequential
benchmark circuit s27.
VDD VDD
VSS
VDD
VSS
VDD
VSS
VDD VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
118
M564
M549
M551
M536
M552
M537
M553
M538
M554
M539
M555
M540
M556
M541
M557
M542
M558
M543
M559
M544
M560
M545
M561
M546
M562
M547
M563
M548 90
93
88
97
119
Fig. 5.Transistor-level schematic of the cell “L” included in Fig. 4(b). The
transistor M564 is assumed faulty.
TABLE I
E
XECUTED RESULT.
Initial Fault Phase: [210-230]
measure[1]:93, Phase: [110-230], Faulty: [208-228]
measure[2]:92, Phase: [108-228], Good
measure[3]:94, Phase: [108-228], Faulty: [206-226]
measure[4]:25, Phase: [106-226], Faulty: [204-224]
measure[5]:99, Phase: [104-224], Faulty: [202-222]
measure[6]:90, Phase: [102-222], Faulty: [200-220]
measure[7]:88, Phase: [100-220], Good
measure[8]:97, Phase: [100-220], Good
There is a fault in the cell: L
measure[9]:119, Phase: [100-220], Good
There may be a fault around the interconnection 118
interconnection(118)
MOS-FET(564)
MOS-FET(549)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
in Fig. 5. Thus, the intended fault was correctly specified.
We compared the number of probing points of our method
with that of the guided-probe method where circuit logical
functions are extracted from the CAD layout data [12] and then
the guided-probe testing [9] is executed. In the guided-probe
testing, to reduce the number of probing points, the speed-up
technique is adopted where we probe first the control lines
among the inputs that can influence the output with errors.
The difference of the number of probing points of the present
method from that of the guided-probe method is shown in Table
2. MIN, MAX, and AVE means the minimum, maximum and
average differences for ten randomly generated performance
faults, respectively. For reference, the average number of prob-
ing points (AVE probing points) of our fault tracing method is
also described. It is seen that the number of probing points of
the expanded hierarchical fault tracing method is reduced a lit-
tle as compared with that of the guided-probe method. Thus the
present method is superior to the guided-probe method when
only CAD layout data is available, since our method does not
need to recognize the circuit logical functions.
V. CONCLUSIONS
We expand a previous hierarchical fault tracing method for
combinational circuits which requires only CAD layout data
in the CAD-linked electron beam test system as applicable to
sequential circuits. The characteristics in the method remains
TABLE II
D
IFFERENCE OF THE NUMBER OF PROBING POINTS OF THE EXPANDED
HIERARCHICAL FAULT TRACING METHOD FROM THAT OF THE
GUIDED-PROBE METHOD.
circuit name AVE
probing
points
#trans. difference
MIN MAX AVE
S27
S208
S510
S953
S5378
136
676
1158
2530
14276
6.6
14.9
10.9
9.0
17.2
-4
-4
-5
-4
-5
0
3
4
3
5
-1.1
0
-0.6
-0.2
-1.0
unchanged that allows us to trace a fault hierarchically from the
top level cell to the lowest primitive cell and from the primi-
tive cell to the transistor-level circuit in a consistent manner in-
dependent of circuit functions The applied results to the CAD
layouts of five sequential CMOS benchmark circuits show the
superiority of our expanded hierarchical fault tracing method
as compared with the guided-probe method where circuit logi-
cal functions are extracted from the CAD layout data and then
the guided-probe testing is executed.
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