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Frequency-selective Optimization of Periodic Gate Control Signals in DC/DC Converters for EMI-reduction
Abstract
High-frequency switching of power transistors in power electronic systems can cause electromagnetic emissions. Simple approaches for reducing high-frequency disturbances, such as inserting an additional gate resistor, lead to increased power losses. This makes achieving both electromagnetic compatibility and power efficiency difficult. Active gate drivers help to find a trade-off between these two. Typically, only narrow-band disturbances must be reduced. Accordingly, a target signal with a spectrum notched at some frequencies can be defined. The target signal can be reached by a target-signal-oriented control of the transistor's gate. This leads to steeper switching slopes, such that the power losses are less increased. Generating arbitrary target signals is impossible. The transistor signal exhibits some physical limitations. A constraint satisfaction problem must be solved, and the gate drive signal must be optimized by applying a residual and Newton's method. The proposed optimization process in the frequency domain is based on the circuit simulation method named “harmonic balance”. Measurements on a DC/DC converter exhibit the benefits of this method.
The voltage rating of the commercial Gallium Nitride (GaN) power devices are limited to 600/650 V due to the lateral structure. Stacking the low-voltage rating devices is a straightforward approach to block higher dc link voltage. In this article, a novel controllable current source gate driver is proposed, which addresses the voltage imbalance issue of series-connected GaN HEMTs for both hard switching and soft switching scenarios. The proposed current source gate driver controls the device switching timing and the dv/dt with fine accuracy by directly regulating the device gate current. Without the employment of the lossy snubber circuit or the external Miller capacitor, the switching energy and the switching speed are almost not compromised for each individual device. Meanwhile, the current mirror circuits are utilized as the discontinuous pulsed current sources, which produce negligible additional gate driving loss. A series-connected GaN-based multiple pulse tester is built to validate the proposed current source gate driver and the voltage balancing strategies. It is demonstrated that the drain-to-source voltage difference of the series-connected GaN devices is below 10% for different load current and different switching speed (dv/dt) conditions.
Globalization concepts for Newton-type iteration schemes are widely used when solving nonlinear problems numerically. Most of these schemes are based on a predictor/corrector step size methodology with the aim of steering an initial guess to a zero of f without switching between different attractors. In doing so, one is typically able to reduce the chaotic behavior of the classical Newton-type iteration scheme. In this note we propose a globalization methodology for general Newton-type iteration concepts which changes into a simplified Newton iteration as soon as the transformed residual of the underlying function is small enough. Based on Banach’s fixed-point theorem, we show that there exists a neighborhood around a suitable iterate such that we can steer the iterates—without any adaptive step size control but using a simplified Newton-type iteration within this neighborhood—arbitrarily close to an exact zero of f. We further exemplify the theoretical result within a global Newton-type iteration procedure and discuss further an algorithmic realization. Our proposed scheme will be demonstrated on a low-dimensional example thereby emphasizing the advantage of this new solution procedure.
A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high speed switching. In this study, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from 64
possible combinations of switching patterns within 15 minutes, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern.
Active gate driving has been demonstrated to beneficially shape switching waveforms in Si- and SiC-based power converters. For faster GaN power devices with sub-10-ns switching transients, however, reported variable gate driving has so far been limited to altering a single drive parameter once per switching event, either during or outside of the transient. This paper demonstrates a gate driver with a timing resolution and range of output resistance levels that surpass those of existing gate drivers or arbitrary waveform generators. It is shown to permit active gate driving with a bandwidth that is high enough to shape a GaN switching during the transient. The programmable gate driver has integrated high-speed memory, control logic, and multiple parallel output stages. During switching transients, the gate driver can activate a near-arbitrary sequence of pull-up or pull-down output resistances between 0.12 Ω and 64 Ω. A hybrid of clocked and asynchronous control logic with 150-ps delay elements achieves an effective resistance update rate of 6.7 GHz during switching events. This active gate driver is evaluated in a 1-MHz bridge-leg converter using EPC2015 GaN FETs. The results show that aggressive manipulation of the gate-drive resistance at sub-ns resolutions can profile gate waveforms of the GaN FET, and thereby beneficially shape the switch-node voltage waveform in the power circuit. Examples of open-loop active gate driving are demonstrated that maintain the low switching loss of constant-strength gate driving, whilst reducing overshoot, oscillation, and EMI-generating high-frequency spectral content.
Silicon carbide (SiC) MOSFETs are viable alternatives for silicon (Si) insulated-gate bipolar transistors (IGBTs). However, direct retrofitting of SiC MOSFETs in Si IGBT-based converters is not feasible due to the presence of a higher amount of parasitic inductance. A large voltage and current overshoot along with oscillation are noticed in such attempts as SiC MOSFETs switch very fast. An active gate driver (AGD) can meet the conflicting requirements of faster switching speed and lower overshoot and ringing. A switched current source-based AGD is designed and extensively tested in a 50-kVA voltage source inverter made with SiC MOSFET power modules. The control methodology is discussed and the experimental results are presented in this article.
State-of-the-art silicon carbide (SiC) power devices provide superior performance over silicon devices with much higher switching frequencies/speed and lower losses. High switching speed is preferred for achieving low switching loss, yet high
dv/dt
and
di/dt
can result in high EMI emission during switching transients. These switching dynamics can be controlled by the device gate driving strategy. The multi-level active gate driver (AGD) approach is able to tradeoff the switching losses with the
dv/dt
and
di/dt
for each switching transient. A novel three-level (3-L) AGD for SiC power
mosfet
trajectory control is introduced. Its turn-off profile has a shorter turn-off delay compared to any existing methodology. Accordingly, a comprehensive datasheet-driven trajectory model for the online model-based optimization of the 3-L turn-off is introduced. The main factors that impact the 3-L turn-off performance are analyzed with this model. The experimental results of double pulse tests validate the approach. Additionally, the benefits of the proposed 3-L AGD method over two-stage turn-off and conventional gate drivers on the market are illustrated through experiments.
Active cancellation of disturbing signals is a common method in EMC. In this paper, a specialized strategy is presented to minimize the disturbing harmonics of stationary clocked systems by injecting an appropriate harmonic cancellation signal with an adjustable signal synthesizer. The optimum cancellation signal is found via a convenient and robust adaptive approach. Each destructive harmonic is generated individually, and the cancelation signal is the superposition of a set of sinusoidal signals. As a special feature of this method, many troublesome effects, like delays or complex frequency characteristics, can be compensated easily. Several implementation variants can be derived from this general approach. Here, the variant, continuously adapted harmonics cancellation (CAHC), is considered. The system's limitations due to the ADC, the DAC, and the synchronization are described. An FPGA-implementation of CAHC is presented and applied to a dc/dc converter in an automotive component measurement setup to demonstrate the effectivity of the method.
A general-purpose clocked gate driver IC to generate an arbitrary gate waveform is proposed to provide a universal platform for fine-grained gate waveform optimization handling various power transistors. The fabricated IC with 0.18μm BCD process has 63 PMOS and 63 NMOS driver transistors on a chip whose activation patterns are controlled by 6-bit digital signals and 40ns time step control. In the 500V switching measurements with a manual gate waveform optimization, the proposed gate driver reduces the IC overshoot by 25% and 41% and the energy loss by 38% and 55% for Si-IGBT and SiC-MOSFET, respectively, which demonstrate the feasibility of driving various power devices with the same driver. An automatic optimization by Simulated Annealing algorithm is introduced to fully utilize the benefit of the gate driver and the further reduction of IC overshoot by 26% and the energy loss by 18% are achieved over the manual optimization.
Using numerical integration to compute a circuit’s transient response is by far the most commonly performed simulation of nonlinear circuits, even when the user is interested in steady-state behavior. As motivation for the chapters that follow, this section presents examples from several general classes of analog and microwave circuits for which the standard performance criteria must be measured when the circuit is in steady-state. And, to be honest, the circuits selected are ones for which the algorithms presented in the rest of this book are substantially more efficient and/or more accurate than standard techniques for computing steady-state. The circuits of this section are revisited in Chapter 8 at the end of this book, and used as examples to show the strengths and weaknesses of the methods presented in the following chapters.
This paper proposes a new concept for attaining a defined switching behavior of insulated-gate bipolar transistors (IGBTs) at inductive load (hard) switching, which is a key prerequisite for optimizing the switching behavior in terms of switching losses and electromagnetic interference (EMI). First, state-of-theart gate driver concepts that enable a control of the IGBT's switching transients are reviewed. Thereafter, a highly dynamic closed-loop IGBT gate driver using simple passive diC /dt and dvCE /dt feedbacks and employing a single analog PI-controller is proposed. Contrary to conventional passive gate drivers, this concept enables an individual control of the current and voltage slopes largely independent of the specific parameters or nonlinearities of the IGBT. Accordingly, a means for optimizing the tradeoff between switching losses, switching delay times, reverse recovery current of the freewheeling diode, turn-off overvoltage, and EMI is gained. The operating principle of the new gate driver is described and based on derived control oriented models of the IGBT, a stability analysis of the closed-loop control is carried out for different IGBT modules. Finally, the proposed concept is experimentally verified for different IGBT modules and compared to a conventional resistive gate driver.
Accurate computer simulation has helped reduce the cost and time required to complete many new integrated circuit designs. This is because a design can be corrected and its performance tuned faster and more economically using computer simulation than by repeated fabrication and testing of prototypes. However, to tune the performance of many analog and microwave integrated circuit designs, prototyping is still used because the commonly available computer simulation programs cannot simulate efficiently the test scenarios of interest. The main difficulty simulating general analog circuit designs is computing steady-state quantities, such as harmonic distortion, for circuits with a widely spread response spectrum. And in the specific case of microwave designs, this problem is compounded because microwave circuits typically include linear time-invariant distributed devices such as dispersive transmission lines.
Active gate control with synthesized signals to avoid overshoot and ringing in DC-to-DC converters. PCIM Europe digital days 2021; International Exhibition and Conference for Power Electronics, Intelligent Motion
- C Krause
- Bendicks
- Frei
C Krause, A Bendicks, S Frei. Active gate control with
synthesized signals to avoid overshoot and ringing in
DC-to-DC converters. PCIM Europe digital days 2021;
International Exhibition and Conference for Power
Electronics, Intelligent Motion, Renewable Energy and
Energy Management, 2021, Nuremberg, Germany. VDE,
2021: 1256-1262.
Improvement of the EMC performance of clocked MOSFETs with the help of synthesized drive signals based on network analysis and the EKV model
- C Krause
- Bendicks
- Frei
C Krause, A Bendicks, S Frei. Improvement of the EMC
performance of clocked MOSFETs with the help of
synthesized drive signals based on network analysis and
the EKV model. Proc. Conf. Electromagn. Compat., 2020,
Cologne, Germany. VDE, 2020: 131-138.
Improvement of the EMC performance of clocked MOSFETs with the help of synthesized drive signals based on network analysis and the EKV model
- krause
Active gate control with synthesized signals to avoid overshoot and ringing in DC-to-DC converters
- krause