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Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs

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Homomorphic Encryption (HE) enables users to securely outsource both the storage and computation of sensitive data to untrusted servers. Not only does HE offer an attractive solution for security in cloud systems, but lattice-based HE systems are also believed to be resistant to attacks by quantum computers. However, current HE implementations suffer from prohibitively high latency. For lattice-based HE to become viable for real-world systems, it is necessary for the key bottlenecks - particularly polynomial multiplication - to be highly efficient. In this paper, we present a characterization of GPU-based implementations of polynomial multiplication. We begin with a survey of modular reduction techniques and analyze several variants of the widely-used Barrett modular reduction algorithm. We then propose a modular reduction variant optimized for 64-bit integer words on the GPU, obtaining a 1.8x speedup over the existing comparable implementations. Next, we explore the following GPU-specific improvements for polynomial multiplication targeted at optimizing latency and throughput: 1) We present a 2D mixed-radix, multi-block implementation of NTT that results in a 1.85x average speedup over the previous state-of-the-art. 2) We explore shared memory optimizations aimed at reducing redundant memory accesses, further improving speedups by 1.2x. 3) Finally, we fuse the Hadamard product with neighboring stages of the NTT, reducing the twiddle factor memory footprint by 50%. By combining our NTT optimizations, we achieve an overall speedup of 123.13x and 2.37x over the previous state-of-the-art CPU and GPU implementations of NTT kernels, respectively.
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Accepted Manuscript: 2022 IEEE International Symposium on Secure and Private Execution Environment Design
Accelerating Polynomial Multiplication for
Homomorphic Encryption on GPUs
Kaustubh Shivdikar, Gilbert Jonatan, Evelio Mora, Neal Livesay, Rashmi Agrawal§,
Ajay Joshi§, Jos´
e L. Abell´
an, John Kim, David Kaeli
Northeastern University, §Boston University, KAIST University, Universidad Cat´
olica de Murcia
{shivdikar.k, n.livesay}@northeastern.edu, {eamora, jlabellan}@ucam.edu, {rashmi23, joshi}@bu.edu,
kaeli@ece.neu.edu, gilbertjonatan@kaist.ac.kr, jjk12@kaist.edu
Abstract—Homomorphic Encryption (HE) enables users to
securely outsource both the storage and computation of sensitive
data to untrusted servers. Not only does HE offer an attractive
solution for security in cloud systems, but lattice-based HE
systems are also believed to be resistant to attacks by quantum
computers. However, current HE implementations suffer from
prohibitively high latency. For lattice-based HE to become viable
for real-world systems, it is necessary for the key bottlenecks—
particularly polynomial multiplication—to be highly efficient.
In this paper, we present a characterization of GPU-based
implementations of polynomial multiplication. We begin with
a survey of modular reduction techniques and analyze several
variants of the widely-used Barrett modular reduction algorithm.
We then propose a modular reduction variant optimized for 64-
bit integer words on the GPU, obtaining a 1.8×speedup over the
existing comparable implementations. Next, we explore the fol-
lowing GPU-specific improvements for polynomial multiplication
targeted at optimizing latency and throughput: 1) We present a
2D mixed-radix, multi-block implementation of NTT that results
in a 1.85×average speedup over the previous state-of-the-art.
2) We explore shared memory optimizations aimed at reducing
redundant memory accesses, further improving speedups by
1.2×. 3) Finally, we fuse the Hadamard product with neighboring
stages of the NTT, reducing the twiddle factor memory footprint
by 50%. By combining our NTT optimizations, we achieve
an overall speedup of 123.13×and 2.37×over the previous
state-of-the-art CPU and GPU implementations of NTT kernels,
respectively.
Index Terms—Lattice-based cryptography, Homomorphic En-
cryption, Number Theoretic Transform, Modular arithmetic,
Negacyclic convolution, GPU acceleration
I. INTRODUCTION
Computation is increasingly outsourced to remote cloud-
computing services [1], [2]. Encryption provides security
as data is transmitted over the internet. However, classical
encryption schemes require that data be decrypted prior to
performing computation, exposing sensitive data to untrusted
cloud providers [3], [4]. Using Homomorphic Encryption (HE)
allows computations to be run directly on encrypted operands,
offering ideal security in the cloud-computing era (Figure 1).
Moreover, many of the breakthrough HE schemes are lattice-
based, and are believed to be resistant to attacks by quantum
computers [5].
One major challenge in deploying HE in real-world systems
is overcoming the high computational costs associated with
HE. For computation on data encrypted via state-of-the-art HE
Safe
Environment
Hostile
Environment
Untrusted
Environment
Internet
Trust Barrier
Message Encrypt Ciphertext
Message Decrypt Ciphertext
Servers
HE GPU
Acceleration
Compute
Fig. 1. HE provides security from eavesdroppers on the web as well as
untrusted cloud services, as encrypted data can be computed on directly.
schemes—such as HE for Arithmetic of Approximate Num-
bers [6] (also known as HEAAN or CKKS) and TFHE [7]—
a slowdown of 4–6 orders of magnitude is reported, as
compared to running the same computation on unencrypted
data [8], [9]. We aim to accelerate HE by targeting the main
operation in these schemes (and, more generally, in lattice-
based cryptography): polynomial multiplication [10], [11],
[12]. The Number Theoretic Transform (NTT) and modular
reduction are two key bottlenecks in polynomial multiplication
(and, by extension, in HE), as evidenced by the performance
profiling of several lattice-based cryptographic algorithms by
Koteshwara et al. [13]. As lattice-based HE schemes have
continued to establish themselves as leading candidates for
privacy-preserving computing and other applications, there has
been an increased focus on optimization and acceleration of
these core operations [14], [15], [16].
For most real-world applications of lattice-based HE, the
number Nof polynomial coefficients and the modulus Q
need to be large to guarantee a strong level of security and
a higher degree of parallelism [9]. For example, N= 216
and dlog2(Q)e= 1240 are the default values in the HEAAN
library. The large values for Nand Qtranslate to heavy work-
load demands, requiring a significant amount of computational
power to evaluate modular arithmetic expressions, as well as
placing high demands on the memory bandwidth utilization.
HE workloads possess high levels of data parallelism [17].
Existing compute systems such as general-purpose CPUs do
not scale well since they are unable to fully exploit this
parallelism for such data-intensive workloads. However, the
SIMD-style GPU platforms, with their thousands of cores
and high bandwidth memory (HBM), are natural candidates
arXiv:2209.01290v1 [cs.CR] 2 Sep 2022
Improvement Input
Size
NTT Kernel
Implementation
Proposed
Optimizations
Single-block
NTT
(Section V-A)
Multi-block
NTT
(Section V-B)
Throughput
Optimized NTT
(Section V-C)
Mixed Radix
2D NTT
(Section V-A.3)
Optimized
Barrett's Reduction
(Section II-B)
Persistent
Shared Memory
(Section V-A.1)
Fused
Hadamard Product
(Section III-B)
Increased
Spatial
Locality
Increased
Temporal
Locality
Reduced
Redundant
Operations
Fewer
Correctional
Subtractions
Scaled Out
FHE Acceleration
Fig. 2. Our contributions: 4major optimizations incorporated into 3kernels
for accelerating these highly parallelizable workloads. The
potential of the GPU platform to accelerate HE has motivated
a rapidly growing body of work over the past year [9], [18],
[19], [20], [21], [22], [23], [24], [25], [26].
To address performance bottlenecks in existing polynomial
multiplication algorithms, we begin by analyzing the Barrett
modular reduction algorithm [27], as well as the algorithm’s
variants [21], [26], [28] which have been utilized in prior
HE schemes. We then analyze various NTT implementations,
including mixed-radix and 2D implementations, which we
tune to improve memory efficiency. Finally, we apply a
number of GPU-specific optimizations to further accelerate
HE. By combining all our optimizations, we achieve an overall
speedup of 123.13×and 2.37×over the previous state-of-the-
art CPU [29] and GPU [21] implementations of NTT kernels,
respectively. Our key contributions are as follows (Figure 2):
1) We propose an instantiation of the Dhem–
Quisquater [28] class of Barrett reduction variants
which is optimized for HE, providing a 1.85×speedup
over prior studies [21], [23], [26], [30].
2) We present a mixed-radix, 2D NTT implementation to
effectively exploit temporal and spatial locality, resulting
in a 1.91×speedup over the radix-2 baseline.
3) We propose a fused polynomial multiplication algorithm,
which fuses the Hadamard product with its neighboring
butterfly operations using an application of Karatsuba’s
Algorithm [31]. This reduces the twiddle factor’s mem-
ory footprint size by 50%.
4) We incorporate the use of low latency, persistent, shared
memory in our single-block NTT GPU kernel implemen-
tation, reducing the number of redundant data fetches
from global memory, providing a further 1.25×speedup.
II. BARRETT REDUCTION AND ITS VARIANTS
Modular reduction is a key operation and computational
bottleneck in lattice-based cryptography [32]. This section
is a self-contained survey of modular reduction algorithms,
particularly Barrett reduction [27], a widely-used algorithm
that we utilize in our work.
Following Shoup [33], we define the bit length len(a)of
a positive integer ato be the number of bits in the binary
representation of a; more precisely, len(a) = blog2ac+ 1.
A. Background: modular reduction and arithmetic
Let xmod qdenote the remainder of a nonnegative in-
teger xdivided by a positive integer q. The naive method
for performing modular reduction—i.e., the computation of
xmod q—is via an integer division operation:
xmod q=x bx/qcq.
However, there are a number of alternative methods for
performing modular reduction—especially in conjunction with
arithmetic operations such as addition and multiplication—that
avoid expensive integer division operations.
For example, Algorithm 1specifies a simple and efficient
computation of the modular reduction of a sum. Let βdenote
the word-size (e.g., β= 32 or 64). Observe that either a+b
lies in [0, q)and is reduced, or a+blies in [q, 2q)and requires
a single correctional subtraction to become reduced (see lines
2–3). The restriction len(q)β1prevents overflow of the
transient operations (i.e., a+b).
Algorithm 1 A baseline modular addition algorithm
Require: 0a, b < q,len(q)β1
Ensure: sum = (a+b) mod q
1: sum a+b
2: if sum qthen
3: sum sum q
4: return sum
There are multiple methods for reducing products. In lattice-
based cryptography, commonly used algorithms for imple-
mentations on hardware platforms such as CPUs and GPUs
include the algorithms of Barrett [27], Montgomery [34], and
Shoup [35], [36]. In this paper, we select Barrett’s algorithm
as our baseline, as Barrett’s algorithm enjoys the following
features:
1) Low overhead: It requires a low-cost pre-computation
(and storage) of a single word-size integer µ.
2) Versatility: It may be used effectively in contexts where
multiple products are reduced modulo q.
3) Generality: It does not restrict to special classes of
moduli, such as Mersenne primes (see, e.g., [37], [38]).
4) Performant: It is significantly faster than integer di-
vision, and has comparable runtime performance with
Montgomery’s algorithm (see, e.g., [39]).
Barrett’s algorithm is used in many open-source libraries,
including cuHE [40], PALISADE [41], and HEANN [20], [6].
The Barrett reduction algorithm, and our proposed variant for
use in HE, are analyzed in Section II-B.
B. Barrett modular reduction: analysis and optimization
Next, we provide details of Barrett modular reduction and
then explore potential improvements. Algorithm 2specifies
the classical reduction algorithm of Barrett [27]. Note that if
2
Speedup
Compute Throughput
Avg. IPC
Memory Throughput
DRAM Throughput
L1 Throughput
L2 Throughput
ALU
Issued Warps
Registers per thread
(a) NTT workload modular reduction comparison
20
0
20
40
60
80
Percent Change
Modular reduction
Classic Barrett
Dhem
Proposed Barrett
Speedup
Compute Throughput
Avg. IPC
Memory Throughput
DRAM Throughput
L1 Throughput
L2 Throughput
ALU
Issued Warps
Registers per thread
(b) inverse-NTT workload modular reduction comparison
20
0
20
40
60
Percent Change
Modular reduction
Classic Barrett
Dhem
Proposed Barrett
Long Scoreboard
Math Pipe Throttle
Wait
Not Selected
Barrier
LG Throttle
Selected
Short Scoreboard
MIO Throttle
Branch Resolving
Dispatch Stall
IMC Miss
No Instruction
(c) NTT stall histogram across various modular reduction algorithms
0
1
2
3
4
Avg. stalled cycles / instruction
Modular reduction
Classic Barrett
Dhem
Proposed Barrett
Long Scoreboard
Math Pipe Throttle
Wait
Not Selected
Barrier
LG Throttle
Selected
Short Scoreboard
MIO Throttle
Branch Resolving
Dispatch Stall
IMC Miss
No Instruction
(d) inverse-NTT stall histogram across various modular reduction algorithms
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Avg. stalled cycles / instruction
Modular reduction
Classic Barrett
Dhem
Proposed Barrett
Fig. 3. Modular reduction profile comparison of architectural parameters (a,b) and causes of warp stalls (c,d).
Algorithm 2 Classical Barrett reduction
Require: m= len(q)β2,0x < 22m,µ=b22m
qc
Ensure: rem = xmod q
1: cx(m1)
2: quot (c×µ)(m+ 1)
3: rem xquot ×q
4: if rem qthen
5: rem rem q
6: if rem qthen
7: rem rem q
8: return rem
0a, b < q and m= len(q), then x=a×bsatisfies
the condition 0x < 22mspecified in Algorithm 2.
This algorithm is commonly used in HE acceleration studies
targeting a GPU [24], [30], [23], [42]. As noted by Sahu
et al. [23], the pre-computed constant µand the transient
operations (excluding the product c×µ) are preferably word-
sized. This condition imposes the restriction len(q)β2.
Note that the classical Barrett reduction may require zero,
one, or two correctional subtractions; see lines 4–7 in Al-
gorithm 2. As noted by Barrett [27], a second conditional
subtraction is required in approximately 1% of the cases. There
have been several attempts to modify Barrett’s algorithm to
eliminate the need for a second conditional subtraction. The
algorithms proposed by ¨
Ozerk et al. [21] and Lee et al. [26]
each require two correctional subtractions to fully reduce the
product of a= 994674970 and b= 994705408 modulo
q= 994705409, although we found experimentally that ¨
Ozerk
et al.’s proposed reduction algorithm only requires a second
conditional subtraction in 0.22% of cases.
Dhem–Quisquater [28] defines a class of Barrett modular
Algorithm 3 Dhem–Quisquater’s modified Barrett reduction
Require: m= len(q)β4,0x < 22m,µ=b22m+3
qc
Ensure: rem = xmod q
1: cx(m2)
2: quot (c×µ)(m+ 5)
3: rem xquot ×q
4: if rem qthen
5: rem rem q
6: return rem
reduction variants (with parameters αand β) that require at
most one correctional subtraction. A commonly used (see,
e.g., Kong and Philips [43] and Wu et al. [44]) instantiation
of Dhem–Quisquater’s class of algorithms is specified in
Algorithm 3(setting parameters α=N+ 3 and β=2,
as defined in Dhem–Quisquater [28]). Notably, this instan-
tiation is used in the PALISADE HE Software Library [41].
Although Algorithm 3provides an improvement in algorithmic
complexity over Algorithm 2, it further restricts the modulus
to at most length (β4) to ensure µis word-sized.
As discussed by Kim et al. [20], restrictions on the modulus
size are significant in the context of optimizing HE, as the
modulus size is inversely related to the workload size. To elab-
orate, polynomial multiplication is typically performed with
respect to a large composite modulus Q. If each prime factor
of Qis m-bits, then the Chinese Remainder Theorem can be
used to partition the computation of polynomial multiplication
with respect to Qinto dlen(Q)/mesimpler computations of
polynomial multiplication with respect to the m-bit factors.
For example, if len(Q) = 1240, then the restriction from
30-bit to 28-bit moduli increases the workload size (i.e.,
dlen(Q)/me) by 7.14%.
3
Algorithm 4 Proposed Barrett reduction optimized for a GPU
Require: m= len(q)β2,0x < 22m,µ=b22m+1
qc
Ensure: rem = xmod q
1: cx(m2)
2: quot (c×µ)(m+ 3)
3: rem xquot ×q
4: if rem qthen
5: rem rem q
6: return rem
Therefore, we propose Algorithm 4for use in HE imple-
mentations on a GPU. Similar to Algorithm 3, Algorithm 4is
an instantiation of Dhem–Quisquater [28] (for α=N+ 1 and
β=2) that requires at most one correctional subtraction.
However, Algorithm 4allows for moduli qof length up to
β2, and thus results in no increase in the workload size.
Figure 3provides a snapshot of the performance of various
modular reduction kernels on a V100 GPU. The detailed de-
scription of each parameter is further described in Table Iand
II in Section IV. The values in the Figure 3(a,b) are normalized
to the built-in implementation of modular reduction on GPUs
(which utilizes the modulo % operator). In Figure 3(a,b) we
see significant improvements in the proposed Barrett reduc-
tion, as marked by the speedups due to improved compute and
memory throughput. The performance improvements achieved
can be attributed to our implementation requiring at most
1correctional subtraction (as compared to 2for others).
Figure 3(c,d) enable us to see the primary causes of kernel
stalls for NTT and inverse-NTT workloads, respectively. Fig-
ure 3(c,d) highlights the reasons for the maximum number
of stalls while executing NTT and inverse-NTT kernels. In
Figure 3(c), the longest stall (measured in the average number
of cycles per instruction) for the NTT workload is due to a
“Math Pipe Throttle”, which results when the kernel begins to
saturate the ALU instruction pipeline (See Table I). Figure 3(d)
reports the cause of stalls in inverse-NTT, with the longest
stall caused by a “Wait”, which signifies the scheduler has an
abundance of “Ready” warps and is starting to saturate the
streaming multiprocessors (SMs) (See Table II).
In Figure 4, we present a comparison of the implementations
of the modular reduction algorithms described in this section.
We report the execution time of a single modular reduction
operation for 28, 29, and 30-bit prime numbers as run on a
V100 GPU. The operands and moduli are randomly sampled
from a uniform distribution. The classical Barrett reduction
algorithm is significantly faster than reduction by integer
division (i.e., the built-in reduction), as shown in Figure 4.
Algorithm 4has nearly identical performance to Algorithm 3
for 28-bit moduli (while permitting 29 and 30-bit moduli, as
well). Algorithm 4has a 1.22×speedup over the classical
Barrett reduction for 30-bit primes. To our knowledge, the
specific instantiation of Dhem–Quisquater modular reduction
specified in Algorithm 4does not appear in an open-source
library nor in the literature.
builtin
reduction
(x % q)
classical
Barrett
(Algo. 2)
modified
Barrett
(Algo. 3)
proposed
Barrett
(Algo. 4)
1.5
2.0
2.5
3.0
Execution time (us)
N/A for 29 bits
N/A for 30 bits
Modulus size
28 bits
29 bits
30 bits
Fig. 4. Execution times of modular reduction implementations for 28,29, and
30-bit prime numbers (on the V100 GPU), averaged over 10,000 iterations.
The error bars represent ranges. The “builtin reduction” uses the CUDA %
construct for modular reduction.
III. POLYN OM IA L MULTIPLICATION
For m > 0, define Zmto be the set {0,1,2, . . . , m 1}
together with the operations of modular addition (a, b)7→
(a+b) mod mand modular multiplication (a, b)7→ (a×
b) mod m. The naive algorithm for multiplying two polynomi-
als PN1
i=0 aixiand PN1
i=0 bixirequires order N2arithmetic
operations. It is well known [45] that the number of operations
can be reduced to the order of Nlog(N)using the Fast Fourier
Transform (FFT) algorithm.
It is convenient to represent a polynomial PN1
i=0 aixias an
N-dimensional coefficient vector a= (a0, a1, . . . , aN1).
A. Background: Number Theoretic Transform
In this section, we give a brief review of the Discrete Fourier
Transform (DFT) and the Fast Fourier Transform (FFT) for the
special case that the field of coefficients is Zq, for qa prime.
The DFT and FFT over Zqare both commonly—and often
confusingly—referred to as the Number Theoretic Transform
(NTT). In the classical setup for the NTT, the parameters N,
q, and ωsatisfy the following properties:
1) N > 1is a power of 2;
2) qis a prime number such that Ndivides q1; and
3) ωis a primitive Nth root of unity in Zq; i.e., ωi= 1 if
and only if iis a multiple of N.
The N-point NTT (DFT) with respect to ωis the func-
tion NTTω: (Zq)N(Zq)Ndefined by NTTω(a) =
(PN1
i=0 a[i]ωij )N1
j=0 . The inverse transformation of NTTω
is 1
NNTTω1. Famously, the cyclic convolution [46] of
vectors aand bin (Zq)Ncan be computed in the or-
der of Nlog(N)arithmetic operations via the expression
1
NNTTω1(NTTω(a)NTTω(b)), where denotes the
Hadamard product (i.e., entry-wise multiplication) on (Zq)N.
A closely related operation to cyclic convolution is nega-
cyclic convolution, which is widely known as polynomial mul-
tiplication in the context of lattice-based cryptography [47].
The setup for polynomial multiplication has parameters N,q,
and ψsatisfying the following properties:
1) N > 1is a power of 2;
2) qis a prime such that 2Nis a divisor of q1; and
3) ψis a primitive 2Nth root of unity in Zq(which implies
that ω=ψ2is a primitive Nth root of unity).
Let Ψand Ψ1denote the vector of “twiddle factors” in
(Zq)N, defined by Ψ[i] = ψiand Ψ1[i] = ψifor all i.
4
(b) (c)
Hadamard
Product
(a)
Fig. 5. (a) Negacyclic convolution block diagram. (b) Hadamard product and its neighboring butterflies. (c) Fusion of butterflies into Hadamard product.
Then the negacyclic convolution a~bof vectors aand bin
(Zq)Nsatisfies the following relation [48]:
a~b=Ψ11
NNTTω1(NTTω(Ψa)NTTω(Ψb))
The NTT algorithm (i.e., the FFT) used to compute the NTT
mathematical function (i.e., the DFT) consists of an iteration of
stages, in which computations are performed in the form of
butterfly operations. The computational graphs for the well-
studied (radix-2) Cooley–Tukey (CT) butterfly [49] and the
Gentleman–Sande (GS) butterfly [50] are shown in Figure 6.
Fig. 6. The Cooley–Tukey (left) and Gentleman–Sande butterflies (right).
P¨
oppelmann et al. [47] define an elegant algorithmic specifi-
cation for polynomial multiplication using NTTs based on the
CT and GS butterflies. Their design utilizes two specialized
variants of the FFT/NTT:
1) the merged CT NTT,NTTCT
nobo, defined by Roy et
al. [51] (see Algorithm 5); and
2) the merged GS NTT,NTTGS
bono, defined by
P¨
oppelmann et al. [47] (see Algorithm 6).
Algorithm 5 Merged CT NTT, NTTCT
nobo
Require: permuted twiddle factors Ψbr
1: m1
2: kN/2
3: while m<N do
4: for i= 0 to m1do
5: jF ir st 2×i×k
6: jLast j F irst +k1
7: ξΨbr[m+i]
8: for j=jF irst to jLast do
9: a[j]
a[j+k]a[j] + ξ×a[j+k] mod q
a[j]ξ×a[j+k] mod q
10: m2×m
11: kk/2
12: return a
Algorithm 6 Merged GS NTT, NTTGS
bono
Require: permuted twiddle factors Ψbr
1: mN/2
2: k1
3: while m1do
4: for i= 0 to m1do
5: jF ir st 2×i×k
6: jLast j F irst +k1
7: ξΨbr[m+i]
8: for j=jF irst to jLast do
9: a[j]
a[j+k]a[j] + a[j+k] mod q
ξ×(a[j]a[j+k]) mod q
10: mm/2
11: k2×k
12: return a
In Algorithms 5and 6,br denotes the bit-reversal of a
log2(N)-bit binary sequence, and Ψbr denotes the twiddle
factors permuted with respect to br; i.e., Ψbr[i] = ψbr(i)for
all iin [0, N ). Polynomial multiplication can be computed via
the merged CT and GS NTTs as follows [47]:
a~b=1
NNTTGS1
bono (NTTCT
nobo(a)NTTCT
nobo(b)).
(1)
The advantages of this algorithmic specification for polyno-
mial multiplication include the following:
1) Hadamard products omitted: The multiplication by pow-
ers of ψ, i.e., the Hadamard products with Ψand Ψ1,
are “merged” into the NTT computations, saving a total
of 3Nmodular multiplications.
2) Bit-reversal permutations omitted: The merged CT NTT
takes the input in normal order and returns the output
in a permuted bit-reversed order (hence no bo), and
vice versa for the merged GS NTT. This removes the
need for intermediate permutations to correct the order.
3) Good spatial locality: In the merged CT NTT, the
twiddle factors Ψbr are read in sequential order. In the
merged GS NTT, the twiddle factors are read sequen-
tially during each stage.
Zhang et al. [52] propose a technique to merge the
1
N-scaling operation in Equation (1) into the GS NTT. Rather
than performing entry-wise modular multiplication by 1
N,
Zhang et al. multiply the output of each butterfly operation
5
by 1
2modulo q. Observe that:
x
2mod q=(x
2if xis even
bx
2c+q+1
2if xis odd
The computation of x
2mod qcan be implemented without
divisions, products, or branching via the expression
x1+(x&1) ×((q+ 1) 1).
¨
Ozerk et al. [21] use this technique to merge 1
N-scaling into
NTTGS1
bono (also see their open-source code [53]). We write
NTTGS1
bono, 1
2
to denote the merging of NTTGS1
bono with
1
N-scaling. Incorporating this NTT into (1) gives the following
algorithm specification for polynomial multiplication:
a~b= NTTGS1
bono, 1
2
(NTTCT
nobo(a)NTTCT
nobo(b)) (2)
This algorithm specification is the basis for all of our imple-
mentations of polynomial multiplication.
B. Proposed optimization: fused polynomial multiplication
Alkim et al. [54] propose several techniques for integrating
the Hadamard product with its neighboring butterflies. They
specify polynomial multiplication algorithms involving one,
two, and three-stage integrations. These algorithms have sig-
nificantly reduced complexity for the multiplication of two
polynomials. However, the complexity of multiplying larger
numbers of polynomials may be significantly increased, espe-
cially when more stages are integrated.
We propose a single-stage fused polynomial multiplication,
which offers significant speedup for multiplying two polyno-
mials at minimized cost for multiplying larger numbers of
polynomials. Our proposal uses Karatsuba’s algorithm [31] to
reduce the number of modular products by N/2compared to
the single-stage algorithm of Alkim et al. [54].
Consider the computational subgraph of Equation (2) in-
duced by the final stages of NTTCT
nobo, the Hadamard product
, and the first stage of NTTGS1
bono, 1
2
. Each of the N/2
connected components in this graph are of the form
1
2buttGS
α1buttCT
αa0
a1buttGS
αb0
b1 (3)
for some twiddle factor αand inputs a0, a1, b0, and b1(see
Figure 5). Thus, the computation for each component consists
of 5 (modular) product operations, 2 scaling by 1
2operations, 6
sum/difference operations, and 2memory accesses. The output
of the computation in expression (3) is
a0×b0+α2×a1×b1mod q
a0×b1+a1×b0mod q(4)
Algorithm 7also computes expression (3), but requires 4
products, 0 scalings by 1
2, 5 sums/differences, and 1memory
access. This variation on Karatsuba’s Algorithm [31] relies on
the fact that a0×b1+a1×b0mod qis equivalent to
(a0+a1)×(b0+b1)a0×b0a1×b1mod q.
Algorithm 7 Butterflies fused into the Hadamard product
Require: [a0
a1],b0
b1(Zq)2, twiddle factor α2Zq
Ensure: [c0
c1]ha0×b0+α2×a1×b1mod q
a0×b1+a1×b0mod qi
1: prod1a0×b0mod q
2: prod2a1×b1mod q
3: sum1a0+a1mod q
4: sum2b0+b1mod q
5: prod3sum1×sum2 mod q
6: prod4α2×prod2 mod q
7: sum3prod1 + prod4 mod q
8: sum4prod3prod1 mod q
9: sum5sum4prod2 mod q
10: [c0
c1][sum3
sum5]
11: return [c0
c1]
We say that Algorithm 7fuses the CT and GS butterflies into
the Hadamard product.
To define the fused polynomial multiplication algorithm,
we first define truncated versions of the CT and GS NTTs.
Define the truncated CT NTT,[
NTTCT
nobo, to be the merged
CT NTT with the final stage omitted (i.e., line 3 in Algorithm 5
is replaced with while m < (N/2) do”). Likewise, define
the truncated GS NTT,[
NTTGS
bono, 1
2, to be the merged GS
NTT with the first stage omitted (i.e., line 3 in Algorithm 6
is replaced with while m > 1do”). Our proposed fused
polynomial multiplication is specified in Algorithm 8.
Algorithm 8 Proposed fused polynomial multiplication
Require: a,b(Zq)N, permuted twiddle factors Ψbr
Ensure: c=a~b
1: b
a=[
NTTCT
nobo(a)
2: b
b=[
NTTCT
nobo(b)
3: for i= 0 to N/21do
4: ub
a[2i]×b
b[2i] mod q
5: vb
a[2i+ 1] ×b
b[2i+ 1] mod q
6: w(b
a[2i] + b
a[2i+ 1]) ×(b
b[2i] + b
b[2i+ 1]) mod q
7: ywumod q
8: b
c[2i+ 1] yvmod q
9: zv×Ψbr[N
4+bi
2c] mod q
10: if iis even then
11: b
c[2i]u+zmod q
12: else
13: b
c[2i]uzmod q
14: c[
NTTGS1
bono, 1
2(b
c)
15: return c
The benefits of our proposed fused polynomial multiplica-
tion algorithm include the following:
1) Fewer operations: N/2fewer modular product oper-
ations, Nfewer scaling by 1
2operations, N/2fewer
sum/difference operations, and N/2fewer memory ac-
cesses (but N/4additional negations).
6
2) Number of twiddle factors halved: The second half of the
entries in the twiddle factor arrays for each of the merged
NTTs are not used in fused polynomial multiplication
and can be omitted.
3) Re-use of recently-accessed twiddle factors: The twiddle
factors read in the last stage of the truncated CT NTT
are immediately re-used in the fused Hadamard product.
IV. GPU ARCHITECTURE
We implement our polynomial multiplication kernels tar-
geting NVIDIA’s 7th generation Volta GPU architecture, the
V100 PCIe GPU with 16 GB onboard memory. The V100 has
a multi-level memory, as shown in Figure 7. The V100 features
a highly tuned high-bandwidth memory (HBM2), which is
called global memory in the CUDA framework. The global
memory, being the largest in capacity, has the highest latency
to access data (1029 cycles) [55]. The V100 provides a 128
KB L1 data cache and a 128 KB L1 instruction cache per
SM, as well as a unified L2 cache for data and instructions
(6.1MB in size). Each SM on a V100 has a shared memory
(each configurable in size up to 96 KB). Data accesses to
shared memory are much more efficient (i.e., 19 cycles) as
compared to accesses to global memory (1029 cycles) [56].
Effective use of the memory hierarchy, and especially shared
memory, on a GPU is critical to obtaining the best perfor-
mance [57]. Our single-block implementation of NTT utilizes
shared memory for local data caching, thus reducing the
number of redundant fetches from global memory [58] by
a factor of log(N)times (where Nis the size of the input
coefficient array). Furthermore, we improve cache efficiency
by increasing the spatial locality of our data access patterns,
exploiting memory coalescing on the GPU [58], as described
in Section V-C.
We obtain performance metrics for our kernels using
hardware performance counters and binary instrumentation
tools. We explore performance bottlenecks using a variety
of tools including the NVIDIA Binary Instrumentation Tool
(NVBit) [59] for tracing memory transactions, the Nsight
Compute for fetching performance counters, and the Nsight
Systems [60] to obtain kernel scheduler performance, as
well as measuring synchronization overheads. We compare
64 KB
Registers
High Bandwidth Memory [ 16 GB ]
Unified L2 Cache [ 6144 KB ]
64 B Cache Line
16-way set-associative
Shared Memory
[upto 96 KB]
RF
T
RF
T
RF
T
RF
T
RF
T
RF
T
RF
T
RF
T
L1
Data Cache
128 KB
Latency (in cycles)
L2 193
L0
12 KB
Instruction
Cache
TLBs
L1
Instruction Cache
128 KB
L1 Data 28
Shared 19
HBM 1029
Fig. 7. V100 GPU memory hierarchy and latency comparison.
kernel performance based on Architectural Profile” and “Stall
Profile” plots. The Arch Profile” compares the relative change
as compared to a baseline (see Table I), whereas the “Stall
Profile” provides information on the primary causes of a kernel
stall during execution (see Table II).
Parameter Description
SM Throughput % of cycles the SM was busy
Avg. IPC Average # of instructions per cycle
ALU ALU Pipeline utilization
DRAM B/W % of peak memory transactions
the DRAM processed per second
L1$ and L2$ B/W % of peak memory transactions the L1$
and L2$ processed per second respectively
L1$ and L2$ Hit-Rate % of memory transactions the L1$
and L2$ fulfilled successfully
Regs/Thread # of registers used by each thread of the warp
Issued Warps Avg. # of warps issued per second by scheduler
TABLE I
DESCRIPTION OF THE ARCH PROFI LE PAR AME TE RS.
Type of stall Reason
Long Scoreboard Waiting for a scoreboard dependency
on a L1$ operation
Math Pipe Throttle Waiting for the ALU execution pipe
to be available
Wait Waiting on fixed latency execution dependency
Indicates highly optimized kernel
Not Selected Waiting for the scheduler to select the warp
Indicates warps oversubscribed to scheduler
Selected Warp was selected by the micro scheduler
Barrier Waiting for sibling warps at sync barrier
Indicates diverging code paths before a barrier
LG Throttle Waiting for the L1 instruction queue
Short Scoreboard Scoreboard dependency on shared memory
Indicates higher shared memory utilization
MIO Throttle Stalled on MIO (memory I/O) instruction queue
Branch Resolving Waiting for a branch target to be computed
Dispatch Stall Warp stalled because dispatcher holds back
issuing due to conflicts or events
IMC Miss Waiting for an immediate cache (IMC) miss
No Instruction Waiting after an instruction cache miss
TABLE II
DESCRIPTION OF THE STALL PRO FIL E PARA MET ER S.
V. OPTIMIZED NTT KER NE LS
We observe that the NTT kernel is a memory-bound work-
load, heavily bottlenecked by the GPU’s DRAM latency. The
butterfly operation is one of the key computations within
the NTT kernel. This operation is characterized by strided
accesses, with the stride varying with each stage. The changes
in the stride lead to non-sequential memory accesses, reducing
the spatial locality of the NTT kernel. To effectively leverage
memory coalescing, we can partition data carefully across
CUDA threads [61]. We propose three different implemen-
tations of NTT kernels, each optimized for different input
sizes and employing different data partitioning techniques.
We follow a similar approach here as described by ¨
Ozerk
7
Speedup
SM Throughput
Avg. IPC
ALU
DRAM B/W
L1$ B/W
L1$ Hit-Rate
L2$ B/W
L2$ Hit-Rate
Regs/Thread
Issued Warps
Architectural Parameters of Shared mem
60
40
20
0
20
% change over Global mem
Workload
NTT
iNTT
Long Scoreboard
Math Pipe Throttle
Wait
Not Selected
Barrier
LG Throttle
Short Scoreboard
MIO Throttle
Branch Resolving
Dispatch Stall
IMC Miss
No Instruction
NTT Workload Stall Histogram
0
1
2
3
Avg. stalled CPI
Memory Type
Global Mem
Shared Mem
Long Scoreboard
Math Pipe Throttle
Wait
Not Selected
Barrier
LG Throttle
Short Scoreboard
MIO Throttle
Branch Resolving
Dispatch Stall
IMC Miss
No Instruction
inverse-NTT Workload Stall Histogram
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Avg. stalled CPI
Memory Type
Global Mem
Shared Mem
Fig. 8. (a) Architectural performance profile of shared memory NTT and iNTT workloads compared against respective global memory workloads. (b) Stall
profile of NTT workload comparing global and shared memory kernels. (c) Stall profile of inverse-NTT workload comparing global vs. shared memory kernels.
et al. [21], though we leverage a number of algorithmic
optimizations, combined with code optimizations, that are
unique to this work.
The three implementations of polynomial multiplications
proposed in this work are as listed below:
LOS-NTT (Latency-optimized Single-block NTT): For
single polynomial multiplication with N211.
LOM-NTT (Latency-optimized Multi-block NTT): For
single polynomial multiplication with N > 211.
TOM-NTT (Throughput-optimized Multi-block NTT):
For multiple polynomial multiplications with no con-
straints on N.
A. Latency optimized Single-block NTT
The LOS-NTT kernel performs all the NTT operations
within a single block of the CUDA kernel. Using a single block
for computing the entire NTT workload has the following
advantages:
The overhead of a single block-level barrier
(syncthreads) is significantly lower than a kernel-
level (multi-block) barrier.
We can leverage shared memory, which can only be
addressed within the scope of a single block.
Since all threads of a block share the same L1 and L2
caches, and L1 is write-through, write updates by any
thread are reflected in L2 across all threads.
Our LOS-NTT implementation consists of two phases,
separated by a block-level barrier. The first transfers the
input coefficient vectors (of size N) from high latency global
memory to the faster, low latency shared memory. The second
phase performs the merged NTTs, as defined in Algorithms 5
and 6. This phase consists of two nested loops. The first
iterates over the log(N)stages of the CT algorithm. This
is followed by the second loop of N
2, iterating over the
elements of the input coefficient vector. These iterations are
free from any loop-carried dependencies, allowing them to
be run in parallel. We capitalize on this inherent parallelism
by computing each iteration of the second loop in parallel,
assigning each loop iteration to a separate CUDA thread. We
further improve the performance of our kernel with four GPU-
specific optimizations.
1) Shared Memory Optimization: Each stage of the CT im-
plementation is characterized by multiple butterfly operations
of varying strides. These butterfly operations result in strided
memory accesses, with the step size varying from 1to N
2
(where Ncan be as large as 216). We optimize for memory
access efficiency by storing the input coefficient vector, as
well as the outputs of butterfly operations, in persistent shared
memory, which is significantly faster than accessing global
memory. We utilize 8KB of shared memory per SM for storing
the input polynomial coefficients, as well as the output of
intermediate stages. Using shared memory incurs the overhead
of transferring input coefficients to shared memory and the
final results back to global memory. Despite these additional
overheads, incorporating the use of shared memory allows
us to obtain a 1.25×speedup over the use of only global
memory (Figure 8). Figure 8(a) denotes a large drop in L1$
and L2$ performance. The primary reason for this degraded
performance is memory transactions that access the shared
memory do not count towards L1and L2cache performance.
Since all the coalesced memory transactions to the global
memory (which counted towards the cache performance) are
now redirected towards the shared memory (which is excluded
from cache performance counters), the L1and L2cache
bandwidth and hit-rate take a performance hit. Figure 8(b,c)
identifies the primary causes of stalls for the NTT and inverse-
NTT kernels, respectively. The“Long Scoreboard” stall is
caused by dependencies in L1 cache operations. The large drop
in the stall values for the “Long Scoreboard” in Figure 8(b)
is an indicator of memory pressure being reduced in the L1
cache and indirectly in the L2 cache and DRAM. Similarly, in
Figure 8(c), the increase in the average “Math Pipe Throttle”
stall values is tied to the compute throughput of the inverse-
NTT kernel.
2) Barrett’s Modular Reduction Optimization: We further
accelerate our NTT kernel with the use of our modified Barrett
implementation, specifically designed for GPU execution, as
shown in Section II-B. The smaller number of correctional
subtractions present in our implementation allows us to obtain
a1.85×average speedup over previous work [21] and a
1.72×speedup over the builtin modulus operation. We also
obtain similar execution times to the 28-bit modified Barrett’s
reduction, as reported for PALISADE [41]. To our knowledge,
8
our proposed Barrett variant is the fastest Barrett modular
reduction for general 30-bit and 62-bit moduli.
3) Mixed Radix Optimization: The naive implementation
of NTT and inverse NTT used in this study is based on a
radix-2algorithm. In this implementation, each thread within a
block operates on 2elements of the input coefficient array. We
improve the performance of our kernel by experimenting with
radix-4,8, and 16 implementations that distribute 4,8, and 16
elements per thread, respectively. Higher radix implementa-
tions improve temporal locality, as the input coefficient vector
data is reused. Unfortunately, this improvement in the temporal
locality is associated with a significant loss in parallelism. We
also experiment with kernels that use radix 4or radix 8for
single-block kernels and radix 16 for multi-block.
Radix 2
Radix 4
Radix 4/16
Radix 8/16
2D Serial
2D Pipelined
NTT workload radix comparison
0
10
20
30
40
50
Duration [us]
Radix 2
Radix 4
Radix 4/16
Radix 8/16
2D Serial
2D Pipelined
inverse-NTT workload radix comparison
0
10
20
30
40
50
Duration [us]
0
20
40
60
80
100
% of Theoretical Peak
0
20
40
60
80
100
% of Theoretical Peak
Duration
Compute Throughput
Memory Throughput
L1$ Throughput
L2$ Throughput
DRAM Throughput
Fig. 9. Higher radix comparison for (a) NTT and (b) inverse-NTT kernels.
We also experiment with 2-dimensional NTT implemen-
tations. A 2D NTT maps the data into a matrix form, thus
treating our coefficient as a row-major square matrix. This
allows us to perform a column-wise NTT followed by a row-
wise NTT. An N1degree polynomial can be mapped into
aN×Nmatrix. This also divides the NTT kernel into
two stages (column-wise NTT and row-wise NTT). The first
stage computes Nnumber of N-point column-wise NTT
operations, followed by the second stage that computes N
number of N-point row-wise NTT. Each N-point NTT is
mapped into a block with N
2threads, where each thread is
responsible for computing a radix-2butterfly. The 2D NTT
approach allows us to map the data while preserving spatial
locality. We further accelerate our computation by pipelining
the two stages of row-wise and column-wise NTT operations,
thus presenting two variants of our 2Dimplementation (2D
Serial and 2DPipelined). This approach provides an average
of 2.91×speedup for NTT and inverse-NTT kernel over the
naive radix-2implementations (Figure 9). This improvement
in execution time can be largely attributed to the increased
memory throughput for NTT (Figure 9(a)), as well as inverse-
NTT (Figure 9(b)). The improved memory throughput also
contributes to the increased compute throughput, as continuous
streaming of data from DRAM no longer starves the SMs of
input operands.
4) Fused Polynomial Multiplication Optimization: Finally,
we propose an optimization that fuses together the last stage
of merged CT NTT, the Hadamard product, and the first stage
of merged GS NTT. Figure 5(c) shows the implementation of
our fused polynomial multiplication. Our implementation of
the fused kernel significantly reduces the number of multipli-
cation operations and re-uses recently-cached twiddle factors.
Experimental results show that we reduce the execution time,
resulting in a 6.1% and 2.4% improvement as compared to the
naive implementation for polynomial multiplication, for input
sizes of N= 211 and N= 216, respectively.
B. Latency optimized Multi-block NTT
Fig. 10. The Multi-block NTT task distribution.
The LOM-NTT kernel is designed to handle large input
arrays (N > 211). The LOM-NTT kernel distributes tasks
using a similar strategy as used in the LOS-NTT kernel, except
that it spreads them over multiple blocks. This allows us to
employ multiple SMs to execute the workload in parallel.
The LOM-NTT kernel splits a single N-point NTT between
multiple blocks. Because of the use of multiple blocks, this im-
plementation requires kernel-wide barriers for synchronization
between stages. We use the LOM-NTT kernel to decompose
a single N-point NTT into multiple 211-point NTTs. Then we
incorporate our LOS-NTT (Single-block) kernel to evaluate
all the 211-point NTTs to harness the optimizations of shared
memory and block-level barriers. We show the distribution for
our LOM-NTT for N= 216 in Figure 10.
C. Throughput-optimized Multi-block NTT
The throughput-optimized kernel is designed to compute
multiple NTTs simultaneously. Unlike the latency-optimized
kernel that computes just a single NTT operation, TOM-
NTT is optimized to compute up to 215 NTT operations
simultaneously, with each NTT computation being a 216-point
NTT (the size of each input coefficient vector is 216). The
TOM-NTT kernel is fed 2input matrices. The first matrix
holds the input coefficient vectors. These vectors, of size 216,
are stacked in the matrix in the row-major format. This matrix
is then transferred to GPU and stored in global memory in a
column-major format, coalescing reads across threads into a
single memory transaction. The second input matrix contains
the twiddle factors. We store twiddle factors in a similar way
as the coefficient matrix. Each input matrix is of dimension
216 ×215. Both matrices, when combined, completely fill the
DRAM storage of 16 GB on the V100 GPU. The TOM-
NTT kernel executes the 28-point NTT over 32,768 vectors in
628 ms. With an average execution time is 19.17 µsper NTT
operation, this kernel exhibits close to linear weak scaling.
9
VI. RE SU LTS
A. Experimental Methodology
We present three different NTT kernels in this work, along
with four optimizations tailored for the GPU platform. We
evaluate the performance of our Single-block NTT kernel
for input coefficient vector sizes of N= 211 and of our
Multi-block kernel for vector sizes of N= 212 to 216.
We incrementally add each of the four optimizations to our
NTT kernels and report performance improvements. Twiddle
factors are pre-computed on the CPU and hence do not add
to the compute overhead on the GPU. We report on multiple
performance metrics for each approach, leveraging profiling
tools on the GPU platform. For each optimization, the speedup
achieved is reported using the respective non-optimized kernel
as the baseline for comparison. Finally, we evaluate weak
scaling for our throughput-optimized TOM-NTT kernel.
B. Performance Metrics
We incrementally add optimizations to our NTT kernels
and report performance improvements in Table III (for input
coefficient size N= 216). For each optimization, the speedup
achieved is reported, using the respective non-optimized kernel
as the baseline for comparison.
Optimization Relative
Speedup
L1$
Throughput
DRAM
Throughput
SM-only 1.2× 27.3% +20.0%
SM + Alg4 1.72×+10.86% +3.2%
SM + Alg4 + 2D 2.91×+5.85% +16.14%
SM + Alg4 + 2D + FHP 1.02×+0.3% 0.33%
TABLE III
NTT KERNEL OPTIMIZATIONS: SM = SHA RE D MEM ORY, ALG 4 = OUR
PROPOSED REDUCTION,2D=MIX ED RADIX 2D N TT, FH P = FU SED
HADAMARD PRODU CT (NTT KERNEL WITH N= 216 AND
dlog2(q)e= 62 US ED A S BAS ELI NE )
Our shared memory optimized kernel, when compared
against the global memory kernel, achieves a 20% improve-
ment in DRAM bandwidth utilization and a 1.2×speedup.
Data is transferred between DRAM and shared memory using
coalesced memory transactions, improving DRAM bandwidth
utilization.
Next, we compare the execution time for our NTT kernel
implementation by incorporating various modular reduction
techniques, as shown in Figure 3. We compare our best
performing NTT kernel (highlighted in Table IV) to ¨
Ozerk
et al. [21] and find a 1.85×speedup for N= 216 and a
1.13×speedup for N= 214. The use of radix 4,8, and 16
and 2Dimplementations provide additional speedup due to the
increased temporal, as well as spatial, locality in 4,8, and 16-
point butterfly operations, as compared to the baseline radix
2implementation. The effects of increased data locality are
reflected in the 5.85% improvement in the L1 cache hit-rate.
Our best performing kernel, that of 2DNTT, achieves a 2.91×
speedup over a radix 2implementation (Figure 9). Our fused
polynomial multiplication kernel reduced the execution time
for the last stage of the merged CT NTT kernel, the Hadamard
11 12 13 14 15 16 17
log(N)
0
5
10
15
20
single block timing (us)
Fig. 11. Timing for the Single-block NTT.
product, and the first stage of the merged GS NTT kernel,
from 8.5µsdown to 6.5µs, resulting in a 1.3×speedup
as compared to its non-fused counterpart. When incorporated
within a polynomial multiplication kernel, this translates to a
6.1% improvement for Single-block kernel (for size N= 211)
and a 2.4% improvement for Multi-block kernel (for size
N= 216).
We also measured the scalability of our fastest single-block
NTT implementation. As our multi-block kernel implemen-
tation leverages our Single-block code, we also analyzed the
performance of the Single-block kernel by varying the input
polynomial size and the hardware resources used. On each
iteration, we double the size of the input array, as well as the
number of potential SMs utilized (by doubling the number
of blocks in the kernel). We observe that our Single-block
kernel exhibits close to linear weak scaling, as execution times
remain near constant as we increase both the input size and
the hardware resources utilized (Figure 11).
We also evaluate our TOM-NTT kernel that is optimized for
operating on a large number of NTT operations simultaneously
(working with up to 215 input coefficient vectors, each of size
216 elements). With an average execution time of 19.17 µs
per NTT operation, this kernel exhibits close to linear weak
scaling. Including all optimizations, our NTT kernels achieve a
speedup of 123.13×and 2.37×over the previous state-of-the-
art CPU [29] and GPU [21] implementations of NTT kernels,
respectively.
VII. REL ATED WO RK
Table IV presents runtimes of various implementations of
NTT and iNTT, adding to Table 8 in the work by ¨
Ozerk et
al. [21] with our own runtimes. Prior studies have explored
accelerated NTT on FPGAs [62] and custom accelerators [8].
But these custom solutions are not typically found on general-
purpose systems. On the other hand, GPUs are ubiquitous and
easily programmed. In recent years, there has been growing
interest in using a GPU to exploit the parallelism present in
NTT [19], [20], [21]. In particular, ¨
Ozerk et al. [21] propose
an efficient hybrid kernel approach to accelerate NTT. Our
LOS-NTT and LOM-NTT kernels are inspired by their work,
however, we provide some further optimizations such as our
fused Hadamard product, an improved version of Barrett
reduction, and explored higher radix NTTs. Kim et al. [20]
also propose some optimizations on NTTs, such as batching
using shared memory. We explored how those optimizations
10
Work Platform Ndlog2(q)eNTT
(µs)
iNTT
(µs)
cuHE [40]GTX 690 214 64c56 65.3
215 64c71.2 83.6
cuHE [40],a Tesla K80 214 64c12.9 12.5
215 64c19 21.6
cuHE [40],b GTX 1070 214 64c66.8
Faster NTT [63]Tesla K80 214 64c9.6 9.7
215 64c15.3 16.2
Accl NTT [24]GTX 1070 214 64c57.8
Bootstrap HE [20] Titan V214 60 44.1
215 60 84.2
Re-encrypt [23] GTX 1050 214 NA 255
215 NA 470
RTX 1080 214 NA 375
215 NA 425
Efficient NTT [21] GTX 980 214 55 51 41
215 55 73 52
GTX 1080 214 55 33 20
215 55 36 24
Tesla V100 214 55 29 21
215 55 39 23
Our Work Tesla A100 214 62 13.3 10.9
216 62 16.5 18.7
Tesla V100 214 30 8.7 10.0
216 30 13.1 13.4
214 62 11.5 11.9
216 62 16.4 17.3
uses constant prime q=0xFFFFFFFF00000001
aresults are from [63]bresults are from [24]
cactual qiis restricted by q2
in < 264 232 + 1
TABLE IV
COM PARI SON T O REL ATED W ORK
could address the limitations we faced when implementing a
kernel with a radix higher than 4.
Alkim et al. [54] define and analyze several algorithms very
similar to Algorithm 8. They not only consider truncating their
NTTs by one stage but by two and three stages. Although some
of Alkim et al.’s algorithms utilize Karatsuba’s Algorithm,
they do not consider using Karatsuba’s Algorithm to merge
a single innermost pair of NTT stages. In our tests, our
fused polynomial multiplication implementation provides an
additional speedup of 6.1% and 2.4% as compared to the naive
implementation for polynomial multiplication for input sizes
of N= 211 and N= 216, respectively using Alkim et al.’s
(k1)-level NTT multiplication algorithm.
There is a Barrett reduction variant proposed by Yu et
al. [64] that requires no correctional subtractions. We found
that this algorithm has severe trade-offs in terms of operational
complexity as a function of workload size, which makes it less
attractive for use with HE.
VIII. CONCLUSION
In this work, we presented an analysis and proposed im-
plementations of polynomial multiplication, the key compu-
tational bottleneck in lattice-based HE systems, while tar-
geting the V100 GPU platform. Specifically, we analyzed
Barrett’s modular reduction algorithm and several variants.
We studied the interplay between algorithmic improvements
(such as multi-radix NTTs) and low-level kernel optimizations
tailored towards the GPU (including memory coalescing). Our
NTT optimizations achieve an overall speedup of 123.13×
and 2.37×over the previous state-of-the-art CPU [29] and
GPU [21] implementations of NTT kernels, respectively.
ACK NOW LE DG EM EN TS
This work was supported in part by the Institute
for Experiential AI, the Harold Alfond Foundation,
the NSF IUCRC Center for Hardware and Embedded
Systems Security and Trust (CHEST), the RedHat
Collaboratory, and project grant PID2020-112827GB-
I00 funded by MCIN/AEI/10.13039/501100011033.
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