Automated Formal Analysis of Temporal Properties of Ladder Programs

Abstract

Programmable Logic Controllers are industrial digital computers used as automation controllers in manufacturing processes. The Ladder language is a programming language used to develop software for such controllers. In this work, we consider the description of the expected behaviour of a Ladder program under the form of a timing chart, describing a scenario of execution. Our aim is to prove that the given Ladder program conforms to the expected temporal behaviour given by such a timing chart. Our approach amounts to translating the Ladder code, together with the timing chart, into a program for the Why3 environment for deductive program verification. The verification proceeds with the generation of verification conditions: mathematical formulas to be checked valid using automated theorem provers. The ultimate goal is twofold. On the one hand, by obtaining a complete proof, one verifies the conformity of the Ladder code with respect to the timing chart with a high degree of confidence. On the other hand, in the case the proof is not fully completed, one obtains a counterexample, illustrating a possible execution scenario of the Ladder code which does not conform to the timing chart.

Full text

International Journal on Software Tools for Technology Transfer (2022) 24:977–997
https://doi.org/10.1007/s10009-022-00680-0
GENERAL
Special Issue: FMICS 2021
Automated formal analysis of temporal properties of Ladder programs
Cláudio Belo Lourenço1·Denis Cousineau2·Florian Faissole2·Claude Marché1·David Mentré2·Hiroaki Inoue3
Accepted: 18 October 2022 / Published online: 1 November 2022
© The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2022
Abstract
Programmable Logic Controllers are industrial digital computers used as automation controllers in manufacturing processes.
The Ladder language is a programming language used to develop software for such controllers. In this work, we consider
the description of the expected behaviour of a Ladder program under the form of a timing chart, describing a scenario
of execution. Our aim is to prove that the given Ladder program conforms to the expected temporal behaviour given by
such a timing chart. Our approach amounts to translating the Ladder code, together with the timing chart, into a program
for the Why3 environment for deductive program verification. The verification proceeds with the generation of verification
conditions: mathematical formulas to be checked valid using automated theorem provers. The ultimate goal is twofold. On the
one hand, by obtaining a complete proof, one verifies the conformity of the Ladder code with respect to the timing chart with
a high degree of confidence. On the other hand, in the case the proof is not fully completed, one obtains a counterexample,
illustrating a possible execution scenario of the Ladder code which does not conform to the timing chart.
Keywords Ladder language for programming PLCs ·Timing charts ·Formal specification ·Deductive verification ·Why3
environment
1 Introduction
Programmable Logic Controllers (PLCs for short) are indus-
trial digital computers used as automation controllers in
manufacturing processes, such as assembly lines or robotic
devices. PLCs can simulate the hard-wired relays, timers and
sequencers they have replaced, via software that expresses
the computation of outputs from the values of inputs and
internal memory. The Ladder language, also known as Lad-
der Logic, is a programming language used to develop PLC
software. This language uses circuit diagrams of relay logic
hardware to represent a PLC program by a graphical diagram.
This language was one of the first available for programming
This work has been partially supported by the bilateral contract
ProofInUse-MERCE between Inria team Toccata and Mitsubishi
Electric R&D Centre Europe, Rennes.
BClaude Marché
Claude.Marche@inria.fr
1CNRS, Inria, LMF, Université Paris-Saclay, 91190
Gif-sur-Yvette, France
2Mitsubishi Electric R&D Centre Europe, Rennes, France
3Mitsubishi Electric Corporation, Amagasaki, Japan
PLCs, and is now standardised in the IEC 61131-3 standard
[29] among other languages [9] for programming PLCs. The
Ladder language is still widely used and very popular among
technicians and electrical engineers.
Because of the widespread use of PLCs in industry, veri-
fying that a given Ladder program conforms to its expected
behaviour is of critical importance. In this work, we consider
the description of the expected temporal behaviour under the
form of a timing chart, describing a scenario of execution.
Timing charts are commonly used in the industry to specify
small- to medium-sized programs, like in the Function Blocks
libraries that are shipped by PLC manufacturers together with
their programming software. Our approach consists of auto-
matically translating the Ladder code, and the timing chart
all together, into a program written in the WhyML language,
which is the input language of the generic Why3 environment
for deductive program verification [8]. In WhyML, expected
behaviours of program are expressed using contracts, which
are annotations expressed in formal logic. The Why3 envi-
ronment provides a set of software tools for checking that
the WhyML code conforms to these formal contracts. This
verification process is performed using automated theorem
provers as back-ends, so that at the end, if the back-end proof
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