Design of a Quantum circuit for 4-Qubit multiplier using IBM Quantum Computer

Abstract

Reversible gates have been one of the emerging research areas in these days. The reversible gates have several applications in the fields of low power CMOS, DNA computing, optical, nanotechnology etc. Quantum computing is one of the fastest and upcoming nanotechnologies that can implement the digital logical circuits using reversible logic gates. In this paper, CNOT, TOFFOLI, FREDKIN and PERES reversible logic gates have been implemented on IBM quantum computer. An efficient one-bit full adder is going to be proposed using the reversible gates like CNOT and TOFFOLI. Later, a 4x4 multiplier will be developed using the proposed one-bit full adder. The proposed multiplier is proved to perform faster calculations compared to the earlier multipliers. The simulation of the presented modules will be done on IBM Quantum computer and the respective probabilities can be observed for different inputs.

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Design of a Quantum circuit for 4-Qubit multiplier
using IBM Quantum Computer
A Arunkumar Gudivada (  aarunkumarg@gmail.com )
Aditya College of Engineering & Technology
Asisa Kumar Panigrahy
Gokaraju Rangaraju Institute of Engineering & Technology
Research Article
Keywords: Quantum computing, IBM Q composer, Reversible gates, Full adder, Multiplier
Posted Date: August 4th, 2022
DOI: https://doi.org/10.21203/rs.3.rs-1909815/v1
License:   This work is licensed under a Creative Commons Attribution 4.0 International License. 
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Abstract
Reversible gates have been one of the emerging research areas in these days. The reversible gates have
several applications in the elds of low power CMOS, DNA computing, optical, nanotechnology etc.
Quantum computing is one of the fastest and upcoming nanotechnologies that can implement the digital
logical circuits using reversible logic gates. In this paper, CNOT, TOFFOLI, FREDKIN and PERES reversible
logic gates have been implemented on IBM quantum computer. An ecient one-bit full adder is going to
be proposed using the reversible gates like CNOT and TOFFOLI. Later, a 4x4 multiplier will be developed
using the proposed one-bit full adder. The proposed multiplier is proved to perform faster calculations
compared to the earlier multipliers. The simulation of the presented modules will be done on IBM
Quantum computer and the respective probabilities can be observed for different inputs.
1. Introduction
Quantum computing is the fastest computational method to compute complex mathematical operations.
It performs rather fast compared to classical computer. Like classical computer, a quantum computer has
two bits namely qubits as |0 > and |1>. The quantum circuits can be implemented in two different ways.
One is using IBM quantum experience online tool or wiring a qiskit code in jupyter notebook. In this paper,
IBM Quantum computer has been used to develop the quantum circuit. It is one of the easiest ways to
design a quantum computer by the researchers. IBM Quantum computer has a composer which allows us
to develop the circuits in very easy way. This online platform was developed by IBM in May 2016 that
works under IBM cloud. The initial version supports only ve qubits and later it was upgraded to 16 to 20
qubits to perform the online quantum circuit simulations.
2. Qubit And Quantum Circuits
A qubit (or quantum bit) is analogous to normal binary bits in classical computer where the data is
described in the form of 0’s and 1’s. In quantum computing the information is represented in terms of
qubits. Unlike classical bits, a qubit has a basis state which is represented in terms of a matrix.
|0> = -------------(1)
|1> = -------------(2)
A quantum qubit may be in any of the above state or a linear combination of the above two like
Ψ = α|0>+β|1>, where α, β ϵ ℂ -------------(3)
Here α and β belong to complex numbers.
The probability of becoming a 0 or 1 can be expressed as
( )
1
0
( )
0
1

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------------(4)
-------------(5)
Three main and basic gates of quantum circuits are Pauli’s X, Y and Z gates. Pauli’s X gate acts as NOT
gate that converts the qubit 0 to 1.
The Pauli’s Y gate is used to add the phase of to the other qubit. That is when input is |0 > then output of
the Y-gate is |1 > and when input is |1 > then output of Y-gate is |0>.
The Pauli’s-Z gate is same as Identity gate when input is |0>, however for input |1 > the Z-gate output is
negative of |1 > which is opposite of the block sphere.
Bloch sphere is used for the representation of coecients along with phase angles of quantum states.
The qubits are located opposite sides of block sphere that is top and bottom as shown in gure
3. Reversible Gates
A reversible gate is a logical circuit with number of inputs equal to number of output unlike conventional
logic gates. That means the advantage of reversible gate is the output states can uniquely determine the
input states. There is no concept of Fan-in and Fan-out in reversible logic gates. Classical logic circuits
represent a deterministic state whereas a reversible gate represents a probabilistic state which is a
nondeterministic state or process. The output is a single valued state or a linear combination of two
states. There are several reversible logic gates that have been designed and developed using standard
quantum logic gates. Among all these, Feynman Gate (CNOT) gate has a great application in majority of
the quantum circuits. It is a controlled not gate.
3.1. Feynman Gate (CNOT)
Unlike classical inverter gate, a Feynman Gate is a Controlled NOT gate. CNOT is a 2x2 quantum gate.
That means it passes two inputs through the quantum circuit and reproduces two outputs. One output is
same as the input and the other output is controlled by the second input. This can be mathematically
expressed by considering the inputs and outputs as A, B and M, N respectively.
First output: M = A
Second output: N = A ⊕ B
3.1.1. Implementation on IBM-Q
The above circuit is implemented on IBM quantum computer by using two qubits. Feynman gate has one
qubit to control the other input vector named as target bit. When the control bit is 0, then there is no
P
(0) = |
α
|2
|
α
|2+|
β
|2
P
(1) = |
β
|2
|
α
|2+|
β
|2
i
i
–
i

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change in the output. When the control bit is 1 then the output will be ipped or toggled. The Feynman
gate has a quantum cost of 1.
3.2. Toffoli Gate
Toffoli gate is a 3x3 quantum gate. It has 3 inputs and 3 outputs. The input vector is having three qubits
viz. A, B, C and the output vectors are related to the input vectors as M = A, N = B, O = AB ⊕ C. A and B are
control bits and C is the target bit. Toffoli gate acts as an AND gate when the target bit is an ancilla bit
which is always set to 0.
3.2.1. Implementation on IBM-Q
The above circuit is implemented on IBM quantum computer by using three qubits. Among 3 inputs of
Toffoli gate, two input vectors are acting as control bits and last bit as target bit. When two control bits
are 0’s, then there is no change in the output. When the two control bits are 1’s then the output will be
ipped or toggled.
3.3. Peres Gate
It is a 3x3 gate, with the input data as I consisting of three qubits A, B, C and the output vectors as M, N, O.
The output is derived as M = A, N = A ⊕ B and O = AB ⊕ C. Peres gate acts as half adder when the third
input is an ancilla bit which is always set to 0.
3.3.1. Implementation on IBM-Q
Peres gate is a 3x3 gate. Peres gate is represented by a Controlled CNOT gate followed by a CNOT gate.
The rst output is same as the input, the second output is the modulo-2 addition of the rst two input
vectors whereas the third output bit as the modulo-2 addition product of rst two inputs and last input.
3.4. Fredkin Gate
Fredkin gate is a 3x3 gate. It has three input vectors for example A, B and C and the output vectors for
example E, F and G. The output states are determined by E = A, F = A′B ⊕ AC and G = A′C ⊕ AB. These
states are represented and truth table is also depicted in the Fig.11(a) and 11(b) respectively.
3.4.1. Implementation on IBM-Q
The above gate is implemented on IBM quantum computer using three qubits. The product and modulo-2
operation is as shown in Fig.11. For this operation the circuit needs two CNOT gates on controlled CNOT
gate in between them.
4. Full Adder

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A full adder is a logical circuit that adds three one bit numbers referred to as A, B, Cin. A and B are said to
be current inputs to be added whereas Cin is a carry that is coming from previous stage. As one full adder
is capable to add only three one bit numbers, it is essential to use more than one full adder during the
addition of multi bit input numbers. There are two output bits namely sum and carry out which are often
represented by S and Cout. The outputs would be expressed as
Sum
=
A
⊕
B
⊕
C
in ---------- (6)
and Cout = (
A
⋅
B
) + ((
A
⊕
B
) ⋅ Cin) ---------- (7)
Figure13 depicts the one bit full adder’s block diagram. To implement the sum and carry out one may
need combinational logic circuits like half adder and few basic gates. According to the expression of the
sum and carry from equations (6) and (7), the sum require XOR gate and two AND gates and one OR gate
is required for Carry out operation. The logical circuit is depicted in Fig.14.
The truth table of one bit full adder is shown in table-1. The sum and carry out are determined based on
the equations (6) and (7).
Table-1: Truth table of Full adder
Input Output
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
4.1.1. Full Adder using Quantum Gates
Looking at the classical full adder, we need XOR, AND and OR gates to be implemented using quantum
gates. For this purpose, we can use fundamental quantum gates like CNOT, Y and Toffoli gates as
building blocks.
4.1.2. Implementation on IBM-Q

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Quantum circuit can be used to realize the full adder. A 2x2 CNOT gates and a 3x3 Controlled CNOT gates
are employed to implement the full adder. The quantum circuit is depicted in Fig.15. It needs ve qubits.
As sum operation is obtained by XOR operation, three 2x2 CNOT gates are used. Later for AND and OR
operations controlled CNOT gates is used as shown in Fig.15. Carry out is obtained by using Toffoli gate
with input vector Qubit4. First three qubits are preferred for inputs A, B and Cin. The outputs are measured
through classical bit lines c1 to c5 which are not bidirectional as in the case of classical computer. The
circuit often produces the output information in terms of input vectors (Q0, Q1), (Q0, Q2), (Q1, Q2) as the
control qubits.
5. 4-bit Multiplier
A multiplier is a digital circuit which has plenty of applications in many areas. In this paper, a 4x4
multiplier has been implemented with quantum gates using full adder discussed in section-4. Consider
two 4-bit numbers A and B consisting of and . The multiplication process
between two 4-bit numbers is explained in Fig.16. This multiplication results in a product term
. The partial products will be added with the help of full adders developed in the
previous section.
Figure16 clearly depicts the standard multiplication process of two 4-bit numbers A and B. While adding
the carry of the previous stage will be added with the next partial product. For this purpose, a full adder is
needed. The partial products can be simply generated by using a combinational logic circuit like AND
gates.
5.1.1 Implementation on IBM-Q
The 4x4 multiplier circuit is designed and implemented on IBM quantum computer by using gates like
CNOT gate, Toffoli gate and Y gate. CNOT gate acts as XOR gate, Toffoli gate acts as AND gate and Y
gate acts as NOT gate in the circuit. After designing the circuit, simulation is done and the output can be
observed by the probabilities obtained for respective inputs. The time taken by various multipliers
designed by Quantum-dot Cellular Automata in [20], [21] and [22] is high compared to the time taken by
the multiplication of qubits in quantum computing using IBM-Q. It shows the advantage of quantum
computing compared to the other technologies. Therefore, quantum computing is one of the fastest and
best nanotechnologies.
For instance, consider a case when the inputs are given as
A = 1001 and
B = 0101
Here A0 = 1, A1 = 0, A2 = 0, A3 = 1 and
A
3
A
2
A
1
A
0
B
3
B
2
B
1
B
0
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0

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B0 = 1, B1 = 0, B2 = 1 and B3 = 0.
The multiplication process of the above two binary numbers is done on IBM Quantum computer.
Respective probabilities are observed as shown in Fig.18.
6. Conclusion
In this paper, design of a fast and ecient multiplier using reversible logic gates in IBM quantum
computer is presented. For the design of a multiplier an ecient binary half adder and full adders are
designed for the addition process. The implementation and simulation of these designs are done on the
cloud application which is established by the IBM. The result of these designs for different inputs is
shown in the form of a graph which shows the probabilities. The outputs appear very fast compared to
the simulation outputs in any software. Finally, the result conrms that the proposed designs of adders
and multipliers reduced the complexity, ecient output without compromising with the delay.
Declarations
Conict of Interest:The authors have no conict of interest.
Ethical Approval:Not applicable
Competing interests:Not applicable
Authors' contributions:All authors contributed equally to the work.
Funding:Not applicable
Availability of data and materials: Not applicable
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Figures
Figure 1
Pauli-X gate
Figure 2
Pauli-Y gate
Figure 3
Pauli-Z gate

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Figure 4
Single Qubit representation using Bloch Sphere
Figure 5
(a) Feynman gate’s block diagram (b) Truth table (c) Symbol

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Figure 6
(a) Feynman gate for inputs 11 (b) Output probability
Figure 7

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(a) Toffoli gate’s block diagram (b) Truth table (c) Symbol
Figure 8
(a) Toffoli gate for inputs 1 1 1 (b) Output probability

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Figure 9
(a) Peres gate’s block diagram, (b) Truth table (c) Symbol

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Figure 10
Peres gate for inputs 111

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Figure 11
(a) Block diagram of Fredkin gate (b) Truth table (c) Symbol

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Figure 12
Fredkin gate for inputs 1 1 0
Figure 13
Full Adder’s block diagram

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Figure 14
Logic diagram of a Full adder
Figure 15
Probability for inputs 1 1 1

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Figure 16
Block diagram of 4-bit multiplier

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Figure 17
Quantum circuit for 4x4 multiplication

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Figure 18
Probabilities of 1001 and 0101