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Improving wafer map classification in Industry 4.0
... The adaptation of these tools in many systems' processes, including installed robotic manipulators, and the direction for more flexible and easily expandable manufacturing systems increase the need for smarter and more efficient control systems. One of the manufacturing sectors into which these tools are introduced at many different stages of the manufacturing process is the semiconductor manufacturing industry [1]. ...
... (i) 1 R to transfer products from in L to 1 In the following subsections, the physical entities ...
... (i) 1 R to transfer products from in L to 1 In the following subsections, the physical entities ...
The current trend in the wafer production industry is to expand the production chain with more production stations, more buffers, and robots. The goal of the present paper is to develop a distributed control architecture to face this challenge by controlling wafer industrial units in a general production chain, with a parametric number of production stations, one robot per two stations where each robot serves its two adjacent production stations, and one additional robot serving a parametric number of stations. The control architecture is analyzed for individual control units, one per robot, monitoring appropriate event signals from the control units of the adjacent robots. Each control unit is further analyzed to individual supervisors. In the present paper, a modular parametric discrete event model with respect to the number of production stations, the number of buffers, and the number of robotic manipulators is developed. A set of specifications for the total system is proposed in the form of rules. The specifications are translated and decomposed to a set of local regular languages for each robotic manipulator. The distributed supervisory control architecture is developed based on the local regular languages, where a set of local supervisors are designed for each robotic manipulator. The desired performance of the total manufacturing system, the realizability, and the nonblocking property of the proposed architecture is guaranteed. Finally, implementation issues are tackled, and the complexity of the distributed architecture is determined in a parametric formula. Overall, the contribution of the present paper is the development of a parametric model of the wafer manufacturing systems and the development of a parametric distributed supervisory control architecture. The present results provide a ready-to-hand solution for the continuously expanding wafer production industry.
... Therefore, there remains significant potential for development in these areas, particularly in SDG 9 (promoting innovation and sustainable industrialization). These research topics include applications in the Fourth Industrial Revolution (Industry 4.0) [59,60], and machine learning for diagnosis in manufacturing systems [61,62], all of which reflect the pursuit of more efficient, environmentally friendly, and sustainable manufacturing processes. ...
Semiconductor development is a major driving force for global economic growth. However, synchronizing it with the Sustainable Development Goals (SDGs) set by the United Nations remains a critical challenge. To gain insight into this, we analyzed SDG-related publications on semiconductors from 2017 to 2022 using the SciVal database. The study found 77,706 documents related to SDGs in the field of semiconductor research, with an overall increase in the number of publications each year. The main focus of these publications was SDG 7 (Affordable and Clean Energy), accounting for 68.9 % of the total publication count. Additionally, the results indicate that semiconductors have multifaceted potential in advancing a range of SDGs. From fostering innovations in healthcare (SDG 3), ensuring clean water access (SDG 6), catalyzing transformative industrial growth (SDG 9), to contributing to climate mitigation strategies (SDG 13), semiconductors emerge as versatile drivers of sustainable development. The respective publication percentages for these goals were 7.3 %, 5.9 %, 9.7 %, and 4.4 %, underscoring their capacity to make substantial contributions across various facets of sustainability. It's worth noting that only 2.9 % of these publications stem from academia-industry collaborations. This indicates a pressing need to facilitate collaboration between academia and industry, as such partnerships have the potential to amplify the impact of semiconductor innovations on the SDGs. The novelty of this study lies in its specific exploration through a comprehensive analysis spanning five years, revealing the alignment between semiconductor advancements and the latest SDGs. It uncovers the significance of collaborative ecosystems involving research institutions, businesses, and governments. Through these results, our study addresses a gap in the existing literature and advances semiconductor contributions to the SDGs.
The supply of defect-free, high-quality products is an important success factor for the long-term competitiveness of manufacturing companies. Despite the increasing challenges of rising product variety and complexity and the necessity of economic manufacturing, a comprehensive and reliable quality inspection is often indispensable. In consequence, high inspection volumes turn inspection processes into manufacturing bottlenecks.
In this contribution, we investigate a new integrated solution of predictive model-based quality inspection in industrial manufacturing by utilizing Machine Learning techniques and Edge Cloud Computing technology. In contrast to state-of-the-art contributions, we propose a holistic approach comprising the target-oriented data acquisition and processing, modelling and model deployment as well as the technological implementation in the existing IT plant infrastructure. A real industrial use case in SMT manufacturing is presented to underline the procedure and benefits of the proposed method. The results show that by employing the proposed method, inspection volumes can be reduced significantly and thus economic advantages can be generated.
Semiconductor manufacturing is a highly complex and competitive branch of industry, comprising hundreds of process steps, which do not allow any deviations from the specification. Depending on the application area of the products, the production chain is subject to strict quality requirements. While heading towards industry 4.0, automation of production workflows is required and hence, even more effort must be spent on controlling the processes accordingly. The need for data-driven indicators supporting human experts via monitoring the production process is inevitable, but lacks adequate solutions exploiting both, profound academic methodologies and
domain-specific know-how.
In many cases, process deviations cannot be detected automatically during the semiconductor frontend production. Hence, the wafer test stage at the end of frontend manufacturing plays a key role to determine whether preceding process steps were executed with the necessary precision. The analysis of these wafer test data is challenging, since process deviations can only be detected by investigating spatial dependencies (patterns) over the wafer. Such patterns become visible, if devices on the wafer violate specification limits of the product. In this work, we go one step further and investigate the automated detection of process patterns in data from analog wafer test parameters, i.e. the electrical measurements, instead of pass/fail classifications, which brings the benefit that deviations can be recognized before they result in yield loss - this aspect is a clear difference to state-of-the-art research, where merely specification violations are observed. For this purpose, an indicator for the level of concern associated with process patterns on the wafer, a so-called Health Factor for Process Patterns, is presented. The indicator combines machine learning techniques and expert knowledge.
In order to develop such a Health Factor, the problem is divided into three major components, which are investigated separately: ecognition of the pattern type, quantification of the intensity of a pattern and specification of the criticality associated with each pattern type. Since the first two components are intrinsically present in the wafer test data, machine learning systems are deployed for both, while criticality is specified by introducing expert and domain knowledge to
the concept. The proposed decision support system is semi-automated and thus, unifies pattern recognition and expert knowledge in a promising way.
The effectiveness of the proposed Health Factor is underlined by experiments conducted on simulated as well as real-world datasets. The evaluations show that the system is not only mathematically valid, but also practically applicable and fulfills the demands raised by a real-world production environment. Moreover, the indicator can be transferred to various product types or even related problem setups given a reliable training dataset.
Image restoration and denoising is an essential preprocessing step for almost every subsequent task in computer vision. Markov Random Fields offer a well-founded, sophisticated approach for this purpose, but unfortunately the associated computation procedures are not sufficiently fast, due to a high-dimensional optimization problem. While the increase of computing power could not solve this runtime issue appropriately, we address it in a mathematical way: we suggest an analytical solution for the optimum of the inference problem, which provides desirable mathematical properties. In practice, our new method accelerates the runtime via reducing the computational complexity of the image restoration task by orders of magnitude, independent from the smoothing intensity. As a result, Markov Random Fields can be considered for modern big data problems in computer vision, especially if numerous images with equal sizes are processed.
Smart manufacturing is reshaping the manufacturing industry by boosting the integration of information and communication technologies and manufacturing process. As a result, manufacturing companies generate large volumes of machine data which can be potentially used to make data-driven operational decisions using informative computerized algorithms. In the manufacturing domain, it is well-known that the productivity of a production line is constrained by throughput bottlenecks. The operational dynamics of the production system causes the bottlenecks to shift among the production resources between the production runs. Therefore, prediction of the throughput bottlenecks of future production runs allows the production and maintenance engineers to proactively plan for resources to effectively manage the bottlenecks and achieve higher throughput. This paper proposes an active period based data-driven algorithm to predict throughput bottlenecks in the production system for the future production run from the large sets of machine data. To facilitate the prediction, we employ an auto-regressive integrated moving average (ARIMA) method to predict the active periods of the machine. The novelty of the work is the integration of ARIMA methodology with the data-driven active period technique to develop a bottleneck prediction algorithm. The proposed prediction algorithm is tested on real-world production data from an automotive production line. The bottleneck prediction algorithm is evaluated by treating it as a binary classifier problem and adapted the appropriate evaluation metrics. Furthermore, an attempt is made to determine the amount of past data needed for better forecasting the active periods.
Cloud-aided robots are increasingly adopted in realizing Cyber-Physical-Social System (CPSS) to reduce human efforts and enhance the system performance with diverse robotic applications. However, the multi-hop distance from robot to cloud data centre elevates the data transfer delay that often inhibits the deadline-satisfied task execution of robotic applications. Thanks to edge computing, this issue can be well addressed by harnessing computing resources in proximity of data sources. As edge resources are constrained in energy and processing capacity, sharing resources among the tasks of multiple robotic applications is critical to ensure. Therefore, in this paper, we develop a congestion game-theoretic robotic edge resource allocation mechanism for CPSS, which not only maintains the Quality-of-Service (QoS) by meeting task completion deadlines but also satisfies the energy constraints of resources. Here, Agriculture 4.0 is considered as a use case for the proposed mechanism which can be extended for other domains. Nevertheless, the performance evaluation of proposed mechanism is conducted in an
iFogSim
simulated edge computing environment. In comparison with existing greedy, heuristic, and evolutionary benchmarks, our mechanism is proven to offer overall 20% improvement in deadline satisfaction, energy consumption, and resource utilization.
Cyber-physical systems (CPS) and Internet-of-Things (IoT) devices are increasingly being deployed across multiple functionalities, ranging from healthcare devices and wearables to critical infrastructures, e.g., nuclear power plants, autonomous vehicles, smart cities, and smart homes. These devices are inherently not secure across their comprehensive software, hardware, and network stacks, thus presenting a large attack surface that can be exploited by hackers. In this article, we present an innovative technique for detecting
unknown
system vulnerabilities, managing these vulnerabilities, and improving incident response when such vulnerabilities are exploited. The novelty of this approach lies in extracting intelligence from known real-world CPS/IoT attacks, representing them in the form of regular expressions, and employing machine learning (ML) techniques on this ensemble of regular expressions to generate new attack vectors and security vulnerabilities. Our results show that 10 new attack vectors and 122 new vulnerability exploits can be successfully generated that have the potential to exploit a CPS or an IoT ecosystem. The ML methodology achieves an accuracy of 97.4 percent and enables us to predict these attacks efficiently with an 87.2 percent reduction in the search space. We demonstrate the application of our method to the hacking of the in-vehicle network of a connected car. To defend against the known attacks and possible novel exploits, we discuss a defense-in-depth mechanism for various classes of attacks and the classification of data targeted by such attacks. This defense mechanism optimizes the cost of security measures based on the sensitivity of the protected resource, thus incentivizing its adoption in real-world CPS/IoT by cybersecurity practitioners.
Defect pattern recognition (DPR) of wafer maps is critical for determining the root cause of production defects, which can provide insights for the yield improvement in wafer foundries. During wafer fabrication, several types of defects can be coupled together in a piece of wafer, it is called mixed-type defects DPR. To detect mixed-type defects is much more complicated because the combination of defects may vary a lot, from the type of defects, position, angle, number of defects, etc. Deep learning methods have been a good choice for complex pattern recognition problems. In this paper, we propose a deformable convolutional network (DC-Net) for mixed-type DPR (MDPR) in which several types of defects are coupled together in a piece of wafer. A deformable convolutional unit is designed to selectively sample from mixed defects, then extract high-quality features from wafer maps. A multi-label output layer is improved with a one-hot encoding mechanism, which decomposes extract mixed features into each basic single defect. The experiment results indicate that the proposed DC-Net model outperforms conventional models and other deep learning models. Further results of the interpretable analysis reveal that the proposed DC-Net can accurately pinpoint the defects areas of wafer maps with noise points, which is beneficial for mixed-type DPR problems.
In the course of the project the methods applied lead to the fact that it is required to utilize a) a service that authenticates machines reliably b) requires a firewall friendly protocol that is ISO/IEC 20922 c) that any architecture needs to be evaluated according to security and safety methods.
In semiconductor manufacturing processes, defect detection and recognition in wafer maps have received increasing attention from semiconductor industry. The various defect patterns in wafer maps provide crucial information for assisting engineers in recognizing the root causes of the fabrication problems and solving them eventually. This paper develops a manifold learning-based wafer map defect detection and recognition system. In this system, a joint local and nonlocal linear discriminant analysis (JLNDA) is proposed to discover intrinsic manifold information that provides the discriminant characteristics of the defect patterns. An unsupervised version of JLNDA (called local and nonlocal preserving projection) is further developed to provide a monitoring chart for defect detection of wafer maps. A JLNDA-based Fisher discriminant is further put forward for online defect recognition without the modeling procedure of recognizers. Comparisons with other regular methods, principal component analysis, local preserving projection, linear discriminant analysis (LDA) and local LDA, illustrate the superiority of JLNDA in wafer map defect recognition. The effectiveness of the proposed system has been verified by experimental results from a real-world data set of wafer maps (WM-811K).
Guidelines for part average testing
- T Haifley
Iot automation: Arrowhead framework
- J Delsing
Simulated Analog Wafer Test Data for Pattern Recognition
- M Pleschberger
- M Scheiber
- S Schrunner
A Training Concept Based on a Digital Twin for a Wafer Transportation System
- G Schneider
- M Wendl
- S Kueck
- M Leitner