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Design of a cell library for formal high level synthesis

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Abstract

In this paper we present a complete design and implementation of a CMOS cell library which supports a formal high level synthesis framework. The library contains the logic level models and VLSI layouts of all primitive functions of the realization specification language (RSL) as well as some commonly used functions which are also built using these basic functions. Modular design methodology is employed to support the expandibility of the basic cells. Example of a formal matrix-matrix multiplier is presented to illustrate the application of the cell library
Design
of
a
Cell Library for Formal High Level Synthesis
Sadiq M. Sait, Masud-ul-Hasan and Khalid Elleithy
Abstract
In this paper we present a complete design and im-
plementation of
a
CMOS
cell library which supports
a formal high level synthesis framework. The library
contains the logic level models and VLSI layouts of
all primitive functions of the Realization Specification
Language (RSL)
[l]
as
well
as
some commonly used
functions which are also built using these basic func-
tions. Modular design methodology is employed to sup-
port the expandibility of the basic cells. Example of a
formal matrix-matrix multiplier is presented to illus-
trate the application of the cell library.
1
*
Introduction
VLSI layout. The front-end of the system under consid-
eration accepts input in ASL and produces RSL (Re-
alization specificastion Language)
as
an intermediate
form. The back-end takes RSL
as
input and produces
corresponding VLSI layout. The block diagram of a
VLSI high level synthesis system is shown in Figure
1.
It consists of two parts, the synthesis part and the
physical design part.
The role of the synthesis part
High
Level
Synthesis
Since the fabrication cost of VLSI chips is very high,
the designer is required to have high degree of confi-
dence in the correctness of a design before committing
it
to hardware. Conventional method of verifying cor-
rectness is computer simulation. Simulation may leave
many design errors undetected, since exhaustive sim-
ulation of complex circuits and systems is not feasi-
ble. It is now widely accepted that current simulation
techniques are not by themselves adequate to ensure
the correctness of complex designs. Testing is another
popular method that is used to prove the correctness
of systems for specific sets of inputs. With the current
advances in VLSI circuits, there is no testing procedure
that is capable of accomplishing an exhaustive exami-
nation of complex circuits.
To
overcome these difficul-
ties,
a
number of formal high level synthesis techniques
are now being developed, and they are likely to become
practical tools
for
detection of design errors.
A
formal high level synthesis system is
a
system
which transforms the formal specifications to imple-
mentable hardware. Here, synthesis is performed
within the framework of
a
suitable formal system, such
as
first-order logic, higher-order logic, temporal logic or
ASL (Algorithmic Specification Language), etc
[l].
In
formal high level synthesis system the design specifica-
tions
(also
called formal specifications) can be verified
for correctness by applying mathematical rules.
Any high level synthesis system has two tightly cou-
pled sub-systems, a front-end and a back-end. The
front-end accepts
a
high level input description and
produces an intermediate form.
The back-end takes
this intermediate form and produces corresponding
$.
Formal
Chips
Figure
1:
Block diagram of a VLSI synthesis system.
is to automatically translate an algorithmic specifica-
tion into an architectural specification that is realiz-
able in hardware. The physical design part translates
the hardware specification to VLSI layout. In a gen-
eral synthesis system, the front-end specifications to
the synthesis can be behavioral descriptions of digi-
tal systems in hardware description languages,
or
even
in programming languages. The synthesis system un-
der consideration uses precursive algorithms to model
the behavior to be synthesized. These algorithms can
be mathematically verified for correctness before being
subjected to the task of translation to architecture and
then to corresponding VLSI layouts. Therefore this
synthesis system is termed
as
formal synthesis sys-
tem.
The objective
of
this work is to make the build-
ing elements (cell library) required by the back-end to
generate VLSI layouts. The cell library is usually the
central part of the back-end of any cell based high level
synthesis system.
In this paper we present a cell library which con-
sists of both logic level and layout level cells used
to
support formal
high
level synthesis of digital sys-
tems modeled
as
precursive algorithms. In the next
0-7803-1772-6/94/$3.00
@
1994
IEEE
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section the algorithmic specification language (ASL) is
introduced which is used in the formal synthesis sys-
tem under consideration. In Section
3
the description
of the
matrix-matrix multiplier
is presented
as
an ex-
ample of precursion modeling. Section
4
introduces
the design of the cell library. The design of
a
matriz-
matrix multiplier
in VLSI is used
as
an example to il-
lustrate modeling in ASL,
RSL
(hardware) constructs,
and application of the cell library.
2
Language
ASL
A
formal behavioral framework for synthesis is intro-
duced in
[2].
The given algorithm is represented using
a newly developed language, termed Algorithm Specifi-
cation Language (ASL). ASL consists of a limited num-
ber of constructs and is capable of representing any al-
goritlnn using these curistructs. It has only three initiai
functions i.e., Zero, Projection and Successor functions,
and three operations i.e., Composition, Recursion and
p-Recursion
[
11.
These three initial functions and three operations of
ASL
can be applied in a certain sequence to obtain
any computable function. Although this language of
specification is complete it may be tedious to model
a large digital system. A library of basic functions is
defined starting from the initial functions to be used in
the definition of larger functions
[l].
This approach is
useful in building
a
cell library to support VLSI synthe-
sis. All basic functions that have been designed using
the proposed approach can be used for specifying other
functions. This technique supports a hierarchical de-
sign methodology in the sense that the specification
can be stopped at any level
as
long
as
the lower levels
are previously defined.
3
A
Design Example: Matrix-
Matrix Multiplier
An example of a formal
matrix-matrix multiplier
cell is
introduced in this section,
as
an application of ASL lan-
guage
[l].
It
is implemented by applying recursion con-
struct on
inner-product
units. The architecture accepts
two matrices
as
input, and produces
a
third matrix
as
an output. The multiplication is done in
a
recursive
way, and can be described by the following high level
subroutine:
Suppose A and
B
are the two input matrices and
C
is
the output matrix.
matrix-multiplication
(A,
B,
C)
begin
for
i
=
1
to
n
for
j
=
1
to
n
begin
Ci,j,o
=
0
for
k
=
1
to
n
next
k
c..
r,j,k
-
-c..
r,j,k-l
-I-
Ai,k
*
Bkj
end
next
j
next
i
end
3.1
ASL
and RSL Representation
The ASL description of
matrix-matrix multiplier
using
recursion is
as
follows:
..................
Cn,n(An,k, Br,n,
K
-
1))
The RSL representation of
matrix-matrix multiplier
is
as
follows:
..................
I
=
py+lsuc(I)
Ready
=
eq?(Z,
m)
Result1
=
comp(W,
I,
p$+'Result#inner-produd)
Result,
=
comp(W,
I,
pF;yl
Result#inner-product)
Figure
2
shows the
RSL
architecture obtained for
matrix multiplication. The architecture consists of
n2
inner-product cells.
1239
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Unit
counter
I
No.
of
Devices
I
Area
(Az)
1
Other Units Used
1]
-0
M
lu
U
PI
4
Table
1:
Number
of
devices and layout area of 8-bit units.
......
m
......
&#i&p&
U
I
IIUUL.II
I
......
Figure
2:
Implementation of
matriz-matriz multiplier.
~i~~~~
5:
~~g~
level model
of
mat*-math
Figure
3:
Successor function.
Figure
6:
VLSI layout of an 8-bit
maths-math mul-
tiplier.
Figure
4:
VLSI layout
of
4-bit
Successor.
1240
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4
The Cell Library Design
In this section. we present the approach used for de-
signing and implemeiitirig the formal cell library which
consists of logic level models
of
basic units and their
corresponding CMOS VLSI layouts. Corresponding
to
each construct in
ASL
is
a construct in
RSL
that maps
the
constructs
to
hardware ql!ivaient
inod!ilrLe
The
RSL
specification
of
basic
functions
is
modeled
as
a
logic netlist and simulated using
a
simulator
[5].
This simulation verify the correctness of translation.
Layouts of these functions are then synthesized
[3].
The
circuit is extracted from the layout and simulated to
verify the functional correctness of layouts.
The layouts of larger functions can be synthesized
by instantiating layouts of primitives and predehed
macros The synthesized logic anti
ita
corresponding
la>ottt
arc’
stort-ci
in
;he
library
fir
iiiter
WP
In
tiic
de-
sign
of
both logic level and layouts
of
cells, care
is
taken
to achieve modularity
so
that basic cells can be easily
expanded
to
large word lengths and can be connected
to build
cells
of larger functions. The VLSI layouta of
cells are implemented using 2-phase dynamic
CMOS
logic.
4.1
The
Successor
Unit
In this section, we show the design of the successor unit
aq
a
case study of the methodology. One of the regis-
ters
is
for the argument
n
and the other for the value
1.
The operation is done in one clock cycle. An input
signal
control
is used to determine the starting of the
*Jperatiuii.
This
uiiil
t
411
r~J*II)
ibc
UAC~
its
hi1
up-.
t-,xt-:
by
feeding
back
the output
ctf
ttic
siixcssor
functicn
to
one
of
its two inputs.
Load/Count
control inputs are
available
to
accomplish the necessary function. Two-
phase clocking scheme is used in the design of all the
cells, input is loaded during
41
and the output is ob-
tained during
42.
The cascading of successor units can
be done
by
connecting the
andout
output of a unit
to
the
widlrr
III~UL
of
the
adjacmi
III~IT
iiw
1
I,Si
laymi
uf
4-ht
SIICC~L.~DP
IS
shwi
in
Figure
4
4.2
The
Matrix-Matrix Multiplier
1x1
ihis
section, we illustrate using the cell library
to
design the
matrix-matrix multiplier.
It consists of one
5
Conclusions
In this paper, we have presented a complete design of
a
cell library that supports the formal high level synthe-
sb
framework
based
on
(RSL)
realization specification
Imguage. The cell library is the heart of the back-
eud unit of a formal methodology for VLSI systems
dwigr,
T!it.
wn)
project
io:i
stirrr~scr rnmposition,
rq:urs!on
arid
p-~~~iizai
,ii f
a119
iil
R,.!.
h.I\t-
I
<’VI
ilpplemented using
a
SCMOS technology.
CO~~~OIIC~~T-
in the RSL formal cell library are described
at
the
log-
id level and layout level. The correctness
of
the
corn-
Nnents have been exhaustively versed through the
YL simulator. All the cells are made modular
BO
that
t4e design is capable of extending
to
any
desired
word
1Qngth. These modules
are
also
used
to
made the larger
functions
A
formal matrix-matrix multiplier circuit of
hais
bfiw
tbsigned
us~ng
thr
sup
pbrt
of
the cell library.
Table
1
shows the number of devices arid layout
area
of
these units
for
an 8-bit data bus.
It
can be observed
tbat
the area
is
high
as
compared
to
the that made by
mn-formal methods. It
is
the price paid for the func-
tionally correct hardware made by formal techniques.
Acknow
iecigemtzr&
The authors would like to thank the King Fahd Uni-
vtrsity of Petroleum and Minerals
for
support.
References
[l]
K!ldiil
hl.
F,lkl!
fly.
:I
F2r~r9r.i:
!7,77nr&<*,,h:
TOT
H7yh
Level Synlhesrs
of
Digital
Designs.
PhD
Liicsis.
1
i:i
Center for Advanced Computer Studies, University
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A.
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I?
ftormnl
ilppp~ch.
Pmrredings-IEEE
idcrniitioxcl
h~njwshnt
on
Ci.rctit:
:ind
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[3]
MCNC’s
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main biilldliig
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r
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;nncr-pr.darl
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roinpotlcirth
id
mid
~Y(J
TI.?
<lJi
aud
the
pr(
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,ts
are
used
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tile
re(
iirsion
conbtruc~
to
build
:hi
Inner-product
unit The logic model
of
mairaL-
ni~frix
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1993,
ure
5
141.
The Figure
7
shows the VLSI layout ofa
matrix-matrix multiplier
[5]
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Reference
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NW
Labo-
rifmy
ftli
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(i%T
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Conference Paper
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A formal behavioral synthesis framework is introduced for specification, simulation, and synthesis of digital signal processing (DSP) algorithms. The given algorithm is represented using a newly developed language called the algorithm specification language (ASL). The components and connectivity of the synthesized architecture can be represented in three different forms: a language called the realization specification language (RSL), schematic captures, and PROLOG. PROLOG is used as a user interface language between the user subsystem and the synthesis subsystem. Algorithms of linear time complexity are introduced for transferring between different representations
Article
Thesis (Ph. D.)--University of Southwestern Louisiana. 1990. Includes bibliographical references (leaves 130-139). Vita. Photocopy. s
Open Archi-tecture Silicon Implementation Soflwan, release 2.0 edition :jl : , : Dhahran, 1993, [5] VLSZ Design Tools Reference Manual. NW Labo-rifmy ftli Tnt: grsitrd Systems r e l a x 3 1 rdition, !<’ -.;dT- (i%T Authorized licensed use limited to: University of Bridgeport
  • Mcnc Center
MCNC’s Center for Microelectronics. Open Archi-tecture Silicon Implementation Soflwan, release 2.0 edition, December 1992. :jl : , : Dhahran, 1993, [5] VLSZ Design Tools Reference Manual. NW Labo-rifmy ftli Tnt: grsitrd Systems r e l a x 3 1 rdition, !<’ -.;dT- (i%T Authorized licensed use limited to: University of Bridgeport. Downloaded on February 24,2010 at 13:32:03 EST from IEEE Xplore. Restrictions apply.