RAM-Based PUFs: Comparing Static-and Dynamic Random Access Memory

Abstract

Integrity, reliability and trustworthiness have always been the basic requirements for secure systems, including doubtlessly authenticated participants. This is increasingly relevant as systems become distributed and even more challenging as devices involved become low-resource Industrial Internet of Thing (IIoT) devices. Nevertheless, more efficient and secure techniques are required to ensure confidentiality and privacy. A promising solution is offered by Physical Layer Security (PhySec), in particular by Physically Unclonable Functions (PUFs). Their functional principle: the exploitation of the unique characteristics of semiconductors is inherent in both Static Random Access Memorys (SRAMs) and Dynamic Random Access Memorys (DRAMs). The paper discusses the properties of both types and compares them in terms of suitability for security-related applications.

Full text

RAM-Based PUFs: Comparing Static- and Dynamic
Random Access Memory
Pascal Ahr†, Marjan Noushinfar†, Christoph Lipps†∗
†Intelligent Networks Research Group, German Research Center for Artificial Intelligence
D-67663 Kaiserslautern, Email: {firstname.lastname}@dfki.de
∗Institute for Wireless Communication and Navigation, University of Kaiserslautern
D-67663 Kaiserslautern, mail: {lastname}@eit.uni-kl.de
Abstract—Integrity, reliability and trustworthiness have al-
ways been the basic requirements for secure systems, including
doubtlessly authenticated participants. This is increasingly rele-
vant as systems become distributed and even more challenging
as devices involved become low-resource Industrial Internet of
Thing (IIoT) devices. Nevertheless, more efficient and secure
techniques are required to ensure confidentiality and privacy. A
promising solution is offered by Physical Layer Security (PhySec),
in particular by Physically Unclonable Functions (PUFs). Their
functional principle: the exploitation of the unique characteristics
of semiconductors is inherent in both Static Random Access
Memorys (SRAMs) and Dynamic Random Access Memorys
(DRAMs). The paper discusses the properties of both types
and compares them in terms of suitability for security-related
applications.
Index Terms—Physical Layer Security (PhySec); Physically
Unclonable Functions (PUFs); Static Random Access Memory
(SRAM); Dynamic Random Access Memory (DRAM)
I. HAR DWARE-BA SE D SECURITY AND ITS APP LICATI ON
Driven by the evolution of the Sixth Generation (6G)
Wireless Systems, Industrial Internet of Thing (IIoT) and edge
computing, the number of low complexity terminals increases.
One example of such terminal is a small environmental sensor
placed in a fabric that is driven by little solar cells and
is connected to the Internet. Thus they can communicate
their measurements to a corresponding client which can use
these information for further processing like controlling the
temperature. Those systems handle with sensible data, that
has to be protected. The low complexity terminals are often
driven by small energy sources and are therefore energy,
computing as well as cost constrained [1]. Thus they would
not be sufficient enough to perform complex security mech-
anisms like asymmetric cryptography, for instance Rivest-
Shamir-Adleman (RSA) algorithm. In addition side attacks for
example to the Non-Volatile Memory (NVM), which are used
to store the key, make the systems more vulnerable. Therefore
it is necessary to use new security mechanisms which suits
more to new technologies´requirements.
Information theoretic methods which can provide authen-
ticity, confidentiality and integrity in a more efficient way
could be used as a solution. The information theoretic methods
benefit the unique features of the medium under use, like
Integrated Circuits (ICs) or wireless channel. Furthermore
there are no assumptions made on the computing power, unlike
cryptographic primitives [1]. Physical Layer Security (PhySec)
as one of these methods provides security in physical layer by
using the intrinsic properties.
A promising approach of PhySec is the Physically Un-
clonable Functions (PUFs) which are defined by Basel Halak
as a: “[...] physical entity whose behaviour is a function of
its structure and the intrinsic variation of its manufacturing
process“ [2]. One prominent type of PUFs is the Random-
Access Memory (RAM)-based PUF since the RAM is already
integrated in most computing devices. One major advantage is
that instead of storing the secret in some digital memories, the
secrets are derived from physical characteristics of the ICs.
Even though the ICs are manufactured in the exactly same
way, they have some slight differences due to production
circumstances and therefore no two ICs would be identical
[3]. RAM-based PUFs take advantage of these fluctuations to
derive a unique pattern. Due to the physical disorder, these
fluctuations are highly random [2]. In comparison to classical
pseudo random number generators that based on deterministic
algorithms, the PUFs provides a true randomness.
Thus it can be concluded that, RAM-based PUFs do not re-
quire expensive hardware like NVM or complex computations
of cryptographic algorithms [4]. Taking into account the above
mentioned advantages, PUFs could be efficient. Considering
the importance of PUFs and also the fact that there are many
different types of them, next section introduces some of the
categories and well-known PUFs. The two most common used
RAMs in computing systems are the Static- and Dynamic
Random-Access Memory. In some devices both are present
and can be used to build a PUF. They has different properties
and advantages for specific applications. Therefor, there is a
choice which one to use. The focus of this work is on the
comparison of the SRAM and DRAM PUFs to provide a base
for this decision.
This paper is structured as follows: Section II gives an
introduction to the subject area PUFs and describes different
PUF derivatives. Section III, though, specifically explains
SRAM and Section IV DRAM PUFs, their architecture and
functionality. A detailed comparison of both RAM types is
given in Section V, before summarizing the work in Section
VI and providing an outlook for further work.

II. TH E PUF ZO O: ANOVE RVIEW
According to Suh and Devadas a ”Physical Random Func-
tion (PRF) or Physically Unclonable Function is a function
that maps a set of challenges to a set of responses based on
an intractably complex physical system” [5]. This function is
unique for each physical instance. There are different catego-
rizations of electrical PUFs according to different concepts,
which can be divided into two areas:
i) Memory-based:
Flip-Flop PUF [6],
Butterfly PUF [6] and
SRAM PUF [7].
ii) Timing-based:
Arbiter PUF [2],
Ring-Oscillator (RO) PUF [2] and
Self-timed Ring PUF [2].
The enumeration above lists examples for those categories but
there are way more researched.
The channel-PUF as another category, uses specific char-
acteristics of the wireless communication channel to derive
unique patterns from it. Those characteristics are unique for
each communication pair (Sender/Receiver) and can not be
measured by a third party, that are further away than half of
the channel wavelength λ
2[8].
PUFs could also be categorized based on the source of
randomness, into PUFs using explicitly-introduced random-
ness, PUFs using intrinsic randomness and PUFs with easier
to control uniqueness, including optical and such as coating
PUFs. There are also more popular PUFs with no modification
to the original design namely: delay PUF (ring oscillator,
arbiter PUF, etc.), memory PUF (SRAM, DRAM, FF PUF,
etc.), mixed signal PUF (Analog PUF) and miscellaneous ones
(Bi-stable ring, magnetic stripe card, quantum confinement
PUF, etc.). PUFs are also classified as weak or strong, based
on size of the Challenge Response Pairs (CRPs) [9].
Low-cost authentication and secure key generation as two
main applications of PUFs are applicable by using PUFs from
two main types: strong PUFs and weak PUFs, respectively. A
black-box challenge-response model can be used to illustrate
the PUF. According to Herder, a challenge cpasses through
the PUF as the input and a response rwill be returned such
that r=f(c). Since the internal parameter of this function
is hidden from the user, then the black box model is suitable
to explain its behaviour. From this point of view, the PUF
security depends on two factors:
i) estimating these parameters, and
ii) having two chips with exactly same parameters.
It can be observed that, PUFs are grouped into strong and weak
based on the number of unique challenges cprocessed by the
PUF. While a weak PUF can only process a few challenges
(in extreme cases only one challenge), a strong PUF is able
to deliver many challenges [3].
III. STATIC RAM-BA SE D PUFS
A SRAM PUF, is based on the start-up state of completely
discharged six-transistor cells and is produced in Complemen-
Fig. 1: six transistor SRAM Cell
tary Metal-Oxide-Semiconductors (CMOS) technology. Figure
1 illustrates the architecture of such a cell. Transistors which
form two cross-coupled inverters which can store one of the
stable states (one or zero). This architecture is a bi-stable
system because it must always contain one out of the two
states. This behaviour results out of the regenerative property
which is illustrated in Figure 2. The voltage of the inverted
SRAM output and voltage of the non-inverted output are
placed at the x and y axis, respectively. The two transfer curves
of the coupled inverters has got an intersection point Vinversion
and split the system in two regions [7].
In case there is an input in one of the regions, this input will
be regenerated to one of the two states. The states correspond
to the stored value either value one or value zero. Therefore
those regions are called regenerative one and regenerative zero
areas. To store a specific value in the SRAM, it is necessary
to put its corresponding value from the zero or one area,
which is higher or lower than the one of the intersection point
Vinversion , at the input [7].
By powering the SRAM on, both inverters try to load their
outputs and influences the other one due to the cross coupling.
As soon as one inverter reaches as its output point Vinversion,
it dominates the the cell and defines the state to be adopted. If
the two inverters are manufactured exactly the same, then the
regenerative areas are equally sized and the point Vinversion is
placed on the bisecting angle. The result is, that the cell obtain
both states with the same probability and the adopted value by
SRAM changes by every start-up. This adopted value is also
called start-up value. The mentioned behaviour is represented
in the middle of Figure 2 [7].
Due to manufacturing fluctuations, these two inverters are
not exactly the same and Vinversion point shifts away from
bisecting angle. The more the inverters differ from each other,
the more distance Vinversion gets from the bisecting angle.
The main manufacturing related parameters that leads to this
behaviour are:
i) channel length,
ii) channel width,

Fig. 2: SRAM Cell Behaviours [7]
iii) oxide-layer thickness and
iv) dotation.
These fluctuations are technical and physical related and
highly random as well as specific for each SRAM transistor.
This leads to a unique behaviour for each SRAM cell. Accord-
ingly, there are three possible behaviours that are illustrated
in figure 2:
i) if Vinversion is shifted to the left-hand side, then the Start-
up value is zero with the highest probability,
ii) if Vinver sion is shifted to the right-hand side, then the
start-up value is one with the highest probability and
iii) if Vinversion is on the bisecting angle, then both Start-up
values are equally probable.
Through the SRAM manufacturing, the goal is to manufacture
the inverters identically and with the least possible mismatch.
Therefore the differences among two transfer curves are very
insignificant and Vinversion is very close to the bisecting angle.
Due to noises, it is also possible that a non-prioritized start-up
value to be adopted. The more similar the two inverters are,
the more probable is this behaviour and the more important
will be the noises [7]. In order to use the mentioned behaviour
of the SRAM to create a PUF following steps should be taken:
i) shut down the SRAM,
ii) wait until SRAM is completely discharged,
iii) power the SRAM on and
iv) read the start-up value by a simple read operation.
A function needs to produce always the same output for the
same input. Since there are cells that change their start-up
values after each power up, some suitable mechanisms are
required to deal with these errors. Therefore the challenge
response pairs are the chosen address and its appropriate start-
up value [7].
IV. DYNA MI C RAM-BAS ED PUFS
DRAM is a volatile Memory consisting out of one transistor
and one capacitor (1T1C). This structure is area efficient but
has got the drawback of being not static. The storage capacitor
(CS) stores the content regarding to a logical 0 or logical 1. To
choose specific cells of the DRAM the capacitor is connected
to the bitline (BL) by a metal–oxide–semiconductor field-
effect transistor (MOSFET) (M1), that connect or disconnect
it. The gate of the MOSFET is connected to the wordline
(WL). The schematic of a DRAM cell is shown in figure 3.
Due to the dimensions of the BL, a capacitance is build up,
called bitline capacitance (CBL ) that is much bigger then the
CS. According to Qtotal = (CS+CBL )·Vr=QS+QBL, the
ratio CS<< CBL effects an exchange of just a very small
amount of load carries, between the two capacitances [10].
This leads to a very small change of the bitline voltage (VBL)
to the resulting voltage (Vr).
To detect this small voltage change a sense amplifier
(SensAmp) is needed, that amplifies the voltage Vrto the
two maxima ground (GND) or supply voltage (VDD). This
SensAmp is similar to a SRAM cell and due to the pre-
charging of the BL to its exact inversion point (Vinversion ),
very sensitive to the small voltage change. Therefore the read-
out procedure of CSleads to the entering in the according
regenerative areas for a logical 0 or logical 1, regarding Section
III. Additionally to minimize the stress from the electrical field
one plate of the capacitor is biased to VDD /2[11]. The DRAM
is called dynamic, because the cell looses their stored data
during a read-out and after some time and needs a periodical
refresh, typically every 64ms. This is caused by leakage effects
of the storage capacitor (CS) and the not ideal MOSFET [12].
Similar to the SRAM, the manufacturing process leads to fluc-
tuations of the semiconductors and capacitences parameters
[2]. There are four types of DRAM-PUFs known [13]:
i) Retention Error,
ii) Row Hammer,
iii) Startup, and
iv) Latency.
Those types differ in terms of how the PUF is generated as
well as in their provided quality.
A. Retention Error
The Retention Error PUF (RE-PUF) is the first one based
on DRAMs and published in 2012 [13]. It uses the property
of the leakage of the DRAM cells and their production related
variations. Generating the PUF takes place in 4 steps:
i) deactivate the refresh mechanism of the DRAM,
ii) load the storage capacitor (CS) to VDD by writing,
iii) wait a predefined time, and
iv) read-out the stored values.
If CSis decayed in the predefined time that much that it
is, during the read-out, not able to load the bitline voltage
(VBL ) higher than the threshold voltage of the SensAmp,
it is interpreted as a logical 0, otherwise as a logical 1.
This is called a bit-flip and influenced by production related
variations, that causes slightly differences in the decay process
for every DRAM cell. Those variations are individual for
each cell and represent the PUF response. The bit-flips of the
RE-PUF are relatively rare and take a long time [14].
B. Row Hammer
An evolution of the RE-PUF is the so called Row Hammer
PUF (RH-PUF). To increase and accelerate the amount bit-
flips the Row Hammer takes place. There are PUF Rows, that
are read out and represent the PUF response, and Hammer
Rows as adjacent ones. In this procedure a quick repeated
read-out happen on the Hammer Rows.

Fig. 3: DRAM Cell
i) deactivate the refresh mechanism of the DRAM,
ii) select which rows are the PUF and which are the Hammer
ones,
iii) load the storage capacitor (CS) to VDD by writing,
iv) perform the Row Hammer procedure, and
v) read-out the stored values.
Due to the Row Hammer procedure the leakage effect happens
faster and additionally there are cells with bit-flips that would
not do so with the classical RE-PUF [15].
C. Startup
This type is similar to the SRAM PUF by using the
generated Startup-Values during the startup process.
i) shut the DRAM down,
ii) wait a defined time until the DRAM is completely dis-
charged,
iii) start the DRAM, and
iv) read-out the stored values.
After the startup, every cell is in a undefined state and point
VCin figure 3 has got, due to the precharge of one plate of CS
to VDD /2, a potential different form GND. If a red-out takes
place to those cells, they charge VBL either over or below
the threshold of the SensAmp. According to the production
related variations of the semiconductors and capacitors, a cell
prefers a logical 1 or a logical 0 [11].
D. Latency
DRAM cells take some time to perform the read and write
operation successfully. If this time is violated the operation is
failed. This time is, due to the manufacture related variations,
individual for every cell. Recommend values by the manufac-
tures are worst case scenarios.
i) write known data normally into a DRAM memory region,
ii) read the written memory region with a predefined lower
read time, and
iii) check which bit is not read correctly.
Some cells are read out correctly while others are not. Those
not correct read cells represent the PUF [16]. This procedure
is also possible for the write operation [17].
V. COMPARING SRAM AND DRAM PUFS
As in Section III and IV the technical background and
the mechanism of the SRAM and DRAM memory PUFs are
described, this chapter compares those two PUF types and
highlights their main differences.
A. Metrics of Evaluation
Important metrics to evaluate the quality of a PUF are the
uniqueness, reliability and uniformity [2]. To calculate those,
the Hamming Distance (HD) and Hamming Weight (HW) are
used. According to Basel Halak those metrics are defined as:
i) Hamming Distance (HD) ”The Hamming Distance
d(a, b)between two words a= (ai)and b= (bi)of
length n is defined to be the number of positions where
they differ, that is, the number of (i)s such that ai6=bi”
[2].
ii) Hamming Weight (HW) ”Let 0denotes the zero vectors:
00...0, the Hamming Weight H W (a)of a word a=ai
is defined to be d(a, 0), the number of symbols ai! = 0
in a” [2].
1) Uniqueness: The uniqueness indicates how unique a
individual PUF chip is and how well it can be distinguished
from others. It is specified by the Inter Hamming Distance
(HDinter) and is calculated with Equation 1:
HDinter =
2
k·(k−1)
k−1
X
i=1
k
X
j=i+1
HD(Ri(n), Rj(n))
n×100% (1)
Whereby Ri(n)is the response of chip iand Rj(n)is the
response of chip jout of kchips with the same challenge.
With the ideal value of 50%, the response of two chips are
completely nonidentical.
2) Reliability: How well a PUF is able to generate a
consistence response for a specific challenge, is specified
by the Intra Hamming Distance (HDintra). It is calculated
according to Equation 2:
reliability = 100% −HDintra (2)
with:
HDintra =1
k
k
X
i=1
HD(Ri(n), R0
i(n))
n×100% (3)
Whereby R0
i(n)is the response of the same chip at a different
condition for the same challenge. This can also be different
time points with the best case of 100%
3) Uniformity: This metric specifies the unpredictability of
a specific PUF response and is therefore a indicator for the
randomness. An uniformity of 50% indicates a true random-
ness. Equation 4 defines the calculation:
Uniformity = 1
k
k
X
i=1
ri×100% (4)
Whereby riis the HW of the ith out of kresponses of the
same chip.

TABLE I: Comparison of the SRAM PUF and the four DRAM PUF types by its important metrics
Property SRAM DRAM
Startup [18] Retention Error [19] Row Hammer [15] Startup [11] Latency [16]
Availability nearly every Microcontroller only in bigger controller or extern
Implementable in already
existing devices yes in nearly every device yes in many devices
Existing of research a lot of not that much because it is a relatively new topic
Area consumption per bit higher (6 transistors) lower (1 transistor and 1 capacitor)
Memory cost per bit higher lower
Type of PUF electrical voltage based
memory PUF electrical current based memory PUF
CRP weak strong
Temperature dependent yes yes
Output generation time only by first power up every time every time only by first
power up every time
Time to generate PUF
sequence just time for one read-out decay time depening:
up to minutes 60s-120s just time for
one read-out 88,2ms
Reliability HDintra = 95.585% high Jintra = 94.54% HDintra<81.4% Jintra>65%
Uniqueness HDinter = 51.392%
decay time depending:
HDinter =
43.1% −79.7%
Jinter ≈0% HDinter = 49.37% Jinter<25%
Uniformity 46.772% decay time depending:
32.3% −53.7% -48% −55% -
B. Jaccard index
For DRAMs it is also common to use instead of the HD,
the Jaccard index. It specifies the ratio of the intersection
of two sets s1and s2. Therefore the closer this value is to
factor one the similar those two sets are. According to the
HDintra (chapter: V-A2) and HDinter (chapter: V-A1), there
is the Intra Jaccard index (Jintra), for two sets of the same
chip and Inter Jaccard index (Jinter) for two sets of different
chips [15]. Equation 5 provides the calculation:
J(s1, s2) = |s1∩s2|
|s1∪s2|(5)
For the Jinter the best possible value is 0% and for Jintra it is
100%.
C. The Comparison
Starting by small IIoT devices up to big super computers,
DRAM and SRAM are common and highly used memory
types in computing systems. Using those as a PUF, is therefore
easy to implement and cost efficient, even in already existing
systems. Sometimes there is, due to the presence of both, the
opportunity to choose one of them for the PUF implementa-
tion. Table I contrasts important properties of the SRAM and
the four different DRAM types. The most similar type of the
SRAM PUF is the DRAM Startup PUF. Both of them have got
the disadvantage of not being accessible at any time but just
at the fist power up. Furthermore, both are very fast, because
they just have to be red out after the startup process. Nerveless
the readout operation of a SRAM is much faster than the one
of the DRAM memory. All other DRAM based PUFs require
much more time to provide the response, up to minutes for
the Retention Error one.
All types have got a high reliability and uniqueness. For
the Row Hammer and Latency DRAM PUF no uniformity
values are given by the papers. The SRAM, DRAM Retention
Error and DRAM Startup PUF provide a high uniformity.
Furthermore the SRAM PUF is defined as a weak while the
DRAM one is defined as a strong PUF. A throwback that both
memory PUF have got is a strong temperature dependency.
VI. CONCLUSION AND OU TL OO K
To put it in a nutshell, both the SRAM and the DRAM
are suitable to be used as a PUF. Which of those types are
chosen mainly depend on two factors: i) at which time point
the response of the PUF is needed and ii) is the memory
type present in the given computing system. If the response
is needed during run-time, the DRAM PUF is the only one
that provides a type for this purpose. Is the given computing
system for example a very small IIoT device, without a DRAM
memory, the SRAM PUF is the only choice. Due to a non
perfect reliability and temperature dependency, both types have
to include a mechanism that is able to handle this behavior.
Future works should also include comparisons of SRAM
and DRAM PUFs embedded in complete PUFs algorithms
with error corrections and further applications. Additionally a
comparison with other memory and non memory PUFs can
provide a more extensive overview of possible integration
choices for specific systems.
ACKNOWLEDGMENT
This work has been supported by the Federal Ministry of
Education and Research of the Federal Republic of Germany
(F¨
orderkennzeichen 16KIS1283, AI-NET PROTECT). The
authors alone are responsible for the content of the paper.
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