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Semiconductor Science and Technology
Semicond. Sci. Technol. 37 (2022) 025007 (6pp) https://doi.org/10.1088/1361-6641/ac419e
Pre-metal dielectric PE TEOS oxide
pitting in 3D NAND: mechanism
and solutions
Peizhen Hong1, Qiang Xu2, Jingwen Hou1, Mingkai Bai1,2, Zhiguo Zhao1,2, Lei Jin1,2,3,
Zongliang Huo1,2,3,∗and Chunlong Li1,∗
1Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029,
People’s Republic of China
2University of Chinese Academy of Sciences, Beijing 100049, People’s Republic of China
3Yangtze Memory Technologies Co., Ltd, Wuhan 430205, People’s Republic of China
E-mail: huozongliang@ime.ac.cn and lichunlong@ime.ac.cn
Received 12 October 2021, revised 7 December 2021
Accepted for publication 9 December 2021
Published 21 December 2021
Abstract
In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and
the stress problem becomes more and more serious. Therefore, the low cost and low stress
plasma enhanced tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP)
oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper
explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer. In our
experiment both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase
protection. There is not any void found in the two oxide structures. However, oxide pitting is
spotted in the subsequent diluted hydrouoric acid wet etching in the PE TEOS split. Moreover,
we observe that the top silicon nitride corrodes in hot phosphoric acid. We study the mechanism
of PE TEOS oxide pitting and silicon nitride corroding, propose two solutions: (1) HDP
oxide +PE TEOS, and (2) PE TEOS +dry etching. Experimental results demonstrate that our
solutions can well address the issue of PE TEOS oxide pitting and effectively protect the
staircase structure. This work extends the application of PE TEOS oxide of which the cost and
the stress are both low in 3D NAND.
Keywords: 3D NAND, pre-metal dielectric, PE TEOS, HDP, stress
(Some gures may appear in colour only in the online journal)
1. Introduction
In order to facilitate the evolution to higher density and lower
cost of ash memory, a signicant step is underway: replace-
ment of 2D NAND with 3D NAND [1–6]. As introduced,
3D NAND raises a lot of new issues regarding their fabrica-
tion, such as the multi-layer thickness [7], staircase formation
[8,9], ultra-high aspect ratio channel hole etch [10–12], stress
[13–15], process detection [16,17]et al. In this paper, the
∗Authors to whom any correspondence should be addressed.
challenges of pre-metal dielectric (PMD) oxide in 3D NAND
are discussed.
In 3D NAND, as the stack number increases, the stack
is higher and higher. The required PMD oxide layer is
thicker and thicker accordingly. As a result, the pro-
cess cost becomes higher and higher, and the stress issue
is becoming more and more severe. Therefore, plasma
enhanced tetraethyl orthosilicate (PE TEOS) [18,19] shows
advantages over high density plasma (HDP) oxide [20],
when applied as the PMD oxide layer in 3D NAND
ash memory, as it incurs less cost and induces less
stress.
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