ArticlePublisher preview available

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

IOP Publishing
Semiconductor Science and Technology
Authors:
To read the full-text of this research, you can request a copy directly from the authors.

Abstract and Figures

In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer. In our experiment both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase protection. There is not any void found in the two oxide structures. However, oxide pitting is spotted in the subsequent diluted hydrofluoric acid wet etching in the PE TEOS split. Moreover, we observe that the top silicon nitride corrodes in hot phosphoric acid. We study the mechanism of PE TEOS oxide pitting and silicon nitride corroding, propose two solutions: (1) HDP oxide + PE TEOS, and (2) PE TEOS + dry etching. Experimental results demonstrate that our solutions can well address the issue of PE TEOS oxide pitting and effectively protect the staircase structure. This work extends the application of PE TEOS oxide of which the cost and the stress are both low in 3D NAND.
This content is subject to copyright. Terms and conditions apply.
Semiconductor Science and Technology
Semicond. Sci. Technol. 37 (2022) 025007 (6pp) https://doi.org/10.1088/1361-6641/ac419e
Pre-metal dielectric PE TEOS oxide
pitting in 3D NAND: mechanism
and solutions
Peizhen Hong1, Qiang Xu2, Jingwen Hou1, Mingkai Bai1,2, Zhiguo Zhao1,2, Lei Jin1,2,3,
Zongliang Huo1,2,3,and Chunlong Li1,
1Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029,
People’s Republic of China
2University of Chinese Academy of Sciences, Beijing 100049, People’s Republic of China
3Yangtze Memory Technologies Co., Ltd, Wuhan 430205, People’s Republic of China
E-mail: huozongliang@ime.ac.cn and lichunlong@ime.ac.cn
Received 12 October 2021, revised 7 December 2021
Accepted for publication 9 December 2021
Published 21 December 2021
Abstract
In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and
the stress problem becomes more and more serious. Therefore, the low cost and low stress
plasma enhanced tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP)
oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper
explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer. In our
experiment both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase
protection. There is not any void found in the two oxide structures. However, oxide pitting is
spotted in the subsequent diluted hydrouoric acid wet etching in the PE TEOS split. Moreover,
we observe that the top silicon nitride corrodes in hot phosphoric acid. We study the mechanism
of PE TEOS oxide pitting and silicon nitride corroding, propose two solutions: (1) HDP
oxide +PE TEOS, and (2) PE TEOS +dry etching. Experimental results demonstrate that our
solutions can well address the issue of PE TEOS oxide pitting and effectively protect the
staircase structure. This work extends the application of PE TEOS oxide of which the cost and
the stress are both low in 3D NAND.
Keywords: 3D NAND, pre-metal dielectric, PE TEOS, HDP, stress
(Some gures may appear in colour only in the online journal)
1. Introduction
In order to facilitate the evolution to higher density and lower
cost of ash memory, a signicant step is underway: replace-
ment of 2D NAND with 3D NAND [16]. As introduced,
3D NAND raises a lot of new issues regarding their fabrica-
tion, such as the multi-layer thickness [7], staircase formation
[8,9], ultra-high aspect ratio channel hole etch [1012], stress
[1315], process detection [16,17]et al. In this paper, the
Authors to whom any correspondence should be addressed.
challenges of pre-metal dielectric (PMD) oxide in 3D NAND
are discussed.
In 3D NAND, as the stack number increases, the stack
is higher and higher. The required PMD oxide layer is
thicker and thicker accordingly. As a result, the pro-
cess cost becomes higher and higher, and the stress issue
is becoming more and more severe. Therefore, plasma
enhanced tetraethyl orthosilicate (PE TEOS) [18,19] shows
advantages over high density plasma (HDP) oxide [20],
when applied as the PMD oxide layer in 3D NAND
ash memory, as it incurs less cost and induces less
stress.
1361-6641/22/025007+6$33.00 Printed in the UK 1 © 2021 IOP Publishing Ltd
ResearchGate has not been able to resolve any citations for this publication.
Article
Full-text available
Channel holes (CH) and common source line (CSL) etch are two of key process challenges in 3D NAND. With the increase of stacked layers, the aspect ratio become larger than 50:1. One of key issues is CSL tilting to CH, leading to serious word-line leakage and block fail in array. In this work, it is demonstrated that trapped charges brought by CH etch process can affect the CSL slit etch process seriously, and lead to CSL tilting issue. Charging model was used to explain the phenomenon and is validated by experiments. An approach by removing the backside films for charges release via poly-Si deposition film is proposed to solve this issue. This work provides effective approach to solve the special deep trench tilting issue in 3D NAND memory processes development.
Article
Full-text available
We propose and implement Stair Divided Scheme (SDS), a novel high density and low cost staircase scheme for 3D NAND. In SDS, the stairs are divided into m zones in Y direction, and thus only N/m stairs are needed in X direction for N control gates. We further present the photoresist (PR) consume model. The PR consume model fits the result well. Based on the PR consume model, we are able to prove the process efficiency and low cost of SDS. We also show that SDS can improve the integration for higher bit density. Finally, we find that the critical dimension (CD) of stair divided zone shifts post stair etching. We investigate the reason and point out that, it is necessary to make compensation in layout to ensure the precise alignment of stairs.
Article
We investigated the impact of etch angles on cell characteristics of 3D NAND flash memory structures. The cell characteristics were extracted from simulations with an empirical etch profile, which was analyzed through comparisons to completely vertical conditions. Here, we observed that a narrowing of the poly-silicon channel width due to etch angles increased the channel resistance, which resulted in an on-current degradation of approximately 19% for an etch angle of 89.2°. The degradation in cell characteristics also became worse as the number of word-lines changed from low to high levels. Additionally, the difference in channel hole size between upper and lower stage aggravated the cell uniformity along the channel, hence the threshold voltage distribution was broadening in the smaller etch angle. We confirmed that critical dimensions should be well-controlled to minimize the etch angles, which provide significant on-current reduction and program characteristics distortion. These results led to an appropriated standard to implement high stack 3D NAND flash memory.
Article
An in situ monitoring the plasma-enhanced chemical vapor deposition (PECVD) of dielectric materials is proposed in this paper. The in situ monitoring of plasma process has become a crucial tool for reducing wafer scrap due to processing, and the use of non-invasive monitoring methods is a key requirement in the semiconductor industry. In addition to optical emission spectroscopy, we propose an electrical measurement technique using newly designed RF signal monitoring sensors that acquire the magnitude and phase of current and voltage from both RF generators and PECVD susceptor. As a test vehicle, the use of multiple oxide/nitride layer deposition process during 3D-NAND flash device fabrication was adopted as a test approach. We assume that the chamber impedance changes during deposition cycles owing to the thickness of films deposited on the wafer and chamber wall, and that it can be observed from a difference in the RF magnitude or phase of the generator and susceptor antennas. Our preliminary finding shows that the voltage phase is correlated over repeated deposition cycles, and is related to the condition of the chamber and the deposited film thickness. The voltage is loosely correlated with the measured RF voltage factor during repeated deposition cycles, showing that our hypothesis that the chamber impedance changes during deposition is valid. This finding enables subsequent investigation of the impact of the thickness of deposited films in cyclic PECVD processes during three-dimensional NAND memory fabrication.
Article
A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested to resolve the issues. For performance enhancement, a novel program method hiding two-page data loading time is presented. This paper also discusses an electrical annealing improving reliability characteristic by removing holes in shallow traps. In addition, a valley tracking read for reducing timing overhead at a read retry is introduced by fast finding optimal read levels. Finally, a high-speed self-test mode for IO operation is presented. The chip, designed with the fourth generation of V-NAND technology, achieved an areal density of 3.98 Gb/mm 2 and operated up to 1 Gb/s at 1.2 V.
Article
Automated STEM/EDS Metrology Characterization of 3D NAND Devices - Volume 23 Issue S1 - Zhenxin Zhong, Justin Roller, Oleksii Bidiuk, Jeff Blackwood, Martin Verheijen, Ozan Ugurlu, Jason Donald