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Higher-order UWB Pulse Generator using Enhanced Amplitude Modulator

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This work presents a higher derivative Gaussian pulse generator using an enhanced amplitude modulator with a differential connected load. The aim of the design was to obtain a high amplitude Gaussian pulse with low power consumption. Our contribution in this thesis is the amplitude modulator which provided pulse shaping and resistive feedback current buffer which enhanced the output swing. This circuit configuration helped to avoid on/off-chip inductor-based filter. Hence, an area-efficient design can be proposed. Two designs were proposed the enhanced amplitude modulator. The first design is a voltage-controlled multi derivative Gaussian pulse generation that offers high coverage area adaptability. The second design is a 7th derivate Gaussian pulse generator which provides better output voltage performance compared to the previous design with a trade-off in power consumption and coverage area adaptability. Both transmitters are capable of high speed, low noise, and low power consumption compared to reported transmitters make this topology suitable for on-chip communication.
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i
Bangladesh University of Engineering and Technology
Higher-order UWB Pulse Generator
using Enhanced Amplitude Modulator
A Thesis submitted by
Md. Abeed Hasan (1506022)
Tasnim Tamanna (1506193)
Under supervision of
Dr. Apratim Roy
Associate Professor
Department of EEE,
Bangladesh University of Engineering and Technology
March 2021
ii
Table of Contents
Chapter 1: INTRODUCTION 1
1.1. Motivation ................................................................................................................... 1
1.2. Overview of On-chip Wireless Interconnects ............................................................. 2
1.3. Why Wireless Interconnect? ....................................................................................... 2
1.4. UWB Transmitter ........................................................................................................ 3
1.5. FCC Spectral Mask ..................................................................................................... 4
1.6. Thesis objectives ......................................................................................................... 5
1.7. Thesis Organization..................................................................................................... 6
Chapter 2: UWB ON-CHIP WIRELESS COMMUNICATION 7
2.1. Introduction ................................................................................................................. 7
2.2. History of UWB Pulse................................................................................................. 7
2.3. Gaussian Pulse............................................................................................................. 8
2.4. Advantages of UWB communication ......................................................................... 9
Chapter 3: DESIGN BACKGROUND OF VOLTAGE CONTROLLED MULTI
DERIVATIVE IR-UWB PULSE GENERATOR 10
Chapter 4: CMOS DESIGN OF VOLTAGE CONTROLLED MULTI DERIVATIVE IR-
UWB PULSE GENERATOR 13
4.1. Block Diagram .......................................................................................................... 13
4.2. Rectangular Pulse Generator ..................................................................................... 13
4.3. Ring Oscillator .......................................................................................................... 15
4.4. Modulating Signal Generator .................................................................................... 16
4.5. PMOS Amplitude Modulator .................................................................................... 17
4.6. Switching Current Amplifier ..................................................................................... 19
4.7. High Pass RC Filter ................................................................................................... 20
iii
Chapter 5: SIMULATION RESULTS OF VOLTAGE CONTROLLED MULTI
DERIVATIVE IR-UWB PULSE GENERATOR 21
5.1. Simulation Overview................................................................................................. 21
5.2. Limitations ................................................................................................................ 24
Chapter 6: DESIGN BACKGROUND OF 7TH DERIVATIVE GAUSSIAN PG USING
ENHANCED AMPLITUDE MODULATION 25
Chapter 7 : CMOS DESIGN OF 7TH DERIVATIVE GAUSSIAN PG USING ENHANCED
AMPLITUDE MODULATION 26
7.1. Block Diagram .......................................................................................................... 26
7.2. Voltage Controlled Inverted Delay Line ................................................................... 26
7.3. Impulse Generator ..................................................................................................... 27
7.4. Impulse Combiner ..................................................................................................... 29
7.5. Modulating Signal Generator .................................................................................... 30
7.6. PMOS Amplitude Modulator .................................................................................... 32
7.7. Switching Current Amplifier ..................................................................................... 34
7.8. RC Filter .................................................................................................................... 35
Chapter 8: SIMULATED RESULTS OF 7TH DERIVATIVE GAUSSIAN PG USING
ENHANCED AMPLITUDE MODULATION 36
8.1. Simulation Overview................................................................................................. 36
Chapter 9: CONCLUSION 39
9.1. Summary ................................................................................................................... 39
9.2. Future of Work .......................................................................................................... 40
Reference ................................................................................................................................. 41
iv
List of Illustrations
FIGURE 1: BLOCK DIAGRAM OF A TYPICAL WIRELESS INTERCONNECT ........................................ 2
FIGURE 2: FCC SPECTRAL MASK FOR UWB INDOOR COMMUNICATION SYSTEMS ..................... 5
FIGURE 3: LEFT COLUMN REPRESENT VPP VS TIME FOR 3RD ORDER TO 7TH ORDER GAUSSIAN
PULSE (ORDER INCREASES ROW-WISE) AND RIGHT COLUMN REPRESENT CORRESPONDING
PSDS FOR THE VOLTAGES IN THE LEFT COLUMN ............................................................... 10
FIGURE 4: RELATIONSHIP BETWEEN VPP AND PULSE WIDTH WITH RESPECT TO PULSE ORDER . 11
FIGURE 5: LEFT SHIFT OF CENTER FREQUENCY FROM 8 GHZ TO 5.3 GHZ FOR CHANGING THE
PULSE WIDTH OF 5TH ORDER GAUSSIAN PULSE FROM 440PS TO 610PS .............................. 11
FIGURE 6: RIGHT SHIFTING OF CENTER FREQUENCY FROM 5.3 GHZ TO 7.2 GHZ FOR CHANGING
FROM 5TH ORDER TO 7TH ORDER FOR CONSTANT PW OF 613 PS ....................................... 12
FIGURE 7: BLOCK DIAGRAM OF THE PROPOSED TRANSMITTER .................................................. 13
FIGURE 8: SCHEMATIC OF RECTANGULAR PG .......................................................................... 14
FIGURE 9: TIMING SIGNALS OF RECTANGULAR PG ................................................................... 14
FIGURE 10: TIMING SIGNALS OF HP FOR DIFFERENT VALUES OF CONTROL VOLTAGE VC ......... 15
FIGURE 11: CIRCUIT DIAGRAM OF VCO BLOCK ........................................................................ 15
FIGURE 12: TIMING SIGNALS OF A, C, AX, CX ......................................................................... 16
FIGURE 13: SCHEMATIC OF MODULATING SIGNAL GENERATOR ............................................... 16
FIGURE 14: TIMING SIGNALS OF HP AND HM WITH RESPECT TO CONTROL VOLTAGE VC .......... 17
FIGURE 15: SCHEMATIC OF AMPLITUDE MODULATOR .............................................................. 17
FIGURE 16: EFFECT OF VX AND VG ON ID ................................................................................. 18
FIGURE 17: TIMING SIGNALS FOR AMPLITUDE MODULATOR SIGNALS ..................................... 18
FIGURE 18: CIRCUIT DIAGRAM OF SWITCHING CURRENT AMPLIFIER ........................................ 19
FIGURE 19: SCHEMATIC OF RESISTIVE FEEDBACK CMOS INVERTING BUFFER .......................... 19
FIGURE 20: VOLTAGE TRANSFER CHARACTERISTIC OF CURRENT BUFFER WITH AND WITHOUT
FEEDBACK RESISTOR ......................................................................................................... 20
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FIGURE 21: SCHEMATIC OF HIGH-PASS RC FILTER ................................................................... 20
FIGURE 22: OUTPUT SWING AND CORRESPONDING PSD FOR 3RD TO 7TH DERIVATIVE GAUSSIAN
PULSE ................................................................................................................................ 22
FIGURE 23: OUTPUT SWING AND CORRESPONDING PSD FOR 8TH TO 11TH DERIVATIVE
GAUSSIAN PULSE .............................................................................................................. 23
FIGURE 24: RELATIONSHIP BETWEEN VPP/PW PARAMETER WITH RESPECT TO PULSE ORDER .. 25
FIGURE 25: RELATIONSHIP BETWEEN VPP AND PULSE WIDTH WITH RESPECT TO PULSE ORDER 25
FIGURE 26: BLOCK DIAGRAM OF THE PROPOSED TRANSMITTER ................................................ 26
FIGURE 27: (A) SCHEMATIC OF VCIDL, (B) TIMING DIAGRAM OF THE DELAYED SIGNALS ........ 27
FIGURE 28: IMPULSE GENERATOR BLOCK ................................................................................ 27
FIGURE 29: TIMING DIAGRAMS OF CHARGING AND DISCHARGING SIGNALS............................... 28
FIGURE 30: SCHEMATIC OF IMPULSE COMBINER CIRCUIT ......................................................... 29
FIGURE 31: TIMING DIAGRAM OF PULSES FROM IMPULSE COMBINER ........................................ 30
FIGURE 32: SCHEMATIC OF MODULATING SIGNAL GENERATOR ................................................. 30
FIGURE 33: TIMING DIAGRAM OF THE MODULATING SIGNAL ..................................................... 31
FIGURE 34: SCHEMATIC OF AMPLITUDE MODULATOR .............................................................. 32
FIGURE 35: EFFECT OF VX AND VG ON ID ................................................................................. 32
FIGURE 36: TIMING SIGNALS FOR AMPLITUDE MODULATOR SIGNALS ..................................... 33
FIGURE 37: CIRCUIT DIAGRAM OF SWITCHING CURRENT AMPLIFIER ........................................ 34
FIGURE 38: SCHEMATIC OF RESISTIVE FEEDBACK CMOS INVERTING BUFFER .......................... 34
FIGURE 39: VOLTAGE TRANSFER CHARACTERISTIC OF CURRENT BUFFER WITH AND WITHOUT
FEEDBACK RESISTOR ......................................................................................................... 35
FIGURE 40: SCHEMATIC OF RC FILTER ..................................................................................... 35
FIGURE 41: SIMULATED OUTPUT WAVEFORM FOR THE PROPOSED DIFFERENTIAL UWB PG ...... 36
FIGURE 42: SIMULATED PSD OF OUTPUT WAVEFORM IN COMPLIANCE WITH INDOOR FCC MASK
.......................................................................................................................................... 37
FIGURE 43: SIMULATED POWER SUPPLIED BY THE SOURCE FOR PRF OF 100MHZ .................... 37
vi
List of Tables
TABLE 1: IEEE STANDARD RF LETTER-BAND NOMENCLATURE. (ADAPTED FROM [8]) ............. 3
TABLE 2: PERFORMANCE OF PROPOSED PULSE GENERATOR .................................................... 21
TABLE 3: PERFORMANCE COMPARISON WITH PREVIOUSLY REPORTED GENERATORS ................ 24
TABLE 4: COMPARISON OF UWB TRANSMITTER WITH THE PREVIOUS WORK ............................ 38
vii
Acknowledgements
First of all, we are grateful to Almighty for our good health and well-being that were
necessary to complete this book.
We then would like to express our sincere gratitude to our thesis supervisor Dr. Apratim
Roy for his continuous support on our thesis study and related research, for his patience,
motivation, and immense knowledge. His guidance helped us in all the time of research and
writing of this thesis. I could not have imagined having a better supervisor and mentor for our
thesis works.
Last but not the least, we would like to thank our families: our parents and to our
siblings for supporting us spiritually throughout writing this thesis.
viii
Abstract
This work presents higher derivative Gaussian pulse generator using enhanced
amplitude modulator with differential connected load. The aim of design was to obtain a high
amplitude Gaussian pulse with low power consumption and small form factor usage. The
amplitude modulator provides pulse shaping and a resistive feedback current buffer enhanced
the output swing. Use of active/passive-on/off chip inductor as a filter is avoided for making
the chip smaller.
Two designs are proposed using same approach. First design is a voltage controlled
multi derivative Gaussian pulse generation which offers high coverage area adaptability.
Second design is a 7th derivate Gaussian pulse generator which provides better output voltage
performance compared to previous design with a trade off in power consumption and coverage
area adaptability.
The performance of the proposed pulse generator has been compared with some other
notable UWB topologies. The simultaneous attainment of high speed, low noise and low power
consumption compared to reported transmitters make this topology suitable for on-chip
communication.
1
Chapter 1
INTRODUCTION
1.1. Motivation
Electronics technology is changing the world like a miracle where microelectronics is
worthy of having a large share of credit. The idea of integrating electronic circuits
commonly known as IC, founded in 1949, is going through continuous development in
terms of speed, functionality and power dissipation. The initial choices of materials- silicon
substrates, silicon dioxide gate, intermediate dielectrics, aluminum interconnection and
process such as planer technology and photolithography have supported this development
for a long period. But as the devices are being continually scaled year after year for more
demanding functionality introducing some changes are becoming increasingly obvious in
near future to stay effectively on the technology roadmap.
Semiconductor industry is moving forward with an accelerated pace. Billions of
transistors are being integrated on a single chip. To make room for the increasing number
of transistors in a single chip scaling in transistor dimension is a must. A year comes and
we get a new process technology for fabrication with smaller device dimensions but larger
area and complexity. Decrease in minimum feature size has led to a decrease in interconnect
cross-sectional area and pitch. Increase in chip area has resulted in increase in
communication distance (wire length). Lastly, increase in chip complexity has demanded
more communication channels resulting in an increase in the number of metal layers. An
increase in the number of metal layers leads to increase in total wire capacitance and
increases delay. For a foreseeable future the scaling of transistors will continue and the
problems associated with it will increase. To quantify the magnitude of the delay incurred
by an interconnect of length, d, with negligible series resistance, is proportional to d and
the square root of the relative dielectric constant, εr, of the inter level dielectric (ILD). For
an ILD of εr = 4.0 (SiO2), the time of flight (TOF) is about 6 ps/mm. For an x-direction
signal of interest, it is usually surrounded by many y-direction signal lines on an adjacent
wiring layer. These orthogonal signal lines will add capacitance and further degrade the
TOF to as much as 8 ps/mm. These numbers are even compared to the delays of a NAND
gate with a fan out of 3 which are 70, 30 and 12 ps for the 250, 130 and 45 nm technologies
respectively. So scaling of transistors deteriorate device performance.
This A microprocessor often requires a long interconnection line between the arithmetic
logic unit (ALU) and the cache storage. For 250, 130 and 45 nm technologies signal line is
assumed to be equal to the edge dimension of the chip that is around 15 mm. The TOF for
such lines would lie in the 125 to 250 ps range, increasing with the lines got smaller and
chips larger. These numbers ranging from 2 to 20 times the gate for the equivalent design
rule are completely unacceptable burden in device performance.
2
Several measures are identified as possible solutions to these problems faced; such as
shifting from aluminum to copper for metallization, using low permittivity dielectric layer,
reverse scaling of wire geometries, adding repeaters, and standard cell modification. But
even these approaches won’t be able to meet challenges in foreseeable future and encounter
fundamental material limits. Thinking outside the box is the only way to see the light at the
end of the tunnel. One of such thoughts is to introduce wireless interconnect.
1.2. Overview of On-chip Wireless Interconnects
As CMOS device dimensions are undergoing through successive scaling down,
operating speed of CMOS devices will soon cross the 100 GHz mark. Successful RF
wireless link demands that the size of the antenna to be comparable with their wavelengths
for efficient transmission and reception. To learn about the exact numbers, we assume 24
GHz as the operating speed and the corresponding wavelength of the electromagnetic
waves in silicon is 3.7 mm. This number is promising because integration of an antenna on
chip won’t require much space. So, for inter-chip and intra-chip communication wireless
interconnect technique can be used [4]-[5]. A block diagram is shown in Fig 1, where a
transmitter (Tx) is transmitting clock signal and four receiver (Rx) modules are receiving.
This technique was used in [6] for high speed clock distribution successfully.
Figure 1: Block diagram of a typical wireless interconnect
1.3. Why Wireless Interconnect?
RF/Wireless interconnect sends the data to the user without any wire as the name
suggests. The fabrication of wireless interconnect is simpler than some other interconnect
process e.g. optical interconnect which is at the same time cheaper and consumes low
power. Different multiplexing techniques e.g. FDMA, CDMA etc. can be adopted to
increase the data transmission ability manifolds with the advantage of reducing crosstalk
at the same time.
3
Some other gains, such as low power spectral density, low interference, simple
architecture, wider bandwidth, fully possible to integrate on a silicon chip and many more
will vote for this technique. So, this technique shows a great promise to replace the current
interconnect system in future.
1.4. UWB Transmitter
The transmitter’s purpose is to generate an electrical signal that is transmitted by the
antenna system, and received by the antenna system. As such, the transmitter specifications
focus on the desired transmitted waveform, and the transmitter hardware is designed to
generate the specified waveform. Waveform characteristics and transmitter technologies
are presented in the following sections.
Radar systems operate over a wide range of frequencies in the microwave regime, often
considered to be between 300 MHz and 300 GHz [7]. In the past, most operational systems
were designed in the 100 MHz to 36 GHz range; however, systems exist that operate at
frequencies as low as a few megahertz and up to the millimeter-wave regime, where
wavelengths are on the order of a millimeter [8]. Impulse, or carrier-free, radars operate
down to frequencies on the order of 1 MHz [9] and light detection and ranging (LIDAR)
systems operate in the optical regime [10]. The microwave spectrum is subdivided into
bands, as noted in Table 1.
Table 1: IEEE Standard RF Letter-Band Nomenclature. (Adapted from [8])
Band Designation
Frequency Range
HF
330 MHz
VHF
30300 MHz
UHF
3001000 MHz
L
12 GHz
S
24 GHz
C
48 GHz
X
812 GHz
Ku
1218 GHz
K
1827 GHz
Ka
2740 GHz
V
4075 GHz
W
75110 GHz
mm
110-300 GHz
4
Transmission in the electromagnetic (EM) spectrum is regulated by government
bodies, such as the Federal Communications Commission (FCC) in the United States. A
radio license is required to operate a microwave system in most of the EM spectrum;
notable exceptions are the industrial, scientific, and medical (ISM) bands, which are 902
928 MHz, 2.4002.484 GHz, and 5.7255.850 GHz in the United States, and the UWB
band, which is 3.1-10.6 GHz in the United States. While a license is not required, it is
important to note that explicit rules exist for transmission in the ISM and UWB bands,
especially related to the allowed power densities. Microwave signals can be characterized
by their carrier, or center, frequency and bandwidth. The carrier frequency is often defined
as the frequency in the middle of the transmission band. For example, the carrier frequency
could be 1.5 GHz for a radar operating in the 12 GHz L-band. The bandwidth describes
the range of frequencies covered by the microwave signal and can be defined in a variety
of ways.
1.5. FCC Spectral Mask
After recognizing the potential advantages of UWB, the Federal Communications
Commission (FCC) developed a report to allow UWB as a communications and imaging
technology. A UWB definition was created as a signal with a fractional bandwidth
greater than 0.2 or which occupies more than 500 MHz of spectrum. The fractional
bandwidth is defined as 2(fH-fL)/(fH+fL), where fH and fL are the upper and lower
frequencies, respectively, measured at -10 dB below the peak emission point. To allow
government and industry to conduct UWB testing, frequency spectrum from 3.1GHz to
10.6GHz was allocated for communications use below specified power levels, while
imaging was limited to below 960 MHz, as seen in Figure 2 below. A significant
amount of testing will be performed to calculate the amount of interference that UWB
causes to narrowband signals. Therefore, until more knowledge is acquired in this area,
the FCC established EIRP levels for various ranges of frequencies influenced by
preexisting emitting sources. For indoor systems, the average output power spectral density
is limited to -41.3 dBm /MHz, which complies with emission limits to successfully control
radio interference.
Although the FCC has regulated spectrum and power levels for UWB, there is
currently no standard for industry to follow. Discussions have developed on the use of
two standards, specifically, multiband orthogonal frequency division multiplexing
(OFDM) and direct sequence spread spectrum (DS-SS), which is based on impulse radio
technology. Each of these schemes has their advantages in a communications system. Prior
to the recent industry boom with these standards, the most common UWB system
implementation was impulse radio, where ultra-short baseband pulses are used with a
variety of modulation schemes to transfer data. Impulse radio has various advantages over
OFDM, with its ability to penetrate through materials and resolve multipath with path
length differences on the order of a foot or less. Impulse radio also allows for lower power
5
consumption with a low duty cycle, making it very beneficial in low probability of
detection applications.
There are three primary drawbacks to current implementations of impulse radio, namely
lack of high data rates, lack of long communication range, and analog components are
necessary to construct the system. The primary focus of this thesis is to develop a
transmitter which produces high data rate and high amplitude UWB pulses, because high
amplitude of pulses allows to increase the distance of communication.
Figure 2: FCC Spectral Mask for UWB Indoor Communication Systems
1.6. Thesis objectives
To achieve voltage swing as high as possible.
To fit the PSD into allotted UWB frequency range (3.1 GHz to 10.6 GHz).
To reduce pulse duration as small as possible to obtain a higher data rate.
To reduce noise in output as much as possible
To mitigate interference components
6
1.7. Thesis Organization
There are total nine chapters in this book. Summary of each chapter is presented here.
Chapter 1 is the introduction of UWB pulse, FCC regulation and necessity of UWB
circuits to reduce wire interconnects. Here, some parameters of signals, in both
frequency and time domain, used in later chapters of the book have been introduced.
Chapter 2 describes UWB communication technology, its advantages compared to
other communication schemes and the purpose of circuit design to meet most
desirable result.
Chapter 3 describes design background of voltage controlled Multi-derivative pulse
generator with enhanced amplitude modulator.
Chapter 4 presents the CMOS circuit design to generate of voltage controlled Multi-
derivative pulse generator.
Chapter 5 represents simulation results of the design with voltage controlled Multi-
derivative pulse generator.
Chapter 6 describes design background of 7th derivative pulse generator with
enhanced amplitude modulator.
Chapter 7 presents the CMOS circuit design to generate of 7th derivative pulse
generator.
Chapter 8 represents simulation results of the design with 7th derivative pulse
generator.
Finally chapter 9 includes summary of the whole thesis and some suggestions on
future of this technology have been included.
7
2. Chapter 2
UWB ON-CHIP WIRELESS
COMMUNICATION
2.1. Introduction
UWB technology has been used in the areas of radar, sensing and military
communications during the few decades. A substantial surge of research interest has
occurred since February 2002, when the FCC issued a ruling that UWB could be used for
data communications as well as for radar and safety applications [11]. Since then, UWB
technology has been rapidly advancing as a promising high data rate wireless
communication technology for various applications.
In this chapter, we present the basic theory behind the use of UWB pulses for
communications. Specifically, we discuss the generation and shaping of UWB pulses,
the modulation of the resulting pulses, and receiver architectures. Additionally, we
briefly discuss signal design for multiple access.
2.2. History of UWB Pulse
UWB systems have been historically based on impulse radio because it transmitted data
at very high data rates by sending pulses of energy rather than using a narrowband
frequency carrier. Normally, the pulses have very short durations, typically a few
nanoseconds (billionths of a second) that results in an UWB frequency spectrum.
The concept of impulse radio initially originated with Marconi, in the 1900s, when
spark gap transmitters induced pulsed signals having very wide bandwidths [12]. At that
time, there was no way to effectively recover the wideband energy emitted by a spark gap
transmitter or discriminate among many such wideband signals in a receiver. As a result,
wideband signals caused too much interference with one another. So the communications
world abandoned wideband communication in favor of narrowband radio transmitter that
were easy to regulate and coordinate.
In 1942-1945, several patents were filed on impulse radio systems to reduce
interference and enhance reliability [13]. However, many of them were frozen for a long
time because of the concerns about its potential military usage by the U.S. government. It
is in the 1960s that impulse radio technologies started being developed for radar and
military applications.
In the mid-1980s, the FCC allocated the Industrial Scientific and Medicine (ISM)
bands for unlicensed wideband communication use. Owing to this revolutionary spectrum
8
allocation, WLAN and Wireless Fidelity (Wi-Fi) have gone through a tremendous
growth. It also leads the communication industry to study the merits and implications
of wider bandwidth communication.
In February, 2002, the FCC amended the Part 15 rules which govern unlicensed radio
devices to include the operation of UWB devices. The FCC also allocated a bandwidth of
7.5GHz, i.e. from 3.1GHz to 10.6GHz to UWB applications [11], by far the largest
spectrum allocation for unlicensed use the FCC has ever granted.
According to the FCC’s ruling, any signal that occupies at least 500MHz spectrum can
be used in UWB systems. That means UWB is not restricted to impulse radio any more, it
also applies to any technology that uses 500MHz spectrum and complies with all other
requirements for UWB.
2.3. Gaussian Pulse
There are many techniques available to create pulses. Gaussian pulse is one of the most
favorite techniques used by UWB system which is said to have bandwidth at least 20% of
its mid-frequency or to have greater than or equal to 500MHz -10dB bandwidth. General
expression for Gaussian pulse is given by the following equation (1) [14]:


Where t, and A are defined as time, pulse width parameter and amplitude
controlling parameter respectively. To transmit information from one place to another, 1st
and 2nd derivatives of Gaussian pulses were used traditionally as transmission carrier in
impulse radio ultra-wideband systems. But in work of [14] it has been shown that the 5th
derivative of Gaussian pulse is the most efficient one to transmit as transmission carrier.
The equation is given by [14]:

 



The Gaussian pulse has a very narrow width ranging from hundreds of picoseconds
to few nanoseconds. So, it has a large bandwidth (from 1GHz to tenths of GHz) in the
frequency domain. As it shares large band, the narrowband signal sharing the same
frequency domain or bandwidth may interfere with this carrier signal. In this regard, the
Federal Communications Commission (FCC) has given a frequency spectrum mask that
must be satisfied by our designed UWB systems for indoor and outdoor applications.
9
2.4. Advantages of UWB communication
UWB signals possess very large bandwidth which can support data transmission at
a very high rate. The more the bandwidth the shorter the pulses in width. So more
data can be transmitted within a certain time using these sharper pulses. However,
excessively large bandwidth cannot be obtained because of the practical issues
related to the transceiver circuits. UWB signals possess very large bandwidth which
can support data transmission at a very high rate. The more the bandwidth the
shorter the pulses in width. So more data can be transmitted within a certain time
using these sharper pulses. However, excessively large bandwidth cannot be
obtained because of the practical issues related to the transceiver circuits.
Since the signal power is distributed over the entire bandwidth, the power spectral
density decreases as the bandwidth increases. This is why the power spectral density
of an UWB signal is very low and is unlikely to interfere with other communication
channels. Short impulse prevents destructive interference from multipath and the
multipath components can be individually resolved. Moreover, Carrier-less nature
of waveform results in less fading, even when pulses overlap. This reduces fade
margin in link budgets.
Modulation techniques of UWB signals are easier. UWB signals themselves are of
high frequency, they do not need the assistance of any other high frequency carrier
for modulation. These signals can be modulated using simple modulation
techniques like PAM (Pulse Amplitude Modulation), PPM (Pulse Position
Modulation), BPSK (Binary Phase Shift Keying), OOK (On-Off keying) etc.
The circuit for transceiver is relatively simple as there is no need for
synchronization, carrier generation etc. Again, simple modulator in turn implies a
simple de-modulator. Thus circuit is simple and cost is minimum.
Therefore, high bandwidth, low power, low cost make carrier less UWB technology a
viable and attractive competitor for wireless interconnect system.
10
3. Chapter 3
DESIGN BACKGROUND OF
VOLTAGE CONTROLLED MULTI
DERIVATIVE IR-UWB PULSE
GENERATOR
A simulation is
synthesized on
MATLAB using Eq.
(1) and (2) to
generate different
orders of Gaussian
pulse waveforms
and their respective
PSDs demonstrated
in Figure 3. An
observation has
been made while
fitting those
waveforms in the
FCC mask with
maximum amplitude
and minimum pulse
width. According to
Figure 4, increment
in the order of
Gaussian pulses
increases Vpp and
PW (from 3rd order
to 7th order) and
remains more or less
unchanged (from
higher than 7th
order).
Figure 3: Left Column represent Vpp vs time for 3rd order to 7th order Gaussian pulse (order increases
row-wise) and right column represent corresponding PSDs for the voltages in the left column
11
Figure 4: Relationship between Vpp and Pulse Width with respect to pulse order
Considering the analysis above, the center frequency of any Gaussian pulse can be
controlled by it’s pulse width and order of the pulse. Increasing pulse width will left-shift
the center frequency and increasing the order of pulse will right-shift the center frequency.
According to Figure 5, increasing pulse width of two 5th order Gaussian pulses from 440 ps
to 610 ps left shifts center frequency from 8 GHz to 5.3 GHz. And from Figure 6, an
increment in the order of the Gaussian pulse from 5th to 7th for a similar pulse width of 610
ps shifts center frequency from 5.3 GHz to 7.2 GHz. To summarize, there is an inverse
relationship between pulse order and pulse duration while the center frequency is
considered constant. In this proposed design, both the order and pulse width of the pulse
are increased simultaneously for keeping center frequency inside 3GHz to 10GHz while
fitting FCC mask.
Figure 5: Left Shift of center frequency from 8 GHz to 5.3 GHz for changing the pulse width of
5th order Gaussian pulse from 440ps to 610ps
12
Figure 6: Right Shifting of center frequency from 5.3 GHz to 7.2 GHz for changing from 5th
order to 7th order for constant PW of 613 ps
13
4. Chapter 4
CMOS DESIGN OF VOLTAGE
CONTROLLED MULTI DERIVATIVE
IR-UWB PULSE GENERATOR
4.1. Block Diagram
In this section, the implementation of the design concept from the previous section is
inspected. A proposed design block diagram is presented in Figure 7.
Figure 7: Block diagram of the proposed transmitter
The design requires a Rectangular PG for controlling PW generated by Voltage
Controlled Delay Line (VCDL). A ring oscillator is necessary for generating different
orders of the Gaussian pulses. A modulating signal generator constructs a triangular pulse.
The triangular pulse is exploited to two PMOS Amplitude Modulators (AM) for pulse
shaping of the signals from oscillator block. These differential outputs from AM circuits
cannot be exploited to directly drive the antenna. A switching inverting current Buffer
generates sufficient current to drive the antenna and the high pass RC filter helps to
diminish lower frequency components for each differential output line.
4.2. Rectangular Pulse Generator
The motivation of this circuit block is to generate two voltage controlled rectangular
pulses FP and HP where HP’s duration is half of FP. FP signal gives a positive pulse during
pulse creation state and remains zero during idle state. In Figure 8, two current starved
delay lines are used to generate inverted delayed signals. These current starved delay lines
are regulated by a single current mirror circuit which is constructed by an NMOS M1 and
a PMOS M2. Both M1 and M2 are operated in saturation mode. They provide a constant
current towards current starved delay lines through M3 and M6 which is controlled by
control voltage VC. Widths of the MOSFETs are chosen in such a way to keep rising and
falling propagation delay equal. D1 is the inverted delayed signal of IN signal and D2 is
14
the delayed signal of D1. Finally, AND gates with inputs IN and D1 devise HP signal and
inputs IN and D2 devise FP signal according to Figure 9.
Figure 8: Schematic of Rectangular PG
Figure 9: Timing signals of Rectangular PG
Current of the current mirror circuit boosts by the increment of VC. This causes
capacitance of current starved delay blocks to charge and discharge faster which results in
a diminution in the pulse width of FP and HP signals presented in Figure 10.
15
Figure 10: Timing signals of HP for different values of Control Voltage Vc
4.3. Ring Oscillator
A CMOS Oscillator with three inverter cells is adopted to generate distinct orders of
Gaussian pulses. In the circuit diagram shown in Figure 11, three inverters are connected
in a ring configuration for oscillating signals generation. MNA1 NMOS is connected with P
node with FP as gate voltage to generate identical oscillating signals during pulse creation
state only.
Figure 11: Circuit Diagram of VCO block
It can be observed from Figure 12 that A, C nodes from the oscillator signals don’t
stabilize at 0 V or Vdd V during idle state. According to the design requirement, these
signals need to be at Vdd V during the idle state. So, two NAND gates are utilized conferred
in Figure 11; one with A, FP as input and AX as output and the other with C, FP as input
and CX as output.
16
Figure 12: Timing signals of A, C, AX, CX
4.4. Modulating Signal Generator
Pursuant to Figure 13, the Modulating
Signal Generator block utilizes HP signal
to generate a triangular signal through a
capacitor Cm. Cm starts to charge
through MMP1 for the positive edge of HP
signal. Hence, voltage at HM starts to
increase. Right after the negative edge of
HP signal, Cm discharges to the GND
through MMN1 and voltage at HM drops.
Peak amplitude and duration of voltage at
HM will depend on the value of
capacitance of Cm, W/L ratios of MMN1,
MMP1 and duration of HP signal. As stated
in Figure 14, pulse duration and peak amplitude of the output triangular pulse depend on
pulse duration of HP signal which is controlled by VC.
Figure 13: Schematic of Modulating Signal Generator
17
Figure 14: Timing signals of HP and HM with respect to control voltage VC
4.5. PMOS Amplitude Modulator
Figure 15 shows the PMOS AM circuit with a
carrier signal VX, modulating signal Vg and
modulated output signal VD. A resistance RM is
connected between VD and VX. AX, CX from the
oscillator block serve as VX; AY, CY serve as output
VD for two Amplitude Modulator circuits used in the
design whereas triangular pulse at node HM from
Modulating Signal Generator acts as Vg.
PMOS operates in linear mode because of
Vg≥0V. ID can be calculated using the current
equation of PMOS.
ID =k ((VSG -Vt) VSD -VSD2/2) ………………..(3)
As R is connected in series,
ID = ( VD - VX) / RM
=> VD = VX + ID *R ………………………….(4)
Before analyzing the impact of Amplitude Modulator on transmitter, dependence
of Id with respect to VG and VX must be perceived. Change on Id with respect to VX for VG
varying from 0V to 1.2V is observed in Figure 16. For any fixed VG, rise in VX causes VSD
to decrease which also decrements Id based on equation (a). When VG is increasing from 0
Figure 15: Schematic of Amplitude
Modulator
18
to higher amplitude, Id is limited to lower absolute value supporting equation (a). VG near
Vdd (1.2V) operates PMOS at cut-off mode with negligible value of ID.
Figure 16: Effect of VX and VG on ID
According to Figure 17, during 0<Vg<Vdd and VX ≈Vdd at t1 time, VSD≈0 so Id≈0.
VD will follow VX considering equation (b). Above condition of VG and VX establishes the
modulating waveshape. For 0< VG <Vdd and Vx≈0 at t2 time, Id has considerable value
and VD=ID*RM ≈Vdd. When VG =Vdd, Id equals 0. VD =VX≈0V at t3 time. During idle
state at t4 time, VG =0, PMOS is ON and VD =Vdd.
Figure 17: Timing Signals for Amplitude Modulator Signals
19
4.6. Switching Current Amplifier
An inverting buffer as a current amplifier can
generate sufficient current to drive the differential
load. As the widths of NMOS and PMOS are quite
large in CMOS inverting buffer circuits, generally
they have high power consumption and swift
transition in unloaded condition according to
Voltage Transfer Characteristic (VTC) displayed in
Figure 20. As output signals from previous AM
blocks have ripples near Vdd, CMOS inverter
buffers consider these ripples as noise and invert to
0V. Addition of a feedback resistor RF presented in
Figure 19, can solve this dilemma. When VD is 0V,
VZ is Vdd. But the feedback resistor RF flows
current from VZ to VD which drops VZ to a lower
voltage than Vdd. Similarly, VZ will be higher than
0V when VD is Vdd. So, Incorporation of feedback
resistor creates slower voltage transition and also
lowers output voltage headroom in unloaded
condition according to VTC given in Figure 20.
Lower the feedback resistance, voltage transition is
slower and output voltage range is lower. So,
optimum value of feedback resistance and MOSFET
widths are chosen in such a way that output signals
provide better performance and optimum power
consumption. A NMOS MNB2 is employed in Figure
19, to interrupt current flowing through RF resistor
in idle state. This offers lower power consumption
in idle state. Another power consumption
optimization is achieved using PMOS modulator in
the previous stage. As the output of AM at idle state
is Vdd, which discharges output to GND through the
buffer. The discharging happens swiftly and
consumes low power during rest of the idle state.
Using NMOS modulator would have required continuous charging and high power
consumption would have materialized during idle stage.
Figure 19: Schematic of resistive feedback
CMOS inverting buffer
Figure 18: Circuit diagram of Switching
Current Amplifier
20
Figure 20: Voltage transfer characteristic of current buffer with and without feedback resistor
4.7. High Pass RC Filter
According to Figure 21, a high-pass RC filter is connected at the output node of the
Switching Current Amplifier to eliminate lower frequency components of the differential
output signal for fitting FCC mask. RL is selected 100 ohm considering impedance matching
for differential circuit connection. Output voltage can be lowered due to voltage divider
configuration in the high-pass filter. Both switching Current Amplifier and value of
capacitance are tuned to achieve maximum orders of Gaussian waveshapes with acceptable
output voltage.
Figure 21: Schematic of High-pass RC Filter
21
5. Chapter 5
SIMULATION RESULTS OF VOLTAGE
CONTROLLED MULTI DERIVATIVE
IR-UWB PULSE GENERATOR
5.1. Simulation Overview
The proposed UWB OOK pulse generator is simulated using 90nm CMOS spice
model files from Predictive Technology Model (PTM) on HSPICE circuit simulator. The
supply voltage of the technology is 1.2V and the generator is capable of driving 100 ohm
load impedances connected in differential configuration. For PRF of 100MHz, the pulse
generator can generate 3rd to 11th order Gaussian output pulses conforming to FCC mask.
The order of output pulse is operated by a control voltage. Output voltage swing, pulse
width, bandwidth and power consumption is 410 - 633 mV, 300 - 770 ps, 2.73 - 14.81 GHz
and .48 - .69 mW respectfully for 3rd to 11th order Gaussian output waveshapes. 5th to
11th order Gaussian pulses also avoid WLAN interference around 4 to 6 GHz by creating
a notch around 5GHz. Table 2 represents simulation results from the proposed generator.
Output pulses with their corresponding PSD with outdoor FCC mask are observed in Figure
22.
Table 2: Performance of Proposed Pulse Generator
order
3
4
5
6
7
8
9
10
11
Vcontrol (V)
.6
.524
.495
.481
.46
.44
.432
.42
.413
Vpp (mV)
410
473
502
544
579
605
618
629
633
Pulse Width (ps)
300
390
410
490
530
580
640
750
770
Frequency band (GHz)
3.16-
17.97
4.23-
18.4
5.21-
16.34
5.57-
11.074
6.23-
10.67
6.326-
10.5
6.66-
10.076
6.93-
9.8
6.96-
9.69
-10dB BW (GHz)
14.81
14.1
11.13
5.5
4.43
4.16
3.41
2.87
2.73
Energy (pJ/pulse)
4.895
4.68
4.74
4.94
5.32
5.62
6.07
6.67
6.9
Average power (mW)
.4895
.468
.474
.494
.532
.562
.607
.667
.69
FCC mask
outdoor
outdoor
indoor
outdoor
outdoor
outdoor
outdoor
outdoor
outdoor
WLAN interference reduction
no
no
yes
yes
yes
yes
yes
yes
yes
22
Figure 22: Output swing and corresponding PSD for 3rd to 7th derivative Gaussian pulse
23
Figure 23: Output swing and corresponding PSD for 8th to 11th derivative Gaussian pulse
24
Table 3 summarizes the comparison of the key specification among this design and
with previously reported pulse generators. It shows that the proposed pulse generator is
Table 3: Performance comparison with previously reported generators
Reference
[10]
[18]
[34]
[27]
This work
Technology(CMOS)
130nm
180nm
180nm
180nm
90nm
Modulation
BPSK
OOK
OOK
OOK
OOK
Pulse shaping process
Ring oscillator
and RLC filter
CMOS active
inductor oscillator
Ring oscillator
and RLC filter
Edge combiner and
RLC filter
Ring oscillator and RC
filter
Vdd (V)
1.2
1.8
1.8
1.5
1.2
Vpp (mV)
389
120
180
500
410-633
Pulse Width (ps)
600
5500a
600
800
300-770
PRF(MHz)
200
30a
200
100
100
Frequency band (GHz)
5.5-10.5
3.5-4.5a
4.9-10.6
3.1-5.1
3.16-17.97
-10dB Bandwidth (GHz)
5C
.528
5.7
2
2.73-14.81
Energy (pJ/pulse)
2.2
88.67a
16.4
4.7
4.8-6.9
Average power (mW)
.44
22.6
3.28c
-
.48-.69
Conform FCC
Yes(indoor)
Yes(indoor)
Yes(indoor)
Yes(outdoor)
Yes(indoor)
c= calculated from the literature data
a=calculated from the literature figure
5.2. Limitations
The proposed design proffers flexibility of high data rate and high coverage area with
a controlling voltage source. But the controlling voltage source has a narrow operating
range of .4V to .6V. So, it will be difficult to tune the circuit within this range. During
simulation, some modification were done. But this is the highest range which was achieved.
25
6. Chapter 6
DESIGN BACKGROUND OF 7TH
DERIVATIVE GAUSSIAN PG USING
ENHANCED AMPLITUDE
MODULATION
A simulation is synthesized on MATLAB using Eq. (1) and (2) to generate different
orders of Gaussian pulse. An observation has been made while fitting those waveforms in
the FCC mask with maximum amplitude and minimum pulse width. According to Figure
25, increment in the order of Gaussian pulses increases Vpp and PW (from 3rd order to
7th order) and remains more or less unchanged (from higher than 7th order). High voltage
swing and low pulse width are important performance parameters of any Gaussian pulse
generator. Figure 24 offers the highest peak voltage and lowest pulse width requirement
for any higher order Gaussian pulse within FCC mask. Vpp/PW (Ratio of Output swing
to pulse width) gives a better overview of which derivative of Gaussian pulse can provide
best performance based on this parameter. In Figure 24, 7th derivative Gaussian pulse
gives better result according to simulation. So for this design we opted for 7th derivative
pulse generator using Edge combiner and Pulse combiner circuit blocks from general
architecture. The contribution of our design is the enhanced amplitude modulation
process using PMOS modulator, resistive feedback current buffer.
Figure 25: Relationship between Vpp and Pulse
Width with respect to pulse order
Figure 24: Relationship between Vpp/PW
parameter with respect to pulse order
26
7. Chapter 7
CMOS DESIGN OF 7TH DERIVATIVE
GAUSSIAN PG USING ENHANCED
AMPLITUDE MODULATION
7.1. Block Diagram
The schematic of the proposed UWB PG that receives clock pulse to generate 7th
derivative Gaussian pulse is shown in Figure 26. The designed PG consists of voltage-
controlled inverted delay lines (VCIDL), impulse generators, edge combiner circuits for
forming combined unmodulated pulse. A modulating signal generator, PMOS amplitude
modulators, switching inverting current buffers and RC high pass filters are utilized for
pulse shaping the unmodulated signal to fit the indoor FCC mask.
Figure 26: Block diagram of the proposed transmitter
7.2. Voltage Controlled Inverted Delay Line
Instead of using a higher number of inverters, VCIDL is utilized for synthesizing 9
delayed inverted pulses from the input clock signal presented in Figure 27(a). A current
mirror circuit with a control voltage VC is employed to generate a constant current which
drives the upper and lower MOSFETs of the current starved VCIDLs in saturation mode
with a constant current. Variation of current in the current mirror circuit and VCDLs are
directly proportional to VC. The variation of current through the VCIDLs varies the delay
inversely. The ratio of W/L ratio of PMOS and NMOS is kept at 3.33 for identical rising
and falling transition times. The current mirror circuit is optimized for low power
consumption because it consumes power during idle state too. The delayed inverted pulses
for VC=580mV is shown in Figure 27(b).
27
7.3. Impulse Generator
The impulse generator generates short pulses for low duty cycle operation and low
power consumption shown in Figure 28. Passing a positive triggered signal and the
corresponding delayed negative triggered signal of the previous signal through an AND
gate develops a positive impulse (Dis_even). Similarly, passing a negative triggered signal
and the corresponding delayed positive triggered signal of the previous signal through a
NOR gate, develops a positive impulse (Dis_odd). The negative impulse (Crg) is the
inverted signal of the corresponding positive impulse (dis). The positive and negative
impulse signals are provided in Figure 29.
Figure 28: Impulse Generator Block
Figure 27: (a) Schematic of VCIDL, (b) Timing diagram of the delayed signals
28
Figure 29: Timing diagrams of charging and discharging signals
29
7.4. Impulse Combiner
Conforming to Figure 30, two impulse combiner circuits merge positive and negative
impulses from impulse generator circuit. This block is mainly a digital control where the
number of oscillations per pulse is selected. As the requirement is to produce 7th order
Gaussian pulse, two impulse-combined alternating signals are generated shown in Figure
31.
Figure 30: Schematic of Impulse Combiner Circuit
30
Figure 31: Timing diagram of pulses from impulse combiner
7.5. Modulating Signal Generator
Figure 32: Schematic of modulating signal generator
With clock signal and Do5 as input, a pulse HP is synthesized through a NAND gate. HP
is used as an input in the inverter displayed in figure 32, which is adopted to form a
triangular pulse. The delay time depends on the transistor size and capacitance of Cm.
When Cm starts to charge through Mmp1 for the negative edge of HP signal, voltage across
31
Cm increases. Right after the positive edge of HP signal, Cm discharges to the GND
through Mmn1 and voltage across Cm drops. Voltage output across Cm at node HM is
shown in figure 33.
Figure 33: Timing diagram of the modulating signal
32
7.6. PMOS Amplitude Modulator
Figure 15 shows the PMOS AM circuit with a
carrier signal VX, modulating signal Vg and modulated
output signal VD. A resistance RM is connected
between VD and VX. AX, CX from the oscillator block
serve as VX; AY, CY serve as output VD for two
Amplitude Modulator circuits used in the design
whereas triangular pulse at node HM from Modulating
Signal Generator acts as Vg.
PMOS operates in linear mode because of Vg≥0V.
ID can be calculated using the current equation of
PMOS.
ID =k ((VSG -Vt) VSD -VSD2/2) ………………..(3)
As R is connected in series,
ID = ( VD - VX) / RM
=> VD = VX + ID *R ………………………….(4)
Before analyzing the impact of Amplitude Modulator on transmitter, dependence
of Id with respect to VG and VX must be perceived. Change on Id with respect to VX for VG
varying from 0V to 1.2V is observed in Figure 16. For any fixed VG, rise in VX causes VSD
to decrease which also decrements Id based on equation (a). When VG is increasing from 0
to higher amplitude, Id is limited to lower absolute value supporting equation (a). VG near
Vdd (1.2V) operates PMOS at cut-off mode with negligible value of ID.
Figure 35: Effect of VX and VG on ID
Figure 34: Schematic of Amplitude
Modulator
33
According to Figure 17, during 0<Vg<Vdd and VX ≈Vdd at t1 time, VSD≈0 so Id≈0.
VD will follow VX considering equation (b). Above condition of VG and VX establishes the
modulating waveshape. For 0< VG <Vdd and Vx≈0 at t2 time, Id has considerable value
and VD=ID*RM ≈Vdd. When VG =Vdd, Id equals 0. VD =VX≈0V at t3 time. During idle
state at t4 time, VG =0, PMOS is ON and VD =Vdd.
Figure 36: Timing Signals for Amplitude Modulator Signals
34
7.7. Switching Current Amplifier
An inverting buffer as a current amplifier can
generate sufficient current to drive the differential
load. As the widths of NMOS and PMOS are quite
large in CMOS inverting buffer circuits, generally
they have high power consumption and swift
transition in unloaded condition according to
Voltage Transfer Characteristic (VTC) displayed in
Figure 20. As output signals from previous AM
blocks have ripples near Vdd, CMOS inverter
buffers consider these ripples as noise and invert to
0V. Addition of a feedback resistor RF presented in
Figure 19, can solve this dilemma. When VD is 0V,
VZ is Vdd. But the feedback resistor RF flows
current from VZ to VD which drops VZ to a lower
voltage than Vdd. Similarly, VZ will be higher than
0V when VD is Vdd. So, Incorporation of feedback
resistor creates slower voltage transition and also
lowers output voltage headroom in unloaded
condition according to VTC given in Figure 20.
Lower the feedback resistance, voltage transition is
slower and output voltage range is lower. So,
optimum value of feedback resistance and MOSFET
widths are chosen in such a way that output signals
provide better performance and optimum power
consumption. A NMOS MNB2 is employed in Figure
19, to interrupt current flowing through RF resistor
in idle state. This offers lower power consumption
in idle state. Another power consumption
optimization is achieved using PMOS modulator in
the previous stage. As the output of AM at idle state
is Vdd, which discharges output to GND through the
buffer. The discharging happens swiftly and
consumes low power during rest of the idle state.
Using NMOS modulator would have required continuous charging and high power
consumption would have materialized during idle stage.
Figure 38: Schematic of resistive feedback
CMOS inverting buffer
Figure 37: Circuit diagram of Switching
Current Amplifier
35
Figure 39: Voltage transfer characteristic of current buffer with and without feedback resistor
7.8. RC Filter
The switch in the current amplifier introduces
low-frequency energy in the spectrum, and thus a
high pass filter is needed. The filter
accommodates the pulse in the allowed FCC
spectral mask by filtering out the unwanted
spectral components at lower frequencies without
the use of off-chip or on-chip RLC filter
components. This leads to achieving the low-cost
and small form factored UWB transmitter module.
Here 100 Ω load resistance is employed in
differential connection to match the antenna
characteristics impedance used in wireless
communication.
Figure 40: Schematic of RC filter
36
8. Chapter 8
SIMULATED RESULTS OF 7TH
DERIVATIVE GAUSSIAN PG USING
ENHANCED AMPLITUDE
MODULATION
8.1. Simulation Overview
The proposed UWB OOK pulse generator is simulated using 90nm CMOS spice
model files from Predictive Technology Model (PTM) on the HSPICE circuit simulator.
The supply voltage of the technology is 1V and the generator is capable of driving 100 ohm
load impedances connected at each output of the differential PG that represents the input
impedance of the antenna. Figure 41, 42 and 43 represent the simulated voltage swing, PSD
and power supplied by the source for the output of the PG. The PG has 812 mV output
voltage swing, 680 ps pulse width and .7049 mW power consumption for PRF of 100MHz.
The PSD of the output also fits within indoor FCC spectrum regulation and has a center
frequency of 8 GHz and -10dB bandwidth of 3.24-9.8 GHz .The proposed PG offers high
output voltage swing keeping power consumption optimized despite using additional buffer
circuits.
Figure 41: Simulated output waveform for the proposed differential UWB PG
37
Figure 42: Simulated PSD of output waveform in compliance with indoor FCC mask
Figure 43: Simulated power supplied by the source for PRF of 100MHz
Table 1 summarizes the comparison of the key specification among this design with
previously reported PGs. As supply voltage is not the same for all the reports in other
literature, the percentage of output swing in source voltage (Vpp/Vdd %) can be used for
better result comparison. Proposed PG has almost 2.4 times improvement in the percentage
parameter compared with the closest challenger among other reported results.
38
Table 4: Comparison of UWB transmitter with the previous work
Reference
[10]
[27]
[33]
[35]
This work
Technology(CMOS)
130nm
180nm
130nm
180nm
90nm
Modulation
BPSK
OOK
OOK
-
OOK
Pulse shaping
process
Ring oscillator
and RLC filter
Edge combiner
and RLC filter
LC ladder
filter
RLC filter
Impulse
combiner
and RC filter
order
Higher
7th
higher
7th
7th
Vdd(V)
1.2
1.5
1.5
2
1
Vpp(mV)
380
500
230
136
812
Vpp/Vdd %
31.67C
33.33C
15.33C
6.8C
81.2
Pulse Width (ps)
600
800
1000
350
680
PRF(MHz)
200
100
200
100
100
Frequency band
(GHz)
5.5-10.5
3-5
.96-1.61
6-10
3.24-9.8
Energy (pJ/pulse)
2.2
4.7
21
.4
7.409
Average power
(mW)
.44
.47C
4.2
.04C
.7049
Conform FCC
Yes(indoor)
Yes(outdoor)
Yes(indoor)
Yes(indoor)
Yes(indoor)
C: Calculated from literature data
39
9. Chapter 9
CONCLUSION
9.1. Summary
Nowadays, IR UWB pulse generators opt to use CMOS technology based integrated
circuit design which offers lower power consumption and compact form factor than discrete
circuit design. Different methods have been adopted for the design of pulse generators. One
of the methods generates triangular pulses from the combination of digitally delayed input
signal. The generated triangular pulses use pulse shaping circuit blocks to fit the output’s
frequency in the FCC mask. Pulse shaping is done by controlling the current flow of
the MOSFETs in the pulse combiner stage or by RC filters that cannot generate enough
current to drive the antenna load of 50 ohm [6][15][22][28]. RC filter also works as a
voltage divider causing reduction in output voltage. In some cases with RC filter, drop at
the output voltage can be reduced by using a buffer which requires high power consumption
[7][13][14] or higher load resistance which may increases crosstalk, resonance and cause
difficulty passing EMI requirements for characteristic impedance mismatch [1][4]. Another
pulse shaping method uses on-chip or off-chip bandpass RLC filters on a digitally
generated baseband pulse to filter out unwanted frequency components outside the FCC
mask [2][5][8][19][23]. But on-chip passive inductors used in the filter require larger chip
area with low quality factor and limited range of value inductance. On the other hand, off-
chip filters always use significant area outside the chip making it incompatible for small
form factor use. CMOS active inductor usage can solve these issues [18]. But the trade-off
is in the degraded noise performance. There is another method of pulse generation using
high frequency switching local oscillator (LC, Ring oscillator) with a pulse shaper
[10][18][34]. Using switching oscillators which are active on certain time durations,
curtails high power usage and also helps to generate identical output pulses when the
oscillating frequency is not an integer multiple factor of the clock frequency.
Generally low derivative Gaussian pulse generators are beneficial for high data rate for
their low PW. Contrarily, higher derivative Gaussian pulse generators can offer high
voltage swing without violating FCC mask which is beneficial for higher coverage area.
So, this kind of versatile design can be useful for multipurpose applications. Previously
there have been some works done with several multi-order Gaussian pulses [23][30]. All
these designs are operated by more than one control voltages or digital signals and they
provide performance drawback with their preferred aforementioned architecture usage.
In the first design of this book, we unveil a differential OOK CMOS UWB pulse
generator using a ring oscillator which is shaped by a modulating envelope signal. Using
the modulating signal instead of bandpass filter, gave us an opportunity to generate 3rd to
11th orders of Gaussian pulse with order dependent pulse width which can be controlled
by an isolated voltage source. These pulses fully compile with the FCC spectral mask for
40
indoor devices. A RC high pass filter is utilized for removal of output DC voltage. To cover
up the output voltage drop across 100 ohm load due to low load driving current, a switching
current inverting amplifier is added between the oscillator and RC filter. Combined effect
of amplifier and filter preserves low power consumption. The proposed design also avoids
any kind of on-chip or off-chip inductor which enables the design to be implementable in
a small form factor.
The second design is also a fully integrated OOK CMOS ultra-wideband (UWB)
pulse generator (PG) which is capable of generating 7th derivative Gaussian pulse. The
designed PG consists of voltage-controlled inverted delay lines (VCIDL), impulse
generators, edge combiner circuits for forming combined unmodulated pulse. A
modulating signal generator, PMOS amplitude modulators, switching inverting current
buffers and RC high pass filters are utilized for pulse shaping the unmodulated signal to fit
the indoor FCC mask. This design is also useable for small form factor use as no inductor
is used. The circuit is designed and simulated on 90nm CMOS technology models using
HSPICE.
9.2. Future of Work
In the work presented in this book, 90 nm CMOS process has been used for simulation
of the circuit architecture. More recent technologies (65 nm CMOS) can be used to achieve
low power consumption and compact design. Our first design has some issue with control
voltage range. It can be solved by digitalizing the voltage according to the derivatives of
the required pulse which can be user friendly.
These results are based on Simulation. Due to unavailability of fabrication,
experimental results couldn’t be conducted. Experimental results may give options for
improvements and the accurate accuracy of the design proposed.
QPSK and BPSK can be used in place of OOK modulation to achieve lower BER (bit
error rate) and make utilization of transmission bandwidth better. The term BER is defined
as the number of error bits per every hundred bits transmitted. Though the use of OOK
modulation is advantageous for near zero static power consumption, the application of
QPSK and BPSK may prove to be effective in sensitive communication architectures where
the bandwidth needs to be utilized better with a very low BER.
The presented architecture in this work only deals with the transmission part of the
communication signal. A receiver circuit with antenna can be designed and incorporated
with the presented architecture to make it a complete transceiver architecture.
41
Reference
[1] Semiconductor Industry Association, The National Technology Roadmap for
Semiconductors, San Jose, CA, 1997
[2] P. D. Fisher and R. Nesbitt, “The test of time. Clock-cycle estimation and test
challenges for future microprocessors,’ IEEE Circuits and Devices Magazine, vol. 14, no.
2, pp 37-44, March 1998
[3] C. S. Chang, K. A. Monnig, and M. Melliar-Smith, Interconnection challenges and the
National Technology Roadmap for Semiconductors,” Interconnect Technology
Conference, 1998. Proceedings of the IEEE 1998 international, pp 3-6, June 1998.
[4] A. B. M. H. Rashid, S Watanabe and T. Kikkawa, “Characteristics of Si Integrated
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