Chapter

# Balancing Automation and Control for Formal Verification of Microprocessors

Authors:
• Centaur Technology
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## Abstract

Formal methods are becoming an indispensable part of the design process in software and hardware industry. It takes robust tools and proofs to make formal validation of large scale projects reliable. In this paper, we will describe the current status of formal verification at Centaur Technology. We will explain our challenges and our methodology—how various proofs and verification artifacts are interconnected and how we keep them consistent over the duration of a project. We also describe our main engine—a powerful symbolic simulator with rewriting capabilities that is integrated in a theorem prover and proven correct.

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... Our program is not designed to handle branches implemented for saturation. Therefore, after our program simplified the saturated designs, we sent the resulting terms to a SAT Solver (glucose [36]) with the FGL utility [26], [37], and we have seen that proofs finished successfully in a few seconds. ...
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We have developed an algorithm, S-C-Rewriting, that can automatically and very efficiently verify arithmetic modules with embedded multipliers. These include ALUs, dot-product, multiply-accumulate designs that may use Booth encoding, Wallace-trees, and various vector adders. Outputs of the target multiplier designs might be truncated, right-shifted, or a combination of both. We evaluate the performance of other state-of-the-art tools on verification problems beyond isolated multipliers and we show that our method applies to a broader range of design techniques encountered in real-world modules. Our verification software is verified using the ACL2 theorem prover, and we can soundly verify 1024x1024-bit isolated multipliers and similarly large dot-product designs in minutes. We can also generate counterexamples in case of a design bug. Our tool and benchmarks are available online.
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Book
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Dill, D.L.: Formal Verification of Libra Blockchain Smart Contracts. Recording of the keynote (2020). https://www.youtube.com/watch?v=cYxxJU-Wt2U
Formal Verification of Application and System Programs Based on a Validated x86 ISA Model
• S Goel
Goel, S.: Formal Verification of Application and System Programs Based on a Validated x86 ISA Model. Ph.D. thesis, Department of Computer Science, The University of Texas at Austin (2016). http://hdl.handle.net/2152/46437
Evaluatable, high-assurance microprocessors
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Greve, D., Wilding, M.: Evaluatable, high-assurance microprocessors. In: NSA High-Confidence Systems and Software Conference (HCSS), Linthicum, MD, March 2002. http://hokiepokie.org/docs/hcss02/proceedings.pdf
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• W A A Swords
• S Davis
• J Slobodova
Hunt, Jr., W.A.A., Swords, S., Davis, J., Slobodova, A.: Use of formal verification at centaur technology. In: Hardin, D. (ed.) Design and Verification of Microprocessor Systems for High-Assurance Applications, pp. 65-88. Springer, Boston (2010). https://doi.org/10.1007/978-1-4419-1539-9_3
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