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New Low-Power Switch-Count Structure for Medium/High Power Multilevel Inverter
Abstract
Inverters as one of the most important elements of power systems have been profoundly developed in recent decades and their performance has attracted researches in control and structure point of view. In this paper, a new structure based on low power switch count is proposed for multilevel converter is feeding. The proposed structure is presented for symmetrical /asymmetrical mode and the number of power electronic devices is decreased in comparison with similar works. Considering recent proposed structures, the proposed structure has superior condition in terms of semiconductor switches and drivers count as well as Total Blocked Voltage (TBV). The performance of the proposed symmetrical 29-level converter is analyzed and simulated in MATLAB/Simulink. Keywords-Power electronic converter, multilevel inverter, low power switch-count, reduced number of devices.
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Multilevel inverters are a new generation of DC-AC converters at medium and high voltage and power levels. In this paper, a new single-phase cascaded multilevel inverter is presented. For this purpose, a new basic cell is presented at first. And then, the new multilevel inverter structure is yielded by series connection of these cells. The proposed new cell is only capable of generating positive voltage levels, and therefore, to produce zero and negative voltage levels, the proposed structure is constructed based on H-bridge module. In order to reduce the maximum blocking voltage especially on H-bridge switches, the cascaded connection of proposed converter is investigated. A comprehensive comparison is carried out between the proposed multilevel inverter with the classical and recently introduced structures in terms of the number of switching devices, the number of drivers, the total blocking voltage of the switches as well as the loss and efficiency. The accuracy of the proposed inverter’s performance is simulated in MATLAB/Simulink in symmetric and asymmetric topologies for a 17-level and 23-level output voltage respectively, and then evaluated by the laboratory prototype.
In this paper, a new multilevel inverter is designed to improve the power and voltage quality, which contains a lesser number of switches in the specified voltage levels. The proposed inverter includes power electronic devices such as switches and diode, and DC inputs. In the proposed structure the desired output voltage can be produced by considering a series connection of a novel sub-multilevel module. This structure can be designed in both the symmetric and asymmetric topologies. The proposed structure has superior condition in terms of semiconductor switches and drivers count as well as switching loss. Additionally, the Total Blocked Voltage (TBV) of the proposed converter is compared with the conventional and the novel converters. This topology is studied by symmetric as well as asymmetric topologies through simulations in Matlab/Simulink environment as well as experiments by a laboratory prototype.
A generalized symmetrical multilevel inverter (MLI) topology with an essential feature of smooth commutation during the dead time for inductive loads is presented in this paper. It consists of a level generation unit (LGU) and polarity generation unit (PGU); Both LGU and PGU provide a freewheeling path for load current during the dead time for an inductive load which avoids large voltage spikes across the output. This topology can also generate the required number of levels at the output with a minimum number of components. As it requires fewer components, switching losses, installations space, and cost of the implementation are low. In this paper, a seven-level structure derived from the generalized topology is considered for detailed analysis. Further, to show the effectiveness of the proposed MLI topology over the existing symmetrical topologies in overcoming commutation problem, simulations were performed and are validated with experimental results. A comparative study is made in terms of power switches, power diodes, clamping capacitors, and driver circuits between traditional, recent, and proposed topologies.
In this paper, a bidirectional diode containing multilevel inverter is introduced to reduce the number of switching elements especially in the case of a high number of output voltage levels. In comparison with classic and recently introduced symmetrical topologies, which are trying to reduce the switch count, this topology has a lower number of semiconductor switches in the same number of output voltage levels. This makes the proposed inverter to be a suitable choice for medium voltage applications like renewable energy applications as well as medium voltage electric drives. Moreover, it can be used in a cascaded configuration for high voltage levels. To depict the performance of the proposed structure, a comprehensive comparison is made between this topology and classic and recently proposed symmetric topologies in terms of switch and gate driver count, power losses and cost. The performance of the proposed symmetrical eleven-level converter is analyzed and simulated in MATLAB/Simulink for both PWM and selective harmonic elimination switching methods. Not only the results are desirable, but also the experimental results of laboratory prototype validate the simulation results.
In this paper, a novel Cascaded H-Bridge (CHB)-based multilevel inverter for symmetric/asymmetric configurations is presented. The proposed MLI can be utilized in medium-voltage applications such as electrical machine drives as well as grid connection of renewable energy resources. The proposed structure uses fewer count of semiconductor devices at the same voltage level in comparison with classic and advanced structures. Cascaded connection of the proposed basic cells leads to reduce complexity and increase efficiency of the proposed structure. In order to investigate the capability and superiority of the proposed structure, a comprehensive comparison is conducted between this structure and the advanced ones in terms of efficiency, switch and gate driver count, and total blocking voltage (TBV). The fundamental frequency switching method is employed to generate proper switching pulses. The performance of the proposed multilevel inverter is investigated by simulating in MATLAB/Simulink environment. The experimental implementation for proposed 15-level symmetric and 33-level asymmetric structures validates the correctness of simulation results.
As one of the key components of electrical systems, inverters have experienced great progress in the past decades, and today improving their structure and performance is a challenge for researchers. In this paper, a new multilevel converter is introduced and then, the cascaded structure is presented based on a series of introduced multilevel converter. In order to show the benefits of the proposed topology, a comprehensive comparison with the recent multilevel converters has been performed. The proposed structure requires a minimum number of power switches for the same number of levels as compared to the current structures. Also, the total blocking voltage of switches is lower than other topologies. The proposed topology can be used in medium and high voltage applications with fewer switches and less cost. In order to evaluate the performance of the proposed topology, simulation studies have been carried out through Matlab/Simulink and simulation results are presented. Keywords-Multilevel inverter (MLI), Number of reduced devices, Reduced total blocking voltage (TBV)
In this paper, a new multilevel inverter is designed to improve the power and voltage quality, which contains a lesser number of switches in the specified voltage levels. The proposed inverter includes power electronic devices such as switches and diode, and DC inputs. In the proposed structure, considering a basic cell including a DC source, a power switch and a diode, two levels are added to the output levels of the base structure. In the proposed structure, two levels will be added to the output voltage, simply by adding a switch, which results in reduction of the number of power switches compared to classical topologies and similar studies. The proposed topology performance principles are illustrated with a single-phase, nine-level inverter. This topology is studied through simulations in Matlab/Simulink environment. The results of comparing the proposed structure with the classical topology and similar topologies reveal that the proposed structure is superior to previous versions in terms of number of switches, number of drivers, and amount of total blocking voltage.
Inverters as one of the most important elements of power systems have been profoundly developed in recent decades and their performance has attracted researches in control and structure point of view. In this paper, a novel structure based on switch-diode-source cell is proposed for multilevel converter that is capable bidirectional feeding. The proposed structure is presented for symmetrical mode and the number of power electronic devices is decreased in comparison with similar works. Considering recent proposed symmetrical structures, the proposed structure has superior condition in terms of semiconductor switches and drivers count as well as switching loss. Also, Total Blocked Voltage (TBV) of the proposed converter is compared with conventional and novel symmetrical converters. Then, switch costs of the proposed converter is compared with structure that its TBV is the lowest. The performance of the proposed symmetrical seven-level converter is analyzed and simulated in MATLAB/Simulink for both PWM and selective harmonic elimination switching methods. Not only the results are desirable, but also the experimental results of laboratory prototype validate the simulation results.
Multilevel Inverters are a new family of converters for dc-ac conversion for the medium and high voltage and power applications. In this paper, two new topologies for the staircase output voltage generations have been proposed with lesser number of switch requirement. The first topology requires three dc voltage sources and ten switches to synthesize 15 levels across the load. The extension of the first topology has been proposed as the second topology which consist of four dc voltage sources and 12 switches to achieve 25 levels at the output. Both topologies, apart from having lesser switch count exhibit the merits in terms of reduced voltage stresses across the switches. In addition, a detailed comparative study of both topologies has been presented in the paper to demonstrate the features of the proposed topologies. Finally, several experimental results have been included in the paper to validate the performances of the proposed topologies with different loading condition and dynamic changes in load and modulation indexes.
Multilevel inverters are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single phase cascaded multilevel inverter topology is suggested in this paper. The proposed multilevel inverter topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity, while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable multilevel inverter topologies to prove the superiority of the proposed structure. Selective harmonic elimination (SHE) pulse width modulation (PWM) technique is used to produce the pulses for switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and the cascading of two such units to achieve 71 levels at the output.
In this paper, a new sub-multilevel converter is introduced firstly. Then, the cascaded structure based on the series connection of proposed sub-multilevel converters is presented. The proposed cascade topology can generate all possible levels at output voltage waveform. In order to show the advantages of presented topology, the comparison results with recently proposed multilevel converters are provided. According to the comparison results, it is indicated that the proposed structure requires the least number of power switches and dc sources. Also, the total blocked voltage by the switches and power losses of proposed cascade topology is less than other topologies. The presented topology can be used in high voltage applications. In order to verify the performance of presented topology, the experimental and simulation works are provided.
Inverters, as one of the key components of electrical systems, have experienced a great evolution in the last decade, and their performance improvement is a challenge even today, leading to many researches on topologies and control schemes. This study introduces a new multilevel converter topology which is able to supply bidirectional current loads. The proposed structure has fewer power electronic devices such as power switches, driver circuits, power diodes, and DC voltage sources and, can be designed in both symmetric and asymmetric structures. In order to increase the number of output levels and the proposed basic unit development, modular expansion or cascading methods can be used. This study demonstrates that the aforementioned methods have the best results in asymmetric and symmetric structures of the proposed topology, respectively. The comparison between the proposed converter and some previous topologies shows that it has better conditions with respect to the used semiconductor count, switching and conduction losses, and total blocking voltage. The operation and performance of the proposed multi-level converter have been ascertained through simulations and verified experimentally for a single-phase symmetric thirty-one-level inverter which shows the proposed converter's ability in smooth sinusoidal output voltage generation with minimum total harmonic distortion.
Inverters as one of the most important elements of power systems have been profoundly developed in recent decades and their performance has attracted researches in control and structure point of view. In this paper, a novel bidirectional structure is proposed for multilevel converter in order to reduction the switch count and total converter cost. This structure contains DC sources, power switches and power diodes. The proposed structure is presented for symmetrical mode and the number of power electronic devices is decreased in comparison with similar works. Considering recent proposed symmetrical structures, the proposed structure has superior condition in terms of semiconductor switches as well as converter cost. The performance of the proposed single phase symmetrical eleven-level converter is analyzed and simulated in MATLAB/Simulink for both PWM and selective harmonic elimination switching methods. Not only the results are desirable, but also the experimental results of laboratory prototype validate the simulation results.
In this paper, a new multilevel inverter is designed to improve the power and voltage quality, which contains a lesser number of switches in the specified voltage levels. The proposed inverter includes power electronic devices such as switches and diode, and DC inputs. In the proposed structure, considering a basic cell including a DC source, a power switch and a diode, two levels are added to the output levels of the base structure. In the proposed structure, two levels will be added to the output voltage, simply by adding a switch, which results in reduction of the number of power switches compared to classical topologies and similar studies. The proposed topology performance principles are illustrated with a single-phase, nine-level inverter. This topology is studied through simulations in Matlab/Simulink environment. The results of comparing the proposed structure with the classical topology and similar topologies reveal that the proposed structure is superior to previous versions in terms of number of switches, number of drivers, and amount of total blocking voltage.
In this paper, a multilevel inverter has been designed and improved in order to lower the number of switching devices, especially when the number of level of the output power is large. The input to the inverter comes from internal direct current (DC) resources which are interconnected via the power circuit breaker. Compared to the classical topologies and similar designs, the proposed method needs lower number of switching device to provide the same power levels at the output. As a precursor, we have drawn the desired topology for a 9-level power level. The procedure can be completed using switching by a phase shift keying techniques, which in addition, make practical output power with higher number of levels. The proposed topology has been tested against topologies of the power class 1 and/or similar classes, based on the simulations in the MATLAB/Simulink environment. The results of the simulation deemed to be promising for future networks.
This research implements and compares a symmetric hybridised cascaded multilevel inverter and an asymmetric multilevel inverter utilizing a switched capacitor unit for 17 level inverters. The symmetric hybridised multilevel inverter topology consists of a modified H - bridge inverter which results in an increase in the output voltage to 5 level from the 3 level by using a bi-directional switch at the midpoint of a dual input DC source. In the proposed asymmetric multilevel inverter DC sources are replaced with switched capacitor unit which in turn boosts the output voltage and produces twice the voltage levels at the loads. The proposed topology with staircase modulation technique has been verified using MATLABSIMULINK and the results are experimentally executed with prototype models, which are interfaced with dSPACE RTI 1104. The results of the proposed topologies are experimentally obtained for steady state and the performance of the same is tested under different resistive and inductive load disturbance conditions. The results substantiate that these multilevel inverter topologies are better stabilized during load disturbance conditions with low THD, a lesser number of switches, increased output voltage levels and these topologies well suit for renewable energy applications.
in this paper, a new cascade switch-ladder
multilevel inverter topology is presented which can
generate a large number of output voltage levels. Firstly, a
fundamental switch-ladder multilevel inverter structure is
described. Then, the structure of recommended cascade
topology based on series connection of fundamental
switch-ladder topologies is presented. To generate
maximum number of levels with minimum number of
switching elements, dc sources and voltage on switches,
the proposed cascade topology is optimized. Comparison
results prove that the presented cascade topology
requires fewer numbers of components. Also, the value of
voltage rating on switches is less than other structures.
Experimental results for two topologies are analyzed to
verify the performance of proposed topology.
The study develops a new topology for a single phase cascaded H-bridge multilevel inverter (CHBMLI) with a focus to reduce the number of power switching devices in the path for the flow of current. The philosophy combines an array of series connected voltage sources on either side of an H-bridge inverter to derive the new configuration for the MLI. It allows a multicarrier pulse width modulation approach to the process of generating the pulses for synthesising the PWM output voltage. The use of a smaller number of switches to reach the output voltage show cases the ability of the modular architecture to expand the scope of the CHBMLI. The architecture of a field programmable gate array fosters to realise its implementation and validate the simulated results over a range of modulation indices. The performance draws a new directive in the choice of a particular topology for the MLI to suit applications in the real world.
This paper presents a new E-type module for asymmetrical multilevel inverters (MLIs) with reduced components. Each module produces 13 levels with four unequal dc sources and 10 switches. The design of the proposed module makes some preferable features with a better quality than similar modules such as the low number of semiconductors and dc sources and low switching frequency. Also, this module is able to create a negative level without any additional circuit such as an H-bridge, which causes reduction of voltage stress on switches. Cascade connection of the proposed structure leads to a modular topology with more levels and higher voltages. Selective harmonics elimination pulse width modulation (SHE-PWM) scheme is used to achieve high-quality output voltage with lower harmonics. MATLAB simulations and practical results are presented to validate the proposed module good performance. Module output voltage satisfies harmonics standard (IEEE519) without any filter in output.
In this paper, an advanced configuration for symmetric multilevel voltage source inverter is proposed. The authority of the proposed inverter versus the conventional cascaded H-bridge inverter and the most recently introduced ones, is verified with provided comparisons. The proposed inverter is able to generate the desired voltage levels using a lower number of circuit devices including power semi-conductor switches and related gate driver circuits of switches. As a result, the total cost is considerably reduced and the control scheme gets simpler. Moreover, reduced amount of on-state switches in the suggested configuration decreases voltage drops. And power losses are diminished, as well. The given simulation results confirms the feasibility of the proposed configuration. Also, to approve the practicability of the proposed inverter, a prototype of the proposed topology has been implemented. Finally simulation and experimental results are compared with each other and the provided comparison shows that the obtained results are in good agreements.
A New General Multilevel Converter Topology Based on Cascaded Connection of Sub-Multilevel Units with Reduced Switching Components, DC Sources and Blocked Voltage by Switches
- R S Alishah
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R. S. Alishah, S. H. Hosseini, E. Babaaei and M. Sabahi, "A New General
Multilevel Converter Topology Based on Cascaded Connection of Sub-Multilevel Units with Reduced Switching Components, DC Sources and
Blocked Voltage by Switches," IEEE Trans. Industrial Electronics, vol.
63, no. 11, pp. 7157-7164, 2016.
Novel Reduced Switch-Count Structure for Symmetric/Asymmetric Cascaded Multilevel Inverter
- A Seifi
- M Hosseinpour
- A Dejamkhooy
- F Ssdaghati