GENERIC COLORIZED JOURNAL, VOL. XX, NO. XX, XXXX 2017 1
Ferroelectric ﬁeld effect transistors as a synapse
for neuromorphic application
M. Lederer, T. K¨
ampfe Member, IEEE, T. Ali, F. M¨
uller, R. Olivo, R. Hoffmann, N. Laleni and K. Seidel
Abstract—In spite of the increasing use of machine
learning techniques, in-memory computing and hardware
has raised interest to accelerate neural network operation.
Hereforth, novel embedded non-volatile memories (eNVM)
for highly scaled technology nodes, like ferroelectric ﬁeld
effect transistors (FeFETs), are heavily studied and very
promising. Furthermore, inference and on-chip learning
can be fostered by further eNVM technology options, such
as multi-bit operation and linear switching. In this article
we present the advantages of hafnium oxide based FeFETs
for such purposes due to its basic three terminal structure,
which allows to selectively activate or deactivate selected
devices as well as tune linearity and dynamic range for
certain applications. Furthermore, we discuss the impact
of the material properties of the ferroelectric layer, the
interface layer thickness and scaling on the device perfor-
mance. Here, we demonstrate good device properties even
for highly scaled devices (100 nm x 100 nm).
Index Terms—ferroelectric, FeFET, hafnium oxide, non-
volatile memory, neuromorphic hardware, synapse
DUE to the von-Neumann bottleneck for memory-
intensive algorithms such as approximate computing the
demand of non-volatile memories has rapidly increased .
New architectures like near- or in-memory computing have
gained much attention and multiple new non-volatile memory
devices, like resistive random access memory (RRAM), phase-
change random access memory (PCRAM) or devices based on
ferroelectric HfO2, e.g. ferroelectric tunnel junctions (FTJs)
or ferroelectric ﬁeld effect transistors (FeFETs), have been
suggested as suitable devices for storing the weight infor-
mation or acting as neuron –. For the implementation
of these devices in large, reliable and power efﬁcient neural
networks, they must satisfy multiple requirements , .
Besides large on/off conductance ratio and symmetric weight
update, recent studies  have highlighted the importance of
device variability, endurance and retention.
This paragraph of the ﬁrst footnote will contain the date on which
you submitted your paper for review. This research was funded by
the ECSEL Joint Undertaking project TEMPO in collaboration with the
European Union’s Horizon 2020 Framework Program for Research and
Innovation (H2020/2014-2020) and National Authorities, under Grant
No. 826655, and by the German Bundesministerium f¨
(BMWi), by the State of Saxony in the frame of the Important Project
of Common European Interest (IPCEI).
M. Lederer, T. K ¨
ampfe, T. Ali, F. M¨
uller, R. Olivo, R. Hoffmann,
N. Laleni and K. Seidel are with the Fraunhofer IPMS, Center Na-
noelectronic Technologies (CNT), Dresden 01109, Germany (e-mail:
As mentioned before, devices based on ferroelectric HfO2
have been suggested as possible candidates , , , –
. Due to its compatibility to complementary-metal-oxide-
semiconductor (CMOS) processes, high coercive ﬁeld and
persistent ferroelectricity for ultra-thin ﬁlms, this material can
easily be integrated in current technology nodes . Non-
volatile memory devices, especially ferroelectric ﬁeld effect
transistors (FeFETs), have been already demonstrated in 28 nm
and 22 nm high-k-metal-gate (HKMG) CMOS technology
nodes , . Hereby, Si- and Zr-doped HfO2(HSO/HZO)
have been widely used , . Furthermore, a multitude
of other dopants, like La, Y, or Al, can be used to stabilize
the ferroelectric phase , as well as stress conﬁgurations,
which promote ferroelectricity even in undoped ﬁlms .
In this article, the main differences between HfO2FeFETs
and common resistive synapses are discussed. Furthermore, the
impact of gate voltage during read-out as well as the signal
sequence on the weight update of the device and inﬂuences of
the device integration in regards of the ferroelectric layer are
elaborated. Finally, ﬁgures of merit with regard of endurance,
retention, and scaling are discussed. Here, good linear behavior
and dynamic range (DR) were demonstrated for a 100 nm x
100 nm device. Thus, demonstrating the advantage of HfO2
based FeFETs for hardware accelerated neural networks and
their readiness for application in current technology.
II. EXPERIMENTAL SECTION
The ferroelectric layers of the FeFETs were produced using
atomic layer deposition (ALD) utilizing chlorine based pre-
cursors with a thickness of 10 nm on SiO2or SiON interface.
For the investigation on layer thickness inﬂuences, 5 nm ﬁlms
were prepared additionally. In case of Si- and Zr-doped HfO2
(HSO and HZO), a cycling ratio of 16:1 and 1:1 was used,
respectively. A 10 nm TiN ﬁlm deposited by physical vapor
deposition (PVD) was used as capping layer. More details on
the full integration ﬂow can be found elsewhere . The
highly scaled embedded non-volatile (eNVM) devices were
produced by using a non-invasive eNVM process . For
the polarization hysteresis of the ferroelectric layer, a 10 nm
bottom TiN electrode was deposited via ALD, followed by
the aforementioned deposition of HSO or HZO. The layer
was then capped by a 10 nm PVD TiN top electrode and
crystallized by rapid thermal annealing at 800◦C. Capacitor
structures were formed by sputtering Ti/Pt using a shadow
mask and subsequent wet etch.
For electrical analysis was conducted utilizing an automated
waferprober and precision semiconductor analyzer. Drain volt-
2 GENERIC COLORIZED JOURNAL, VOL. XX, NO. XX, XXXX 2017
Fig. 1. Schematic layout of a two terminal (a) and three terminal (b) device using a ferroelectric layer. Different remanent polarization states of
a ferroelectric ﬁlm can be addressed by returning at a certain voltage in a triangular waveform (c). FeFETs (three terminal device) can be poled
almost continues by pulsing between the two extreme states (d). A possible crossbar layout using FeFETs is presented in (e).
age was set to 100 mV for all measurements. Pulse sequences
with amplitudes ranging from 2.5 V to 4.5 V and widths from
50 ns to 300 ns (10 ns steps) were tested. The signal inves-
tigation was carried out on devices with a width and length
of 25 µm each. Electrical characterization for investigating
dopant, pulse sequences with varying width (50 ns to 300 ns)
were used with an amplitude of 3.5 V and -4 V for potentiation
and depression, respectively. For investigating the thickness
inﬂuence, the amplitudes were increased to 4 V and -4.5V,
respectively. Devices under test had a width of 20 µm and
length of 15 µm.
Retention measurements for the intermediate states were
performed by setting the state using a pulse of varying
amplitude and measuring transfer characteristics after certain
amounts of time. For cycle-to-cycle variability, a pulse train
with varying amplitude (from 2.5 V to 4 V for program and
from -3 V to -4.5 V for erase with a width of 100 ns) was used
repeating up to 30 times on a FeFET with width and length
dimensions of 10 µm each. For investigating the device-to-
device variability, 20 devices with a channel width and length
of 5 µm each were measured using a pulse sequence with
varying amplitude (from -3 V to -4.55 V with a width of
III. RESULTS AND DISCUSSION
Ferroelectric HfO2can be used in two different design
schemes for embedded non-volatile memories. Similar to
resistive memories, it can be used in a two terminal device
conﬁguration (see Figure 1a). This design concept is usu-
ally applied by connecting the ferroelectric capacitor to the
drain of a select transistor in conventional ferroelectric RAM
(FeRAM). This concept results in a destructive read-out of
the polarization . Applying this two terminal device in
a resistive crossbar does not promise good properties, as the
tunnel electroresistance (TER) shift due to the local electric
ﬁeld resulting from the polarization state as in ferroelectric
tunnel junctions (FTJs) is very low and leakage current is
likely to deteriorate the material.
An alternative structure is the FeFET, which is a three
terminal device. Here, the ferroelectric material is integrated
in the gate stack of a ﬁeld effect transistor (see Figure 1b). An
equivalent device can be formed, by connecting a ferroelectric
capacitor to the gate contact of a transistor, as used for
back-end of line (BEoL) integration . A three terminal
device offers many advantages over two terminal devices.
Firstly, three terminal conﬁguration enables a decoupling of
writing and reading paths. Secondly, the gate contact allows
the deactivation of selected devices as well as the application
of certain inhibit voltages for selective programming in an
array conﬁguration. Thirdly, due to a capacitive coupling of the
polarization state and the surface potential of the channel, high
on/off ratios can be achieved. These and other functionalities
resulting from the third terminal, will be discussed later on.
Furthermore, due to the FeFETs similarity to high-k metal
gate transistors, these devices can be easily co-integrated into
highly scaled technology nodes .
Stable intermediate states, which are necessary for
e.g. multi-bit precision based hardware accelerated neural-
networks, can be formed by different polarization states of the
ferroelectric material . While the unit cell allows only a
very limited and ﬁnite number of orientations of the polariza-
tion axis with a ﬁxed remanent polarization, domain structure
as well as differences in the crystallographic orientation of
grains enable an almost continuous number of these states.
Figure 1c shows the different remanent polarization states,
which are achieved by applying different voltage amplitudes
using a triangular wave form to a ferroelectric capacitor.
As illustrated in Figure 1d, the polarization states in a
AUTHOR et al.: PREPARATION OF PAPERS FOR IEEE TRANSACTIONS AND JOURNALS (FEBRUARY 2017) 3
Fig. 2. Alteration in the current distribution of the intermediate states in dependence of the gate voltage for FeFETs with a 10 nm HSO layer
and SiO2interface layer. (a) shows the transfer characteristics of the intermediate states. By extracting the currents for certain gate voltages and
normalizing them to the local current maximum, the resulting current state distributions for depression (b) can be visualized, analogously potentiation
can be analyzed. As shown in (b), the three types of sequences result in curves being very linear in case of seq. 2 (at -3.5 V and 50 ns to 250 ns
with 10 ns increment) and seq. 3 (at 100 ns and -3 V to -4.5 V with 0.05 V increment), whereas a quite non-linear behavior is found seq. 1 (at
-4.5 V and 100 ns). For quantitative analysis, a non-linearity coefﬁcient ,  was introduced. Respective curves for certain non-linearity values
are shown in (c). The opposing trend of linearity in dependence of the gate voltage (VG) can be seen clearly in for potentiation and depression.
Furthermore, dynamic range shows a gate voltage dependence (d), here shown for sequence 2 with pulse amplitudes of 3.5 V/-4 V. Reducing the
pulse width (e) or amplitude (f) can improve the linearity.
FeFET can be addressed by applying multiple pulses, e.g. of
the same shape. By changing the polarity of the pulse, the
polarization can be inverted. Nevertheless, the device can also
be fully programmed or erased by applying a single pulse with
a sufﬁcient amplitude.
For integrating this device in a crossbar structure, an ad-
ditional line connected to the gate terminal of the devices is
necessary. A possible crossbar schematic is shown in Figure
1e. Consequently, the write signal, which is addressed to the
gate terminal, and the input signal, addressed to the source
terminal, during read operation are physically separated and
A. Impact of gate voltage on pulse-switching
Furthermore, the intermediate states in a FeFET can be
addressed by applying rectangular pulse sequences. When
measuring transfer characteristics after each pulse, an almost
continuous shift in the threshold voltage over a broad range
can be observed (see Figure 2a). From this, a high dynamic
range greater than four orders of magnitude, limited only to the
transistor characteristics at suitable VG, as well as the ability
to switch off devices completely for low enough gate voltages
can be deduced.
Due to the third terminal, linearity and dynamic range are
inﬂuenced both by the gate voltage (VG) during readout and
by the signal sequence shape applied during write operation.
Previously, three different pulse schemes (see Figure 2b) were
discussed to program the states in a multi-level memory cell
. The easiest one (sequence 1) is the repetition of the same
pulse multiple times. Alternatively, the pulse width (sequence
2) or the pulse amplitude (sequence 3) can be increased with
the pulse count.
The latter is in terms of theory straightforward for fer-
roelectrics, as only domains with an effective coercive ﬁeld
smaller or equal to the voltage drop across the ferroelectric can
switch, like discussed for Figure 1c. The reason sequence 2
can be used for multi-state switching is attributed to nucleation
limited switching (NLS) present in hafnium oxide based ﬁlms
On the contrary, sequence 1 is not expected to result in
a very linear behavior. As the pulse time and amplitude
remain constant, neither NLS nor classical switching propose
the addressability of multiple states. Origins for addressing
different states with this sequence could be explained by
changes in the voltage drop across the ferroelectric due to the
changes in the polarization and therefore local electrical ﬁeld.
On the other hand, a neuron like integrate and ﬁre scheme
was reported in literature for seq. 1 and has been referred to
as accumulated switching .
As shown for depression, the three sequences (with com-
parable signal parameters) reveal a clear trend to more linear
curves for seq. 1 to 3 at a gate voltage of 0.8 V (see Figure
2b). In order to quantitatively compare the measured behavior,
a ﬁtting model proposed by Yu et al. based on the equations 1
and 2, where P is the pulse number and A, B the ﬁt parameters,
was used to extract a non-linearity coefﬁcient α, .
Additionally, as it can be already deduced from Figure 2a,
4 GENERIC COLORIZED JOURNAL, VOL. XX, NO. XX, XXXX 2017
changes in the current distribution of the intermediate states
will differ in dependence of the gate voltage due to the
nonlinear behavior of the transfer characteristic.
(A+ 0.162) (2)
As shown in Figure 2c for seq. 1, the ﬁtting of each
distribution results in clear dependence of linearity on the gate
voltage. Here, potentiation and depression show very contrary
trends, which is a result of the asymmetric switching behavior
of FeFETs, regarding programming and erasing, combined
with the shape of transfer characteristics. While potentiation
shows an increase of non-linearity with higher gate voltages,
depression shows strong reduction. In both cases, values tend
to saturate for higher gate voltages. Similar trends are observed
for the other sequences.
Combined with the average conductance change and on/off
ratio (see Figure 2d), it allows to optimize the operating
conditions of the crossbar for a speciﬁc neural-network ap-
plication. Either it can be optimized for a maximum of on/off
ratio by choosing an appropriate gate voltage, or for a more
symmetric behavior. Furthermore, a change in the threshold
voltage targeting allows to further tune the device.
As already depicted in Figure 2e, this behavior can be
further tuned by adapting the pulse’s amplitude and width.
In contrast to seq. 1, seq. 2 and seq. 3 can only modulate am-
plitude or width, respectively. As shown in Figure 2e, shorter
pulses result in an increase of linearity for potentiation and
depression, with changes being more pronounced in the latter.
Analogously, a lower amplitude shifts also both directions to a
lower non-linearity coefﬁcient (see Figure 2f). This trend has
been found consistent for all three sequences. Thus allowing to
achieve also low non-linearity in seq. 1 based pulse schemes.
Consequently, improving the signal for high writing speed
as well as for low power consumption falls in line with the
optimization for a more linear behavior. Furthermore, a high
dynamic range larger than three magnitudes can be achieved
by adapting gate voltage, substrate doping and writing signal.
Power consumption during write operation is estimated by
simulation to be in a range of 10 fJ to 6 fJ for pulse
amplitudes in the range of 4 V to 2 V, respectively. This is
signiﬁcantly lower compared to RRAM and PCRAM, with a
power consumption of around 0.1 pJ and 10 pJ, respectively
. As the requirements for on-chip training and interference
are quite different, the implications for those two are discussed
separately in the following paragraphs.
As the linearity of writing plays a reduced role in pure
interference mode, the focus lies here on dynamic range.
Therefore, devices should be optimized in the gate voltage for
the maximum in on/off ratio. Additionally the write signals can
be improved for increased on/off ratio, even if this results in
a slight decreases in linearity. Furthermore, the devices can
be operated in unipolar mode, if this improves the ﬁgures
of merit. Due to the absence of on-chip training in pure
interference mode, the requirements on variability of the
devices also increase.
On the contrary, the requirements on linearity and symmetry
become much more stringent, if on-chip training is included.
Therefore, the long term potentiation (LTP) and depression
(LTD) signals should be optimized for symmetry, while still
having a linear behavior. Consequently, bipolar mode should
be used. Dynamic range is still not negligible, as interference
will be performed afterwards. The requirements on variability
become more loose, as the training will adapt the weights
depending on the device properties. Regarding the writing
sequence, seq. 1 would be favorable as it simpliﬁes the signal
circuits. Seq. 2 should also be possible to integrate in an easy
manner, thus enabling stronger improvements on the Figure of
merits. On the contrary, seq. 3 is expected to be quite difﬁcult
to integrate due to changing voltages.
To judge whether the multi-bit states of FeFET technology
are complying with the requirements of implementation into
resistive crossbars for neural netowrk applications, additional
Figures of merit in context of reliability have to be taken into
account. As seen in Figure 3a, retention measurements of the
intermediate states were conducted up to 5×103s. We observe,
that after a short initial relaxation, the intermediate states
retain stable. This initial relaxation originates from electron
detrapping, which is especially pronounced and takes slightly
longer for the high current state due to more electron trapping
during the larger programming pulse.
Furthermore, we observed very good cycle-to-cycle variabil-
ity (see Figure 3b). Additionally, results suggest a good device-
to-device variability, which is mainly inﬂuenced by saturation
current variability and therefore not inherent to the switching
behavior of the ferroelectric layer, as can be seen in Figure 3c.
The resuts in 3b furthermore suggest a high symmetry between
the potentiation and depression branch while preserving a
high linearity, which eases technical realizations. A ratio of
minimum and maximum resistance of >103can be achieved,
as well as linearly switched 32 states (5-bit). The device-to-
device variation was investigated and only a small variation
was observed, the cycle-to-cycle-variation is limited as was
shown in 3b. The endurance is furthermore expected to be
improved upon sub-loop operation and hence even could
comply with on-chip learning needs which are expected to
be in the order of 109cycles.
B. Cell design considerations
The weight update behavior is further inﬂuenced by the
device integration of the FeFET gate stack, consisting of the
gate material, interface layer, ferroelectric and top electrode.
Inﬂuences of different materials, thicknesses, and process
related parameters on the device properties in respect to
binary operation have already been addressed elsewhere ,
–. Here, inﬂuences of the material properties, layer
thickness as well as impacts resulting from scaling on the
analog switching properties of the device will be discussed in
the following paragraphs.
First, the impact of different dopants on the device were
investigated using HSO and HZO. Dynamic hysteresis mea-
surements of these two materials already show strong dif-
ference (see Figure 4a). While the HSO shows a higher
AUTHOR et al.: PREPARATION OF PAPERS FOR IEEE TRANSACTIONS AND JOURNALS (FEBRUARY 2017) 5
Fig. 3. Reliability of FeFETs in terms of synaptic devices. Retention measurements of intermediate states (a) in HSO SiO2FeFETs indicate very
stable states up to 105s. Furthermore, very linear and stable operation for repeated cycles is found (b) for this material stack, thus having a very
low cycle-to-cycle variability. Comparison of 20 devices (HZO FeFETs with SiON interface) further suggests low device-to-device variability (c).
Fig. 4. Differences between HZO and HSO based devices with SiON interface and impact of scaling. Polarization hysteresis (a) shows lower
coercive ﬁeld but higher remanent polarization for HSO. 10 nm FeFETs based on HZO show lower nonlinearity coefﬁcient (b) compared to HSO
based devices with a ﬁlm thickness of 10 nm. However, the dynamic range (c) of HSO based devices is higher. Impact of thickness scaling of HZO
SiON FeFETs on the nonlinearity coefﬁcient is shown in (d). Intermediate states (e) are still observable in highly scaled HSO devices (100nm x
100nm) using varying amplitudes from -2 V to -4 V (0.05 V increment) at 200 ns. Furthermore, good linearity is achievable (f).
remanent polarization (PR), the HZO ﬁlm shows a higher
coercive ﬁeld (Ec) with a broader distribution. Consequently,
differences in the non-linearity coefﬁcient as well as on/off
ratio are observable (see Figure 4b and 4c, respectively).
The lower non-linearity is in very good agreement with the
expectations, as the ratio of signal amplitude to coercive ﬁeld
(Vmax/Ec∗dF E ) is much lower. Furthermore, the broader
Ecdistribution supports a more pronounced subloop behavior.
The resulting drawback on the other hand is the reduced on/off
ratio, resulting analogously from the Vmax/Ec∗dF E ratio.
This can be of course counteracted by increasing the applied
voltage. This would also result in utilizing a larger portion
of the memory window, which is expected to be larger for
HZO devices . Consequently, HZO devices would enable
a larger dynamic range and better non-linearity along the
drawback of increased voltage amplitudes during LTP/LTD.
The reduced dynamic range of HSO FeFETs with SiON
interface (Fig. 4c) compared to HSO devices with SiO2
interface (Fig. 2d) is originates from the difference in the
voltage divider resulting from the interface and ferroelectric
capacitance, thus changing the electric ﬁeld drop across the
ferroelectric layer for identical pulse conditions.
Changes to a larger thickness of the ferroelectric layer result
in a stretching of the transfer characteristics due to the change
in electrical ﬁeld across the ferroelectric and semiconductor.
Consequently, a stretching of the characteristic curves for non-
linearity (see Figure 4d) and dynamic range.
Furthermore, a strong impact with scaling to very small de-
vice areas is expected, as the total amount of grains inside the
layer decreases drastically . Nevertheless, a high number
of intermediate states can be observed in devices as small as
100x100 nm2(see Figure 4e). Furthermore, very linear and
analog like switching can be observed while still exhibiting
a high dynamic range, as seen in Figure 4f. Additionally,
zero width domain walls have been suggested to exist in
ferroelectric hafnium oxide due to ﬂat phonon bands and
6 GENERIC COLORIZED JOURNAL, VOL. XX, NO. XX, XXXX 2017
thus enabling domain sizes as small as single unit cells .
This stresses the possibility of analog operating FeFETs even
in strongly scaled devices and further optimizations in the
material processing for small grain sizes or orientation control
should improve this behavior.
In summary, we demonstrated that hafnium oxide based
FeFETs offer a versatile device, which can easily be optimized
for speciﬁc applications like hardware accelerated neural-
networks by simply changing signals or the gate voltage.
Furthermore, by adapting the pulse scheme, not only seq.
3 (voltage variation) but also seq. 2 (pulse width variation)
and seq. 1 (identical pulses) can achieve a very linear current
distribution of the addressed states. Due to the third terminal it
is furthermore possible to deactivate selected devices, allowing
very dense crossbars, as only 1T cells are required. The power
consumption of these devices are also very low due to the
large on/off ratio and low read currents. In point of design
considerations, material improvements to larger memory win-
dows or a less steep slope at Ec, resembling a broader domain
orientation distribution, were demonstrated as being favorable.
Furthermore, smaller grains are preferable for further device
scaling. Consequently, microstructure engineering of grain size
and crystallographic orientation will be of major importance
for ferroelectric synaptic devices. In addition, changes in the
layer thickness of the ferroelectric ﬁlm allow to improve the
device for speciﬁc applications.
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