Conference Paper

Parallel, True Random Number Generator (P-TRNG): Using Parallelism for Fast True Random Number Generation in Hardware

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... There are several other approaches for generating random numbers (Bhattacharjee and Das, 2022;L'ecuyer, 2004;Datcu et al., 2020;Dridi et al., 2023;Tutueva et al., 2021;Levina et al., 2022;Gupta and Chauhan, 2021;Arciuolo and Elleithy, 2021;Pazos et al., 2023). These approaches either need dedicated hardware or complicated processing which make them inappropriate for microcontroller implementation. ...
Article
Microcontrollers are widely used in everyday applications as a result of their cheap and versatile nature. Recent advances in the fields of Internet of Things and Artificial Intelligence further increased the application areas of microcontrollers. A major problem of microcontroller applications is the generation of random numbers with the limited hardware resources available. Existing methods which use the jitter in different clock sources or incorporate dedicated random number generators either lack operation speed or need addition of expensive hardware components. This paper uses the avalanche breakdown uncertainty in a transistor to generate random numbers on a microcontroller platform. In the context of this study, a hardware platform is designed to generate random numbers and generated data is analyzed through statistical methods. The presented solution is quite fast and cost effective in terms of both design budget and hardware resources.
... Many RNGs are based on physical processes, such as thermal noise, radioactive decay, and other physical phenomena [4], [5], [8]. True RNGs have good entropy and can generate high-quality random numbers. ...
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Random number generation (RNG) is a crucial element in security protocols, and its performance and reliability are critical for the safety and integrity of digital systems. This is especially true in 5G networks with many devices with low entropy sources. This paper proposes 5G-SRNG, an end-to-end random number generation solution for devices with low entropy sources in 5G networks. Compared to traditional RNG methods, the 5G-SRNG relies on hardware or software random number generators, using 5G spectral information, such as from spectrum-sensing or a spectrum-aware feedback mechanism, as a source of entropy. The proposed algorithm is experimentally verified, and its performance is analysed by simulating a realistic 5G network environment. Results show that 5G-SRNG outperforms existing RNG in all aspects, including randomness, partial correlation and power, making it suitable for 5G network deployments.
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Unpredictable true random numbers are required in security technology fields such as information encryption, key generation, mask generation for anti-side-channel analysis, algorithm initialization, etc. At present, the true random number generator (TRNG) is not enough to provide fast random bits by low-speed bits generation. Therefore, it is necessary to design a faster TRNG. This work presents an ultra-compact TRNG with high throughput based on a novel extendable dual-ring oscillator (DRO). Owing to multiple bits output per cycle in DRO can be used to obtain the original random sequence, the proposed DRO achieves a maximum resource utilization to build a more efficient TRNG, compared with the conventional TRNG system based on ring oscillator (RO), which only has a single output and needs to build multiple groups of ring oscillators. TRNG based on the 2-bit DRO and its 8-bit derivative structure has been verified on Xilinx Artix-7 and Kintex-7 FPGA under the automatic layout and routing and has achieved a throughput of 550Mbps and 1100Mbps respectively. Moreover, in terms of throughput performance over operating frequency, hardware consumption, and entropy, the proposed scheme has obvious advantages. Finally, the generated sequences show good randomness in the test of NIST SP800-22 and Dieharder test suite and pass the entropy estimation test kit NIST SP800-90B and AIS-31.
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In the Internet of Things era, security concerns may require a cryptography system in every connected device. True random number generators (TRNGs) are preferred instead of pseudo-random number generators in the cryptography systems to achieve a higher level of security. For on-chip applications, we seek scalable and CMOS-compatible devices and designs for TRNGs. In this article, the stochastic behavior of the spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized for the source of randomness. However, variations and correlations exist in MTJs due to fabrication limitations, so TRNG designs based on a single MTJ have to be post-processed or tracked in real time to ensure an acceptable level of randomness. Two novel designs are proposed in this article which can produce random sequences with high variation-resilience. The first design uses a parallel structure to minimize variation effects, and the second design leverages the symmetry of an MTJ-pair to take advantage of any correlations. Moreover, a universal circuit for quality improvement is proposed and it can be used with any random number generator. All of the designs are validated in a 28-nm CMOS process by Monte Carlo simulation with a compact model of the MTJ. The National Institute of Standards and Technology (NIST) statistical test suite is used to test the randomness quality of the generated sequences under the scenario of encryption keys in Transport Layer Security or Secure Sockets Layer (TLS/SSL) cryptographic protocol.
Conference Paper
Random number generators are an essential part of cryptographic systems. For the highest level of security, true random number generators (TRNG) are needed instead of pseudo-random number generators. In this paper, the stochastic behavior of the spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized to produce a TRNG design. A parallel structure with multiple MTJs is proposed that minimizes device variation effects. The design is validated in a 28-nm CMOS process with Monte Carlo simulation using a compact model of the MTJ. The National Institute of Standards and Technology (NIST) statistical test suite is used to verify the randomness quality when generating encryption keys for the Transport Layer Security or Secure Sockets Layer (TLS/SSL) cryptographic protocol. This design has a generation speed of 177.8 Mbit/s, and an energy of 0.64 pJ is consumed to set up the state in one MTJ.
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This paper presents a new method for creating TRNGs in Xilinx FPGAs. Due to its simplicity and ease of implementation, the design constitutes a valuable alternative to existing methods for creating single-chip TRNGs. Its main advantages are the high throughput, the portability and the low amount of resources it occupies inside the chip. Therefore, it could further extend the use of FPGA chips in cryptography. Our primary source of entropy is a True Dual-Port Block-RAM operating at high frequency, which is used in a special architecture that creates a concurrent write conflict. The paper also describes the practical issues which make it possible to convert that conflict into a strong entropy source. Depending on the users' requirements, it is possible to connect many units of this generator in parallel on a single FPGA device, thus increasing the bit generation throughput up to the Gbps level. The generator has successfully passed the major statistical test batteries.
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