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Parallel, True Random Number Generator (P-TRNG): Using Parallelism for Fast True Random Number Generation in Hardware
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In the Internet of Things era, security concerns may require a cryptography system in every connected device. True random number generators (TRNGs) are preferred instead of pseudo-random number generators in the cryptography systems to achieve a higher level of security. For on-chip applications, we seek scalable and CMOS-compatible devices and designs for TRNGs. In this article, the stochastic behavior of the spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized for the source of randomness. However, variations and correlations exist in MTJs due to fabrication limitations, so TRNG designs based on a single MTJ have to be post-processed or tracked in real time to ensure an acceptable level of randomness. Two novel designs are proposed in this article which can produce random sequences with high variation-resilience. The first design uses a parallel structure to minimize variation effects, and the second design leverages the symmetry of an MTJ-pair to take advantage of any correlations. Moreover, a universal circuit for quality improvement is proposed and it can be used with any random number generator. All of the designs are validated in a 28-nm CMOS process by Monte Carlo simulation with a compact model of the MTJ. The National Institute of Standards and Technology (NIST) statistical test suite is used to test the randomness quality of the generated sequences under the scenario of encryption keys in Transport Layer Security or Secure Sockets Layer (TLS/SSL) cryptographic protocol.
Random number generators are an essential part of cryptographic systems. For the highest level of security, true random number generators (TRNG) are needed instead of pseudo-random number generators. In this paper, the stochastic behavior of the spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized to produce a TRNG design. A parallel structure with multiple MTJs is proposed that minimizes device variation effects. The design is validated in a 28-nm CMOS process with Monte Carlo simulation using a compact model of the MTJ. The National Institute of Standards and Technology (NIST) statistical test suite is used to verify the randomness quality when generating encryption keys for the Transport Layer Security or Secure Sockets Layer (TLS/SSL) cryptographic protocol. This design has a generation speed of 177.8 Mbit/s, and an energy of 0.64 pJ is consumed to set up the state in one MTJ.
This paper presents a new method for creating TRNGs in Xilinx FPGAs. Due to its simplicity and ease of implementation, the design constitutes a valuable alternative to existing methods for creating single-chip TRNGs. Its main advantages are the high throughput, the portability and the low amount of resources it occupies inside the chip. Therefore, it could further extend the use of FPGA chips in cryptography. Our primary source of entropy is a True Dual-Port Block-RAM operating at high frequency, which is used in a special architecture that creates a concurrent write conflict. The paper also describes the practical issues which make it possible to convert that conflict into a strong entropy source. Depending on the users' requirements, it is possible to connect many units of this generator in parallel on a single FPGA device, thus increasing the bit generation throughput up to the Gbps level. The generator has successfully passed the major statistical test batteries.
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