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Abstract This study presents integration of complementary CMOS active feedback low noise amplifier with coplanar waveguide fed patch antenna for Wi‐Fi networks. The LNA design‐I, involves a cascode amplifier followed by active feedback common source amplifier offering wideband impedance matching with lowered parasitic losses. The inductor‐less feedback mechanism is used to nullify noise effect with extended bandwidth in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on agilent's advance design system using 45 nm CMOS process. The noise figure (NF) is approximately 2 dB while the stability factors µ and µ prime are well above 1 dB with IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm2 under dc power supply of 1V while power consumption of 0.8 mW. A CPW fed antenna design‐II, achieves a wide band response similar to the bandwidth of LNA. The size of the fabricated antenna is calculated as 40 x 40 mm2. The peak gain is approximately 4.1 dBi at 3.9 GHz. The codesign‐III, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system integration by reducing overall chip area and offers saving in the effective cost.
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Received: 30 January 2020
Revised: 24 November 2020
Accepted: 25 November 2020
IET Microwaves, Antennas & Propagation
DOI: 10.1049/mia2.12062
Active feedback supported CMOS LNA blended with coplanar
waveguidefed antenna for WiFi networks
Gunjan Mittal Roy
|Santanu Dwari
|Binod Kumar Kanaujia
Sandeep Kumar
|Hanjung Song
JIMS Engineering Management Technical Campus,
Greater Noida, Uttar Pradesh, India
Department of Electronics Engineering, Indian
Institute of Technology IIT(ISM), Dhanbad,
Jharkhand, India
School of Computational and Integrative Sciences,
New Delhi, JNU, India
Department of Electronics and Communication
Engineering, National Institute of Technology
Karnataka, Surathkal, Mangaluru, India
Department of Nanoscience and Engineering,
Centre for Nanomanufacturing, Inje University,
Gimhae, Korea
Sandeep Kumar, Department of Electronics and
Communication Engineering, National Institute of
Technology Karnataka, Surathkal, Mangaluru, India.
This study presents integration of complementary CMOS active feedback low noise
amplier with coplanar waveguide fed patch antenna for WiFi networks. The LNA
designI, involves a cascode amplier followed by active feedback common source
amplier offering wideband impedance matching with lowered parasitic losses. The
inductorless feedback mechanism is used to nullify noise effect with extended bandwidth
in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on
agilent's advance design system using 45 nm CMOS process. The noise gure (NF) is
approximately 2 dB while the stability factors µand µprime are well above 1 dB with
IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm
under dc power supply of 1V
while power consumption of 0.8 mW. A CPW fed antenna designII, achieves a wide
band response similar to the bandwidth of LNA. The size of the fabricated antenna is
calculated as 40 x 40 mm
. The peak gain is approximately 4.1 dBi at 3.9 GHz. The
codesignIII, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a
gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system
integration by reducing overall chip area and offers saving in the effective cost.
The demand and supply rule is applicable in the eld of
research and technology too. The demands of consumers of
technology are fullled by the scientists and researchers by
supplying the upgrading in technology. In the eld of radio
frequency (RF) integrated circuit, the researchers have adopted
new methods and technology to satisfy the escalating technical
hunger of human beings. In wireless communication, the
complementary metal oxide semiconductor (CMOS) low noise
amplier (LNA) with integrated antenna has gained ubiquitous
reputation to serve as a receiver system. The basic criteria of
designing a receiver system are wide bandwidth, high gain,
good impedance matching, high reverse isolation, minimal
noise with good linearity and stability at the cost of lower
power consumption and smallest chip size. Till now, thousands
of researchers have tried to achieve the best results, with lot of
scope for improvement. Various technologies are adopted to
get the optimum results. An LNA must primarily adopt the
noise cancellation technique. It has been done by catering a
two stage differential LNA offering noise gure (NF) of only
1.7 to 2.7 dB with higher power consumption of 13 mW and
low voltage gain of only 16 to 18 dB [1]. For gain consider-
ation, distributed stages have been a trend in the designing of
an LNA. In [2], it is also taken into account by having current
reuse conguration with double transformer coupling tech-
nique. The three common source (CS) stages turn out to be
successful in achieving a peak gain of 31.4 dB. But the setback
observed is RF inductor coupling that gives unreliable fre-
quency stability. However, the other issues like noise and
bulkiness are worth considering. The use of inductor is to be
avoided to eliminate its evident drawbacks. Other techniques
of noise control incorporates dual cross coupling that brings
out NF less than 4.5 dB [3]. Linearity is the other serious issue
that needs a proper attention while synthesizing an LNA.
Thus, a wide band inductorless LNA is designed that offers
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© 2021 The Authors. IET Microwaves, Antennas & Propagation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.
IET Microw. Antennas Propag. 2021;15:537546.
high linearity of 10 dBm in terms of third order intercept point
(IIP3) attained to be 1 dB with compression point of 0 dBm.
The hinder in this approach is the maximum power dissipation
of 30.2 mW [4]. In [5], a special technique of parallel push–
pull design using CMOS circuit is devised to adhere high
noise cancellation and high linearity at the cost of high power
consumption of 20.8 mW and low voltage gain of 13 dB in
the frequency spectrum of 0.1 to 1.6 GHz. The inductive
gain peaking technique popularly adopted choice for noise
cancelling and gain attening, offers the limitation of narrow
bandwidth and use of inductor [6]. The other scheme that
enhances gain performance with wide band, used a negative
capacitance that mitigates the effect of parasitic capacitances
[7]. When designing LNA, the use of active inductor omits
obvious problems encountered by the conventional inductors
[8]. In [9], a multistage LNA is designed using active tunable
inductor to offer a reasonably high gain. Although, the active
inductor has the potential to be a solution to multiple
problems encountered by the conventional one, it needs to
be altered. Thus, the much simpler inductorless technique is
used to make the circuitless complex. In [10], inductorless
LNA with multiple feedback technique is used to achieve the
desired parameters along with least power consumption of
only 2.8 mW. Another low power inductorless LNA design
used common gate active g
boost method, where the power
consumed by LNA is even less that is only 1.32 mW [11]. In
[12], the inductorless LNA is designed using active shunt
feedback technology. It offers the same band as that of [4]
with a maximum gain of 12.3 dB and IIP3 of 10 dBm. In
another low power active shunt feedback approach of an
LNA, a much wider band of interest of 2 to 8 GHz has been
attained with the little compromise in power gain [13].
Another approach of current reuse feed forward noise
cancellation offers the minimum power consumption [14]. In
one more design of current reuse, the concept of inductor
less LNA is incorporated with an active feedback network
(AFB), where the maximum voltage gain of 21.1 dB and IIP3
of 4.7 dBm are attained [15]. Not only this but the inductor
less technology is being adapted to a huge extent such that
even the transconductance g
boost and noise cancelling
techniques exploit it [16]. An LNA design uses a cascode
amplier followed by active feedback inductorless CS
amplier to lower the parasitic losses and achieve wide
impedance matching. The tunable AFB is exploited to yield
the welldened outcomes while being active it offers sig-
nicant amount of gain. The bandwidth achieved is 3.6 GHz
ranging from 2.2 GHz to 5.8 GHz. The coplanar waveguide
(CPW) fed antenna is designed to achieve wide band
response similar to that of LNA. The peak gain is approxi-
mately 4.1 dBi at 3.9 GHz. The codesign receiver system
gives a much wider band of 1.6 to 6 GHz, whereas the gain
of 16.5 dB is acheived at minimum NF of 2.59 dB at 2.06
GHz. The study is organised as follows: Section 2describes
design and performance of LNA. Section 3presents antenna
design and performance. Section 4discusses the blending
approach of LNA with antenna and nally, Section 5briefs
the conclusion.
A lot of research study has been done in the eld of CMOS
LNA. The researchers have the constraints to get the opti-
mised performance out of minimal resources used with less
complexity. The basic designing idea is to keep the desired
results intact with simplied architecture. In the proposed
design of LNA, the complete design involves cascading of a
cascode amplier and a single stage CS amplier along with
AFB network. The cascode network shown in Figure 1(a) is
widely used to design distributed ampliers because of its
capability to satisfy the gain and resistance properties with
good reverse isolation features as compared to a conventional
CS amplier while it does not offer signicantly higher g
However, the bandwidth is restricted due to the internal
capacitive effect of the metal oxide semiconductor (MOS)
devices. The frequency response of the cascode network offers
a low frequency dominant pole at 1
2ΠRiCgs where R
is the gate
resistance of the transistor and high frequency nondominant
pole. The size of CS transistor is used to control the value of
the dominant pole [17]. To compensate the parasitic effect, a
100 fF capacitor is connected between the drain of M
and the
output of the feedback network. Figure 1(b) depicts the
feedback network used to serve multiple purposes including
the gain atness. Here, negative feedback has been exercised to
excel the LNA performance. A negative feedback topology
caters various benets to an amplier behaviour inclusive of
bandwidth enhancement, noise reduction, gain stability
improvement and impedance matching. It can be practiced by
using the traditional passive elements or recently used active
devices. Passive networks can be used comprising only of
resistive or only reactive elements such as LC networks.
The resistive feedback technique provides a wideband
input impedance matching without utilising the extra power in
the feedback path and is preferred due to the small die area
consumption, whereas the LC tuning feedback networks have
their evident limitations but can be used for higher frequency
ranges. The inductorless congurations are preferred as it
reduces the chip size, cost and noise factor. Thus considering
these issues, the AFBs prove themselves to be better per-
formers at the cost of additional power [12]. The integration of
the devices using CMOS technology is a cumbersome process
FIGURE 1 Adopted designs for LNA: (a) cascode cell and (b) CS with
feedback network
since linearity, dynamic range and signaltonoise ratio are
limited by the short channel effect [14]. Thus, the feedback
used here not only enhances the expected features but also it
signicantly contributes to the linearity parameter (IIP3). The
feedback is obtained through the combination of comple-
mentary derivative superposition and active shunt feedback.
The shunt feedback reduces input impedance by a factor of (1
+A), so lower g
is used which in turn enables a lower power
consumption. Figure 2shows the complete proposed sche-
matic of LNA. Here M
and M
form an input stage that is a
cascode amplier which gives high impedance matching due to
reverse isolation and good noise factor with a bandwidth about
three times the conventional amplier. The output of this stage
is coupled to a CS amplier M
to provide a cascade approach
enabling much higher gain. The CS stage is the most widely
used LNA, being simple and traditional. It offers high gain and
other complementary factors of LNA inclusive of decent
bandwidth. Its small channel size yields into downscaling of
the chip size. The output of CS stage is fed back into a negative
feedback loop where the feedback network is active in nature
using MOS devices. This offers all the anticipated benets of
negative feedback in ampliers along with the gain factor.
Transistors M
and M
form an active network to offer gain
and wide band in conjunction with M
forming a folded
network to behave like a feedback network. Figure 3shows the
impedance bandwidth response of LNA. It is mainly inu-
enced by the capacitive effect of the device. For a cascode
amplier, it is considered to be three times to that of con-
ventional amplier as it mitigates the Miller effect to limit the
bandwidth while for a negative shunt feedback amplier, it
elevates by the factor (1 þ|AV|). The proposed LNA ach-
ieved a band that ranges from 2.2 GHz to 5.8 GHz. The
bandwidth of a cascode amplier can be given by Equation (1).
sCgs2 þ2Cgd2ð1Þ
s¼Rsrin2 ð2Þ
where R
is nearly 500 Ω while r
is in the range of 1 to 2 KΩ.
Also C
is about 20 pF and C
is approximately 1 pF. For a
feedback system, it is dened as:
f2¼foð1þ|Av|Þ ð3Þ
where f
is the bandwidth of the open loop system. More
conventionally, it can be put as Equation (4).
2πRCgs3 þC1ð1þAVÞð4Þ
where Ris the output resistance of cascode stage.
The frequency response representation of return loss is
approximated by exploiting a two port Sparameter model
shown in Figure 4. The incoming and outgoing waves at input
and output ports are described by the following equations [18].
pðV1þI1Z0inÞ ð5Þ
pðV1I1Z0inÞ ð6Þ
FIGURE 2 Proposed schematic of LNA
FIGURE 3 Return loss versus frequency
FIGURE 4 General twoport representation of Sparameters
pðV1þI2Z0outÞ ð7Þ
pðV1I2Z0outÞ ð8Þ
where Z
and Z
are characteristic impedances of input and
output ports. These equations have interlinks to block specic
Sparameters in the following manner:
The generalised equation of return loss of LNA in terms of
input and source impedance is considered from [19].
S11 ¼Zin Rs
Zin þRsð11Þ
The return loss in terms of frequency response is given as:
S11 ¼S2þω2
where ω
and Q
are resonance frequency and quality
factor, respectively; dened as:
ðRsþR1Þcgs1 þCdg11þgmRL
Cgs1 þCdg11þgmRL
Figure 5depicts the input impedance of LNA with respect
to frequency. Total input impedance is affected by all the three
active stages of the device which include a cascode stage, gain
cell and the feedback network. The parameters are so chosen
that the input impedance of the LNA is matched with 50 Ω
requirements. The input impedance is determined by the cas-
code stage only given in Equation (15) [20].
gm1 1þScgs1ð15Þ
where g
is the material transconductance of M
while c
the gatetosource junction capacitance. The impedance of
feedback network is given below [16].
Scgd12þcgs4 þcgd5ð16Þ
where cgd12is the gate to drain capacitance of M
and M
. The
effective transconductance of feedback structure and the
output impedance can be calculated as:
Gm4 ¼gm4
1þgm4 ð17Þ
scgs3 ð18Þ
where gds12is draintosource conductance of M
and M
The overall gain of the LNA is determined by the product
of the gains of the cascode amplier and the CS amplier with
feedback network. It is observed that with the increase of
transconductance of the transistors, the gain is improved. Due
to the combined feedback system, the g
factor elevates
resulting into higher gain and reduced power consumption
[15]. Figure 6shows equivalent small signal model of LNA
FIGURE 5 Input impedance variation versus frequency
FIGURE 6 Small signal equivalent model of
used to analyse the gain factor while in Figure 7the gain
performance of LNA is depicted in terms of simulated,
mathematically calculated and measurement done from the
fabricated chip of LNA. It is observed that theoretically, that
the gain is 21.2 dB while the measurement turns out to be 22.5
dB when the other performance factors are taken into
consideration such as parasitic components and noise factors,
these are remarkably good gures. The gain of cascode
amplier is given by the following equation [20].
Av1 ¼gm2ro21þgm1ro1Z2
2ro1 þro2 þro1ro2scgs1þgm1 ð19Þ
The gain of CS amplier with feedback network is acquired
from the following equation [15].
Av2 ¼Gm3 1
Taking Z
>> Z
, the above equation can be simplied as:
Av2 ¼Gm3Z2ð21Þ
By multiplying Equations (19) and (21), the total gain of
LNA is achieved.
From the LNA circuit, it is evident that the main noise
contributors are MOS devices along with the passive resistors. In
order to calculate noise factor, it is more important to assume
some parameters. For example, the output impedance of the
transistors is assumed to be innite, while the bias cur rent source
is assumed to be an ideal one. Only the thermal noise from
transistors ði2
n=Δf ¼4kTγgmÞand resistors ði2
n=Δf ¼4kT=RÞ
is taken into consideration. Here γis noise parameter of the MOS
devices that varies from 2/3 to 2 for short channel devices. The
gate resistance can be ignored [12]. The NF can be determined
from the below mentioned equations [15].
F¼FCascode þFCSamplifier þFRs þFRB ð22Þ
FCascode ¼γM2gmM2
where α¼gm
gdo, while g
is the zero bias transconductance
of the transistor.
FCS ¼γgmcs1þgmcGRs
gmcs¼ ðnþ1ÞgmcGð26Þ
FCS ¼γ
nþ1;where n¼4ð28Þ
Ffeedback ¼γM4gmM4
ð1þgmM4RFÞ2NM5 ð29Þ
F¼1NRS ð30Þ
The above expressions explain the combined effect of NF.
Further studies of these expressions show that it can be
minimised by choosing some factors carefully.
In case of cascode amplier section of LNA, by
increasing αfactor which in turn can be controlled by g
and g
, the NF can be reduced. The effect of R
and R
FIGURE 7 Forward gain variation versus frequency FIGURE 8 Noise gure variation versus frequency
contributes in the noise performance of the device. By
keeping these values low the NF can be improved. Figure 8
shows the performance of LNA in terms of NF with respect
to frequency. It is noted that NF remains almost constant
in the operating band of 2.2 to 5.8 GHz at approximately
2 dB.
Figure 9shows stability factor and thirdorder intercept
point (IIP3) performances with respect to frequency. When the
feedback method is adopted, it is worth considering stability of
the amplier, as it is evident that the incorporation of negative
feedback improves the stability factor. For RF frequency range,
the stability is determined by using Kfactor that depends on
Sparameters. To achieve stability, it is required to have K>1
and Δ <1. Both Kand Δ are given by the equations given
below [12].
K¼1S112S222þS11S22 S12S212
2 │ S12S21 ð32Þ
Δ¼S11S22 S12S21ð33Þ
The stability factor is dependent on gain and reection
coefcients which in turn are derived from the transistor pa-
rameters like g
and r
. By varying these factors along with the
body bias voltage ranges within 1 V, the unconditionally good
stability is achieved for the complete frequency range of
operation as depicted in the simulated performance graph. The
stability factor is only 2.5 dB. The linearity of a circuit is
affected by nonlinear g
of MOS devices. It occurs at the time
of conversion of input voltage into output voltage. Most
commonly, the linearity of LNA is determined by thirdorder
intercept point. The indulgence of feedback in the LNA circuit
yields all the frequency responses which include fundamental
response (H
and F
), secondorder response (H
and F
) and
thirdorder response (H
and F
). The complete effect can be
FIGURE 9 Stability factor and IIP3 variation versus frequency
FIGURE 10 Mu and Muprime versus frequency
FIGURE 11 Die microchip photograph of LNA
IIP3¼ ffiffi
shown in equation given below [15].where R=(1 +H1F1) – 1
is the feedback gain reduction factor. The (W/L) aspect ratio
of all the MOS devices is maintained in a manner so as to keep
the linearity factor in desired range. As depicted graphically the
simulated IIP3 is about 15 dBm. The stability is elaborated by
considering the factors µand µprime plotted in Figure 10
where both have acquired the values greater than 1 for un-
conditionally stable system. Figure 11 shows die microchip
photograph of CMOS active feedback proposed LNA. It is
fabricated using mixed signal TSMC process 45 nm CMOS
technology with all testing pads. The calculated dimensions of
the chip are 0.57 x 0.57 mm
, while dc power consumption is
0.9 mW. Here, BSIM (Barkley short channel IGFET) RF
MOSFET is used with an nchannel substrate for designing
and fabricating the LNA chip. The behavioural performance of
the chip is governed by measuring Sparameters and NF as
depicted in Figures 3, 7 and 8where the results are found to be
quite correlated. The gureofmerit (FoM) of LNA is calcu-
lated to be 111.8. The FoM can be calculated by using relation
given below:
FOM ¼S21½dBX BW ½GHz
PdcðmWÞX½NFmin 1ð35Þ
Table 1summarises about component values while Table 2
gives a comparison of the proposed research work with other
reported works.
The structural design of antenna with its results has been
discussed in this section. A rectangular slotted CPW fed an-
tenna is crafted for its obvious enormous benets. The FR4
substrate with relative permittivity (ε
) of 4.4 and thickness h=
1.6 mm is used with the dimensions of 40 mm x 40 mm. The
antenna design with its dimensions is illustrated in Figure 12(a)
while measurement set up is depicted in Figure 12(b). The
simulation is done on EMAnsoft high frequency structure
simulator (HFSS) v11. The total substrate comprises of a
rectangular radiator with two rectangular slots inside it. The
CPW feeding is used whose dimensions are calculated from
[21] with two partial symmetrical rectangular ground planes.
These ground planes produce capacitive effect in order to
nullify the inductive effect created by the rectangular radiator.
Thus the antenna becomes completely resistive. The outcomes
of CPW feeding are desirable in many ways that is why it is
popularly used in antenna designing. The obvious benets are
its wideband response, minimal losses and ease of fabrication
[22]. The antenna is designed for WiFi network applications in
the band range of 2.2 to 5.8 GHz. The worthy point consid-
ered in this design is that the LNA crafted in the above section
TABLE 1Component values of LNA design
Components Values Components Values
225 pF RL 200 Ω
1 Pf I 5 mA
1 Pf M
(W/L, g
) (0.001/0.045 µm, 0.0091S)
175 KΩ M
(W/L, g
) (225/0.045 µm, 0.042S)
175 Ω M
(W/L, g
) (325/0.045 µm, 0.016S)
175 KΩ M
(W/L, g
) (525/0.045 µm, 0.012S)
175 Ω M
(W/L, g
5) (0.001/0.045 µm, 0.0091S)
1K Ω M
(W/L, gm6) (225/0.045 µm, 0.042S)
TABLE 2Performance comparison of LNA with other
Design parameters [6] [8] [11] [13] [14] Present work
Technology (nm) 65 65 65 180 180 45
Frequency (GHz) 1–11 0.3–4.4 0.1–4.3 2–8 2–5 2.2–5.8
NF (dB) 2.5–3 3–4.4 2.8–4 2.9–3.3 6–8 2
| (dB) 14–17 26.7 21.2 11 13 22.5
IIP3 (dBm) >‐8 14.2 –7.7 +14 ‐ +15
Pdc (mW) 11.3 13.9 0.96 7 1.8 0.8
FoM 138.6 5.69 27.08 76 129 111.8
FIGURE 12 Proposed active antenna (a) structure and
(b) measurement setup
has the same operating band so that both can be integrated
together to form a complete receiver unit. Figure 13 shows the
frequency band of antenna. It exactly matches with LNA while
is closely –16dB. Figure 14 gives the variation of the peak
gain of the antenna with respect to frequency which remains
almost of the highest value in the range of 3 to 5 GHz, while
Figure 15 depicts its radiation pattern that turns out to be
desirable one. The dimensions of antenna are illustrated in
Table 3.
This section includes the antenna incorporation with LNA to
get the receiver system designed for WiFi application. The
designing and performance results of antenna and LNA are
discussed in the above sections. This structure can be attrib-
uted to an active antenna. The performance of receiver is based
on the two vital parts which are antenna and LNA. In order to
simulate the overall receiver performance, we call for integra-
tion of both LNA and antenna. For this purpose, the process
includes export of HFSS le and imports it on advanced design
system (ADS) platform. It is done by using the procedure
given in the mentioned ow diagram of Figure 16. The rst
step includes creation of s2p le from HFSS software tool. In
second step, it is imported in ADS and nally the simulation is
done for the integrated device. As mentioned above, both
these elements are designed to work in the same band so that
they can be built together for other various functions in RF
communication systems.The similar combination has been
used in [23] for millimetre wave application. The concept of
conguring LNA with antenna is being used time to time to
elevate the features of wireless receiver systems.
The impedance matching and NF of an antenna are
improved by directly coupling the antenna with an LNA [24].
FIGURE 13 Return loss variation with respect to frequency
FIGURE 14 Antenna gain variation with frequency
FIGURE 15 Antenna radiation pattern
TABLE 3Dimensions of proposed antenna
Dimensions Values (mm) Dimensions Values (mm)
Wsub 40 L
Lsub 40 L
A 36 W
B 20 W
15 T0.5
In another research effort [25], a low frequency radio as-
tronomy antenna is connected to measure noise of a differ-
ential LNA. Thus this research study proposes a blend of
LNA with active antenna. The codesign structure is shown in
Figure 17. In this design, it is important to maintain imped-
ance matching between the elements so that the gain factor
and other desired parameters are not affected poorly. Here the
impedance of the structure is attained in the preferred range.
As it is evident that antenna catches noise, therefore, the
combination of LNA with antenna sacrices noise factor
which comes out to be 2.6 dB of its minimum value at 2.06
GHz with variation of ±1.5 dB as shown in Figure 18.
The combinational performance of the receiver in terms of S
parameters shown in Figure 19 reveals that much wider band
ranging from 1.6 GHz to 6 GHz is attained. The individual gain
of antenna is not good enough as the signal can be fed to the
load directly. Thus addition of LNA with antenna offers a
reasonably good gain factor in the same band with a peak value
of 16.5 dB.
The study presented a CMOS LNA with AFB for WiFi
networks. The LNA design architecture has the input stage as a
cascode network to offer wideband impedance matching fol-
lowed by the CS amplier along with NMOS AFB. The feed-
back mechanism with inductorless approach is used to nullify
the noise effect with improved bandwidth, gain stability and
impedance performances while being active andhelps to obtain
the enhanced gain. The LNA achieved wide bandwidth in the
range of 2.2 GHz to 5.8 GHz with the peak forward gain of 22.5
dB. The NF value of approximately 2 dB, the stability factor of
nearly 2.5 dB and IIP3 of about 15 dBm have been achieved
with µand µprime well above 1. A CPW fed antenna is
designed to achieve wide band response similar to that of LNA.
The peak gain of approximately 4.1 dBi at 3.9 GHz is achieved.
Finally, the codesign receiver system gave a much wider band of
1.6–6 GHz, whereas gains of 16.5 dB and minimum NF of 2.59
dB at 2.06 GHz in the same band were achieved.
FIGURE 16 Flow diagram of integration procedure
FIGURE 17 Proposed schematic of integrated receiver
FIGURE 18 Overall noise and input impedance of codesign
FIGURE 19 Combinational S parameter performance of receiver
This research study was supported by the National Research
Foundation of Korea, Grant/Award Number:
Gunjan Mittal Roy
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How to cite this article: Roy GM, Dwari S,
Kanaujia BK, Kumar S, Song H. Active feedback
supported CMOS LNA blended with coplanar
waveguidefed antenna for WiFi networks. IET
Microw. Antennas Propag. 2021;15:537546. https://
... After the simulation experiment, a 9% fractional bandwidth (300 MHz) with PAE at the 6 dB output power backed-off level that ranges between 50% and 55% was realized. Similar research work on integrated designs is presented in [29][30][31][32][33]. However, these designed integrated PA antenna structures do not consider the adverse effects of mismatching between the antenna and the PA used in their co-design methodology. ...
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A 3D electromagnetic circuit design and analysis of a MOSFET-based absorber active integrated antenna has been performed. It integrates a transmitting dual-band double material substrate (DMS) cylindrical surrounding patch antenna (CSPA) with a MOSFET-based absorber of reflected radio frequency power. It is a solution to the problem of performance degradation in the power amplifier (PA) resulting from antenna and PA impedance mismatch. This fully integrated MOSFET-based absorber antenna can absorb reflected RF power with a diode-based quasi-circulator as part of the integrated design circuitry. The antenna used for the proposed integrated design will operate at frequencies ranging from 2 GHz to 3 GHz and from 4.6 GHz to 6.1 GHz, thus providing a bandwidth of 1 GHz and 1.5 GHz at a resonance frequency of 2.5 GHz and 5.3 GHz, respectively. This makes it suitable for use in lower and upper bands of WLAN/WiMAX medium RF front-end applications. Furthermore, the condition for MOSFET connected to the absorber (IS ≤ ID and VDS = 0) has been satisfied at both instances of resonance. In this proposed design, an antenna radiation efficiency of 84% has been observed.
In this article, a wideband differential low-noise amplifier (LNA) for multiband wireless communication applications is proposed. First, shunt peaking is implemented with a self-biased active inductor (AI) to realize wideband characteristics in a compact size. Second, a cross-coupled capacitor is added to the AI, thus constructing a feedforward path. It adds a signal to the output node so that the bandwidth (BW) can be further increased by compensating the gain reduction according to the frequency. Additionally, the feedforward path creates another feedback loop, generating a negative capacitance. The negative capacitance can cancel parasitic capacitance to increase BW with a cascade amplifier. The prototype LNA is fabricated with a 65-nm CMOS process. It has a gain of 26.7 dB and a BW of 4.1 GHz. The noise figure (NF) is 3 dB and the third-order input intercept point (IIP3) is -14.2 dBm at 2 GHz. It consumes 13.9 mA at a 1-V supply and has an area of 0.009 mm <sup xmlns:mml="" xmlns:xlink="">2</sup> .
We present two methods for measuring the noise temperature of a differential input single-ended output (DISO) Low-Noise Amplifier (LNA) connected to an antenna. The first method is direct measurement of the DISO LNA and antenna in an anechoic chamber at ambient temperature. The second is a simple and low-cost noise parameter extraction of the DISO device using a coaxial long cable. The reconstruction of the DISO noise parameter from the noise wave measurements of the DISO LNA with one terminated input port is discussed in detail. We successfully applied these methods to the Murchison Widefield Array LNA and antenna.
Two inductorless low-power differential low-noise amplifiers (LNAs) are designed for multiband wireless communication applications. Both LNAs are based on the combination of common-gate (CG) and shunt feedback topologies. In the first LNA, the cross-coupled push-pull structure with separated bias for nMOS and pMOS CG transistors is utilized to realize gm enhancement, partial noise cancellation, and bandwidth extension. In the second LNA, cascode transistors are utilized on the basis of the first topology to alleviate the Miller effect and to construct current steering structures, so as to extend the bandwidth. For both LNAs, in-depth analysis is given, and methods for sizing and biasing optimization under power constraint are proposed to obtain good overall performance tradeoffs while maintaining low-power consumption. The prototypes are implemented in 65-nm low-power CMOS technology. The first LNA achieves a gain of 21.2 dB, a noise figure (NF) of 3-3.5 dB over the 3-dB bandwidth of 200 MHz to 2.7 GHz and an IIP3 of -2 dBm at 1.1 GHz. It consumes 0.96 mW from 1.2-V supply. The second LNA exhibits a gain of 21.2 dB, an NF of 2.8-4 dB over the 3-dB bandwidth of 100 MHz to 4.3 GHz. It consumes 2 mW from 1.2-V supply. Each LNA occupies an area of 0.05 mm <sup xmlns:mml="" xmlns:xlink="">2</sup> .
This paper presents an energy efficient wideband Low Noise Amplifier (LNA) operating in subthreshold regime. Wideband matching and low noise figure in subthreshold domain is achieved by using a gate inductor assisted impedance matching and a current reuse feed-forward noise cancellation technique, respectively. Fabricated in UMC 0.18 μm CMOS technology, the proposed LNA draws 1 mA from 1.8 V supply and achieves a voltage gain of 13 dB (taking into account a 8 dB loss in buffer), minimum Noise-Figure (NFmin) of 6 dB, and 3 dB bandwidth from 2 GHz to 5 GHz.
This paper deals with the fabrication of an inductorless wideband low-noise amplifier (LNA). The LNA includes two branches in parallel: a common-source (CS) path and a common-gate (CG) path. The CS path is responsible for providing enough power gain, while the CG path is used to achieve the input impedance matching. To eliminate the noise contribution of the CG path, the noise cancellation technique is applied. Therefore, the overall noise figure (NF) is improved. The phase mismatch between the two paths is also quantitatively analyzed to investigate its effect on gain and NF. The analytical results agree well with the simulation results. The LNA has been fabricated by a commercial 0.18-μm CMOS process. The measurement results show that the LNA has achieved a maximum gain of 14.5 dB with 1.7-GHz 3-dB gain bandwidth and a minimum NF of 3.0 dB. The tested input 1-dB gain compression point (IP1dB) is -10.4 dBm at 1 GHz and the input third-order intercept point (IIP3) is 0.25 dBm. With 1.8 V supply, the LNA draws only 6 mA dc current.
A high-gain, low-power, and low-noise amplifier (LNA) is designed in UMC 65 nm radio frequency (RF)-CMOS technology for operation over the 1 to 11 GHz RF band. This LNA design is based on an m-derived inductive peaking circuit with a shunt feedback inverter. The m-derived inductive peaking circuit is placed between two shunt feedback inverters. Further, a split inductor topology is introduced in the circuit. The procedure for the integrating of an m-derived inductive peaking circuit in LNA is explained in detail. The proposed circuit achieves more than 14 dB of power gain over an ultra-wideband of 1 to 11 GHz. The measurement of the proposed LNA achieves a minimum of 2.5 dB of noise figure, and more than −8 dBm of third-order input intercept point, while consuming 11.3 mW of power. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:521–526, 2017
This letter presents the design of an inductorless low power differential low-noise amplifier (LNA) in 65 nm Low Power (LP) CMOS technology for multi-standard radio applications between 100MHz and 4.3 GHz. Based on the combination of common-gate (CG) and common-source (CS) with shunt feedback (SFB) topologies, the LNA utilizes a cross-coupled push-pull structure to realize g <sub xmlns:xlink="">m</sub> boosting and partial noise cancelling under low power consumption. A cascode transistor is used to alleviate the Miller effect and also constructs a current steering structure to increase the bandwidth and gain. These techniques result in a good overall performance tradeoff after sizing and biasing optimization under the power constraint. A prototype has been implemented and it exhibits a voltage gain of 21.2 dB, an NF of 2.8-4 dB over the frequency range of 100 MHz to 4.3 GHz. It consumes 2 mW from 1.2 V supply and occupies an active area of 0.05 mm <sup xmlns:xlink="">2</sup> .
Future hyper-connected devices must support several communication standards, across various frequency bands, with a low-area, single-chip, radio frequency frontend. In this paper, we present a reconfigurable, inductorless, wide-band, low-noise amplifier (LNA) for multistandard applications. This LNA is based on a complementary current-reuse common source amplifier, combined with a low-current active feedback. A gyrator-C effect is used to achieve wideband input matching. High linearity is obtained through complementary derivative superposition and active shunt feedback. Implemented in 130-nm CMOS technology, the prototype exhibits a -3 dB bandwidth of 2.2 GHz. In high linearity mode, the LNA achieves a minimum NF of 2 dB, a voltage gain of 21.1 dB and an I I P <sub xmlns:mml="" xmlns:xlink="">3</sub> of +14.3 dBm, with 7 mW of power consumption. In low-power mode, it draws 1.5 mW, while providing a NF of 2.6 dB, a gain of 21 dB, and an I I P <sub xmlns:mml="" xmlns:xlink="">3</sub> of 4.7 dBm. The active die area is 0.0072 mm <sup xmlns:mml="" xmlns:xlink="">2</sup> .
This letter presents a current-reused V-band low-noise amplifier (LNA) with a double-transformer-coupling technique in 65nm CMOS technology. A couple of common-source (CS) stages are stacked to share current, and the double transformers are used as an RF signal path between the CS stages for both gain and stability considerations. The LNA has three CS-CS stages, and achieves a peak gain of 31.4 dB, a minimum noise figure (NF) of 4.7 dB, and a P1dB of -2 dBm over 62.9-67 GHz with a power consumption of 6 mW. The chip size is 0.66 × 0.90 mm <sup xmlns:mml="" xmlns:xlink="">2</sup> including pads.