Content uploaded by Jiaqi Tang
Author content
All content in this area was uploaded by Jiaqi Tang on Jan 27, 2021
Content may be subject to copyright.
Benefits of using a CF4-Free Microwave Induced Plasma (MIP) Spot Etch
Process to Remove Underfill and Analyze 2.5D Modules
Kevin Distelhurst1, Joe Myers1, Dan Bader1, Ron Russotti1, Pradip Pichumani2
1GLOBALFOUNDRIES, Essex Junction, VT USA
2GLOBALFOUNDRIES, Malta, NY USA
Kevin.Distelhurst@globalfoundries.com
Jiaqi Tang, Mark McKinnon
JIACO Instruments, Delft, The Netherlands
jiaqi@jiaco-instruments.com
Abstract
Advanced packages such as 2.5D will continue to grow in
demand as performance increases are needed in various
applications. Failure analysis must adapt to the changes in the
interfaces, materials and structures being developed and now
utilized. Traditional techniques and tools used for selectively
removing materials to isolate and analyze defects need to
evolve alongside these packages. A CF4-free Microwave
Induced Plasma (MIP) process is used to remove underfill
(UF) with minimal alteration of other materials on the samples,
a process which has become more difficult on 2.5D modules.
UF is removed using this MIP process to allow subsequent
analysis on interposer interconnects and µbumps in cross-
section. SEM inspection, Electron Beam Absorbed Current
(EBAC), and FIB are techniques used post cross-sectional UF
removal of these 2.5D structures. The benefits of the specific
MIP process through case studies are presented. Specifically,
the use of an automatic cleaning step and a CF4-free down-
stream O2 plasma allow easy removal of UF without damaging
other structures of interest with little tool recipe development.
Introduction
Advanced packages such as 2.5D designs are integral in the
shift of the industry to increased product performance utilizing
packaging. The interposer interconnect chip is one key to
increasing the performance of the 2.5D package by providing a
high bandwidth connection between the connecting chips as
illustrated in Figure 1. Even though the interposer can be made
with a mature technology node, it introduces many new
stresses and weak points in the Chip-Package Interface (CPI).
In order for a successful qualification of a technology node,
die level and package level milestones are carried out in
tandem. To verify reliability of the back end of line (BEOL),
CPI structures are designed and added to the test chips during
early phases of the design process. These structures are used to
test the BEOL robustness during the assembly process (dicing,
packaging, UF dispense and curing). They are also tested post
stress cycling at regular readouts of Unbiased/Biased Highly
Accelerated Stress Test (U/BHAST), High Temperature
Operating Life (HTOL), Temperature Humidity Bias (THB),
etc. One of the structures tested in 2.5D modules includes the
long (>1mm) µbump chains that connect the top large die to
the interposer along the high stress edges as shown in Figure 2.
The µbumps are typical of the industry at <40µm in diameter.
Figure 1: Cross-Sectional Illustration of a 2.5D Module, not
to scale. The interconnect portion of this form factor provides
high bandwidth communication between the top chips.
Figure 2: Cross-sectional Illustration of the CPI µbump chain
between the ASIC and Interposer on the 2.5D Module, not to
scale.
Long µbump chains with alternating connections in the top die
and interposer are among the most complicated structures for
the FA labs to successfully analyze. Fault isolation (FI)
becomes a challenge due to the complexity involved in the
sample preparation process. Multiple approaches to analyzing
long structures like µbump chains can be implemented but all
of them involve complicated sample preparation or expensive
tooling. FI can be performed on the chains prior to destructive
processes but eventually are needed to further isolate and
analyze the defect [1].
The MIP process described in this paper provides an approach
where the µbump chain can be kept intact till the fault isolation
techniques such as EBAC, lock-in thermography, Magnetic
Laminate
Interposer
Top Chip
Top Chip
Interconnect
Field Imaging (MFI) or OBIRCH are complete. This process
also allows the analysts to inspect a bump chain in cross-
section, visually without the presence of UF restricting the
visibility of the structures. The visual inspection without the
presence of UF allows the analysts to inspect the solder region
of the µbumps for cracking, sidewall wetting and many other
anomalies that might be altered or removed with other FA
destructive techniques. Specifically, a cross-section has many
layers and metals exposed that would be etched or altered by
acid or fluorocarbons such as CF4 when trying to expose
structures deeper into the cross-section. The mechanical cross-
section in Figure 3 was subjected to a fluorocarbon based
recipe to illustrate the various materials affected during the
etch; the exposed silicon and various dielectric layers are
altered heavily even before the µbumps are fully exposed.
Figure 3: SEM images of 2.5D samples subjected to
fluorocarbon plate based plasma etches. (a) A mechanical
cross-section of µbumps after etching. Most of the cross-
section is altered by the etch even though the ubumps are still
not fully exposed. (b) A top-down view of the interposer and
top chip after etching. The metalization of the interposer is
becoming exposed and the silicon surface attacked by the etch
before the UF has been adequately removed.
The interposer interconnects are another structure difficult to
expose for, at least, inspections. Once again, various materials
are present that would inevitably be altered during different
etches. The laminate, chip bumps and µbumps would be
attacked by various wet etches while the passivation, metal
layers and chip silicon would be attacked by fluorocarbon
based dry etches. An example of a 2.5D sample subjected to
O2 chamber, plate based plasma with CF4 is shown in Figure
3b.
Further development can be performed to optimize the plate
based system used in Figure 3 or other plasma systems.
However, this paper focuses on using a CF4-free MIP process
to expose µbumps and interposer interconnects by iteratively
removing the organics of the UF and an automated procedure
to clean off the inorganic UF beads. The primary benefit of
using this specific process/tool set is that only the organics are
removed, quickly and automatically, without substantial
alteration of many other inorganic materials of interest.
Subsequent SEM inspection, EBAC and FIB are performed on
the µbump cross-section to explore the capabilities post MIP
processing. Analysis using other plasma based systems is
reserved for future research.
Background of MIP
A diagram of the MIP system used for removing the UF in this
paper is shown in Figure 4. The plasma used to etch the UF
consists of the Ar carrier gas and the O2 etchant gas. No
fluorocarbons are used in the system, i.e. CF4. The plasma is
formed in the Beenakker Cavity using the microwave
generator’s power coupled via a coaxial cable inserted into the
cavity. A more detailed description of the system can be found
in [2].
Figure 4: A diagram of the MIP system used. Argon (Ar) and
Oxygen (O2) are the gases used in the plasma.
The resulting plasma stream or effluent is directed out of a
nozzle and towards the sample. The spot size of the plasma is
only several millimeters so the XYZ stage that holds the
sample is rastered under the beam at prescribed speeds and
paths dictated by the recipe. Parameters such as the microwave
Interposer
Top Chip
UF
Exposed
Metal
(b)
Interposer Si
TSV
µbump
UF
(a)
power can also be altered in the recipe to the specific
application. Similar to other O2 only based plasma systems, the
etch slows to a stop when it encounters the UF’s inorganic
filler beads. However, the sytem encorporates an ultrasonic
deionized-water bath to remove the beads and expose the next
layer of epoxy for additional plasma etching. The system can
lower the fixturing and sample into the ultrasonic bath for
processing. The etch and clean process is repeated
automatically for an alloted time.
The preferential nature of the CF4-free MIP process means the
process can continue even after protective inorganic oxides or
nitrides (e.g. SiO2 or Si3N4) are exposed and even various
metal structures (e.g. wirebonds); the etch will not signficantly
alter these layers or structures as illustrated in Figure 5. Even
silver (Ag) will be undamaged when a hydrogren plasma is
used instead of O2 [3]. The setup of the MIP tool means the
sample has minimal heating due to the downstream plasma
generation; a benefit over typical plate based plasma systems.
Heating can be detrimental to the FA process flow for defects
related to CPI or CCI (chip-chip interaction) structures where
further heat cycles can generate or propagate cracks especially
when the sample is further stressed in an epoxy block.
Figure 5 : SEM of a µPillar before(a) and after(b) the MIP
process. Little alteration of the structure is observed.
The two case studies in this paper are examples where CF4
cannot be used at all throughout the process; a step that usually
takes place at the start of many etch tools currently available.
In both case studies, the metalization, silicon and dielectrics
are exposed throughout the entire UF removal process. Any
CF4 during the etch process will alter these materials. Sticking
with a CF4-free recipe on many tools requires the manual
removal of the Si-based UF beads which normally would be
etched with the CF4. As mentioned, this MIP process has an
automatic bead removal process. The automation compounded
with CF4-free etch means a batch of samples can be etched
with no intervention, overnight and with minimal recipe
development without the need for a robust end-point detection.
Cross-Section Sample Preparation
The 2.5D samples are prepared for mechanical cross-section
by first encapsulating the sample in epoxy. The encapsulation
process is setup to minimize voids or air bubbles in the final
solid epoxy “block”. The block is trimmed down after it
hardens so that it can later fit into the MIP tool fixture. The
epoxy block is then attached to a cross-sectioning jig and hand
polished.
The goal of the mechanical cross-section is to carefully
approach an entire row of µbumps but not expose them. The
sample material and epoxy are removed up until the µbump
row using decreasing silicon carbide grit sizes. Upon reaching
close to the targeted µbump row, the silicon carbide papers are
replaced with polishing slurries to remove scratches, pitting
and other artifacts left by the previous deprocessing steps. The
area of interest is kept intact and planarity of the deprocessing
and polishing steps is not as critical. The mechanical cross
sectioning process is stopped upon the visibility of the µbumps
of interest through the remaining UF as shown in Figure 6. An
entire row of µbumps is carefully prepared this way.
Figure 6: Mechanical cross-section stopped just before the
µbumps are exposed. The reflection from the bumps is visible
through the UF and is a good end-point indication. The entire
cross-section face (>10mm) is brought to approximately this
point.
Preliminary inspection of the two initial samples (Figure 7)
that went through the MIP process showed that the epoxy
block was also etched. This was expected but not initially
addressed. In one initial case, the sample began to “unzip”.
Several steps were taken to prevent the unzipping on two
subsequent samples with defective µpillars.
First, polyimide tape is applied to the edges of the epoxy block
where the sample was cut down. Next, an aluminum clamp was
designed and milled using a CNC. Several iterations of a
clamp were made to find a design that flexed well enough to
apply pressure uniformly across the sample sides. Materials
resistant to the DI water bath were chosen. The aluminum was
clamped to the sample using stainless steel screws and nuts.
Finally, copper tape was applied to the polished face to cover
the epoxy block but leave the µpillar face uncovered.
Top Chip
Interposer
µbumps
(a)
(b)
Exposing µBumps in Cross-Section
All samples are mounted on a tool specific fixture so that the
cross-section face is under the MIP nozzle. The raster of the
stage under the nozzle captures the entire µpillar chain. The
spot size covers most of the sample and portions of the epoxy
block. Two samples were initially processed with one sample
being processed long enough to expose two rows of µbumps as
seen in Figure 7b.
Figure 7: Tilted environmental SEM images of µbumps after
MIP processing. Most of the UF has been removed around
non-defective µbumps. (a) A single row of exposed µbumps.
(b) Two staggered rows of µbumps exposed enabling analysis
of defects further into the cross-section.
Two additional samples with known defective µpillars were
then prepared. Both samples in Figure 8a & b have a two row
µpillar chain as illustrated in Figure 9. The sample in Figure 8
was prepared so that the first row was not mechanically cross-
sectioned into. MIP processing was used to expose the first
row but the recipe was not long enough to expose the second
row. Electrically, only the second has an open signature;
however, SEM inspection of the first row did indicate a
knocked over µpillar that is still contacting its pad.
The sample in Figure 8b has the first row polished into.
Electrically, both the second and first row have an open
signature. MIP processing exposed both rows and SEM
inspection revealed the likely cause of the open for both rows.
The MIP process is extremely useful in exposing mechanical
cross section surfaces where an entire row of solder bumps
(C4) and/or µbumps, in the case of 2.5D design, are required
to be exposed uniformly for further fault isolation. This
technique is beneficial in exposing the bumps with minimal
alteration for further analysis such as SEM inspections and/or
EBAC.
Figure 8: SEM images of the two subsequently processed
samples with the entire row including the defective µpillars
exposed through MIP processing. (a) This sample was
polished to just before the first µpillar row. The MIP process
exposed the first row sufficiently but did not uncover the
second. (b) A sample where the first µpillar row was
mechanically polished into. The MIP process was able to
expose the second row into the sample.
Figure 9: A layout of the two row µpillar chain. Cyan is the
interposer top level metal, red is the top chip top level metal,
and green is the µpillar. The µpillars labeled TAP, IN, OUT
are three points the chain can be electrically contacted in the
full module. The first row is the closest to the cross-section
face.
Top Chip
Interposer
Top Chip
Interposer
(b)
(a)
UF
(a)
(b)
Top Chip
Interposer
Interposer
Top Chip
1st Row
2nd Row
TAP
OUT
IN
Stitch
Stitch
Removing Underfill over 2.5D Surfaces
MIP processing has been successful in various top down
techniques such as exposing wirebonds [4], [2], [5], [6]. Figure
10 illustrates the removal of UF around chip bumps from a
FC-BGA (Flip-Chip Ball Grid Array) sample using this
technique. Typically, the chips are freed from their packages
by mechanically removing the package material up until the
UF using CNC based techniques or hand z-grinding. The UF is
then removed using wet etches that preferentially remove the
UF but stop at the top level oxide, nitride or other passivation
layers. Wet etches are typically convenient and easy to
perform; however, they can attack the underlying layers of the
chip if there is any ingress point in the sample. MIP and other
plasma based systems are capable of removing the UF. The
entire sample in Figure 10 is rastered under the plasma stream
of the MIP tool used in this paper. The automatic etching and
ultrasonic clean repeated process is employed until most of the
UF is removed.
Figure 10: Example of UF removal of a FCBGA die post
laminate removal. (a) Chip after laminate mechanically
removed. Only UF is remaining over the chip surface. (b) Post
MIP processing with bumps still present and underlying
structures unaltered.
Figure 11: Optical images of pre and post MIP processing
focusing on removing the overmold around the HBM top chip
stack and the UF over the interposer and between the top
chips. (a) Top down optical image of the HBM overmold and
surrounding UF. (b) Top down optical image of the HBM
after MIP processing has removed the overmold and UF. (c)
An angled optical image of the HBM before MIP processing.
(d) An angled optical after MIP processing.
The same process can be applied when trying to remove the
UF between the laminate and interposer after the laminate is
removed in 2.5D packages. Likewise, the UF can be removed
between the top chip(s) and interposer after the laminate and
interposer are removed. However, UF is present around and
under the top chips which then covers most, if not, all of the
underlying interposer as shown in Figure 11a&c. Careful
removal of this UF without damaging the rest of the package is
difficult with wet etches. The CF4-free MIP processing
employed thus far is preferred. Once again, a repeated etch and
clean process is employed. Furthermore, a raster path is
chosen so that only the UF around the area of interest is etched
as shown in Figure 11b, Figure 11d and Figure 12.
Figure 12: Top down optical images focusing on the
interposer interconnects between the top chips. These nets are
only visible after MIP processing has removed the UF
covering the interposer at this location. (a) A lower
magnification optical image focusing on the interposer
interconnects. (b) A higher magnification optical image of
some of the interconnects highlighted in (a). The
magnification is sufficient for inspection of various defects.
Removing the UF to expose the interposer interconnects
enables optical inspection of top metal traces as shown in
Figure 12. This may also enable fault isolation (FI) such as
laser scanning techniques like Optical Beam Induced
Resistance Change (OBIRCH). Further study of the various FI
techniques enabled after this type of MIP processing is
required.
EBAC of Cross-Sections
The primary electron beam from the SEM column generates a
large number of electron-hole pairs in the interaction volume.
The generated electron-hole pairs recombine either by a non-
radiative process releasing energy in the form of phonons
(heat) or a radiative process (with 3 bodies involved in the
process) releasing energy in the form of light. There is a third
form of energy release that results in current flowing through
the material and enables Electron Beam Absorbed Current
(EBAC) analysis, which has been extensively used in the
(a)
(b)
(a)
(b)
(c)
(d)
(a)
(b)
Top Chip
HBM Stack
Underfill
Overmold
Underfill
Overmold
Visible Traces
semiconductor industry for isolating defects in the failing nets.
This technique allows the analyst to pinpoint the location of
the defect with minimal sample preparation while keeping the
defect location intact [7].
EBAC is used on the cross-sections of the µpillars as shown in
Figure 13. Typically, the SEM tool used is capable of tilting
the stage to view the sample at various angles. However, the
EBAC stage/probes prevents the tilting of the stage so a
manual tilt is created when the sample is mounted. The tilt
allows the viewing of the second row of the µpillar chain for
imaging and EBAC analysis.
Initial EBAC of the first row indicates the chain is no longer
fully intact. Closer inspection revealed the mechanical cross-
section prior to MIP processing removed the chain links. The
second row exposed by the MIP process enables EBAC
analysis on those rows. Although the SEM inspection in Figure
13a does reveal an open µbump, the EBAC analysis shown in
Figure 13b indicates an open several µbumps before the open.
EBAC provides a high resolution fault isolation approach for
this analysis and other subtle defects as shown in [1].
Figure 13: EBAC of a µPillar chain in cross-section post the
MIP process. (a) SEM image of the EBAC area of interest.
Obvious opens are observed in the far right of the image. (b)
EBAC signal image which indicates an open several µbumps
before the obvious open in the second row. The arrow
indicates the location of the suspected open according to
EBAC. Note that the first row is disconnected due to
mechanical cross-sectioning.
FIB Post MIP Cross-Sectional Etch
SEM inspection post MIP etch may reveal the defect
sufficiently but, in some cases, a FIB cross-section may be
needed to inspect deeper into the µbump. One concern with
using the FIB is the redeposition of material into the various
interfaces now present after the UF has been removed. A FIB
cross-section is performed on a random µbump after MIP
processing in Figure 14. Interestingly, the MIP etch is capable
of under cutting a portion of the µbump. No signs of
redeposition are present from the FIB or MIP process.
Figure 14: FIB Ga Image post Ga cross-sectioning. Grain
structures of the metallurgy are visible. (a) Low magnification
image capturing the entire µbump. (b) High magnification
image showing the etch undercut of the µbump.
Conclusions
The importance of removal techniques such as the MIP
process discussed here is increasing as advanced packaging
continues to grow and evolve. The paper focused on a specific
CF4-free MIP process that allows for relatively easy removal
of UF on 2.5D modules without any adverse effect on the
inorganic materials of the module.
Etching the UF in cross-section allows closer analysis of the
µbump shape, metallurgy and contact integrity. Note that any
defect in the UF should be considered before the UF removal.
For example, cracks that propagate through the UF would be
removed. However, etching the UF after inspection allows
analysis of how defects in the UF affect the µbumps and other
structures.
(a)
(b)
FIB CAP
Etch Undercut
(b)
(a)
Figure 15: 3D optical profilometer map (left) and a line scan
plot (right) over a cavity of recessed UF.
The recipes used to expose multiple rows of µpillars need
further refinement to time the exposure of at least the second
row. The MIP process most likely slows down as it etches
deeper into the cross-section. Optical profilometery is one
method to help gauge the depth of the recessed UF as recorded
in Figure 15 and can be used for future study of the etch rate as
it progresses into the cross-section. Future work could also
focus on using other plasma-based tools and processes to see if
any additional times saving or advanced removal technique
can be discovered.
The MIP process is also used to remove UF on a fully intact
2.5D module where a wet etch or fluorinated etch would alter
many of the other inorganic materials present on the module.
Specifically, this paper focuses on removing UF over the
interposer and surrounding the top chips to expose the
interposer interconnects for optical inspection. This possibly
enables further fault isolation of the interconnects; a topic for
future work.
Acknowledgments
Frank Palermo, Doug Hunt, Chris Torcedo
References
[1] K. Distelhurst, D. Hunt, and D. Bader, “Isolating an
Open in 2.5D µBump & Chip Bump Chains using
SDR, EBAC and Capacitive Measurements,” in ISTFA
2019: Conference Proceedings from the 45th
International Symposium for Testing and Failure
Analysis, 2019, pp. 393–396.
[2] J. Tang, M. R. Curiel, S. L. Furcone, E. G. J. Reinders,
C. T. A. Revenberg, and C. I. M. Beenakker, “Failure
Analysis of Complex 3D Stacked-die IC Packages
using Microwave Induced Plasma Afterglow
Decapsulation,” 2015 Electron. Components Technol.
Conf., pp. 845–852, 2015.
[3] J. Tang, J. Wang, and W. Van Den Hoek, “Artifact-
Free Decapsulation of Silver Wire Bonded
Semiconductor Devices Using Microwave Induced
Plasma,” in ISTFA 2019: Conference Proceedings
from the 45th International Symposium for Testing
and Failure Analysis, 2019, pp. 456–460.
[4] J. Tang, B. Wang, C. Liu, J. Wang, and C. I. M.
Beenakker, “Unique failure analysis capabilities
enabled by the MIP decapsulation technique,” Proc.
Int. Symp. Phys. Fail. Anal. Integr. Circuits, IPFA,
vol. 2017–July, pp. 1–5, 2017.
[5] J. Tang et al., “CF4-free microwave induced plasma
decapsulation of automotive semiconductor devices,”
Conf. Proc. from Int. Symp. Test. Fail. Anal., pp. 151–
160, 2016.
[6] C. Odegard, A. Burnett, J. Tang, and J. Wang,
“Preserving Evidence for Root Cause Investigations
with Halogen-Free Microwave Induced Plasma,”
ISTFA 2018 Conf. Proc. from 44th Int. Symp. Test.
Fail. Anal., pp. 1–4, 2018.
[7] D. Hunt, P. Pichumani, K. Distelhurst, and M. Coster,
Microelectronics Failure Analysis. ASM International,
2019.
Recessed UF
