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1
A Distributed Pulse-Based Synchronization Protocol for Half-Duplex
D2D Communications
Onur Karatalay1, Ioannis Psaromiligkos1, Benoit Champagne1and Benoit Pelletier2
1Department of Electrical and Computer Engineering, McGill University, Montreal, PQ, Canada.
2InterDigital Canada Lt´
ee, Montreal, PQ, Canada.
Email: onur.karatalay@mail.mcgill.ca; ioannis.psaromiligkos@mcgill.ca;
benoit.champagne@mcgill.ca; benoit.pelletier@interdigital.com
In distributed device-to-device (D2D) communications, no common reference time is available and the devices must employ
distributed synchronization techniques. In this context, pulse-based synchronization, which can be implemented by distributed
phase-locked loops is preferred due to its scalability. Several factors degrade the performance of pulse-based synchronization, such
as duplexing scheme, clock skew and propagation delays. Furthermore, in distributed networks, devices should be aware of the
synchronization status of others in order to initiate data communications. To address these prevailing issues, we first introduce
a half-duplex timing-advance synchronization algorithm wherein each device alternates between being a transmitter and receiver
in their exchange of synchronization pulses at each clock period. Based on this algorithm, we propose a novel fully-distributed
pulse-based synchronization protocol for half-duplex D2D communications in 5G wireless networks. The protocol allows participating
devices to become aware of the global synchronization status, so that they can complete the synchronization process ideally at the
same time and proceed to data communication. In simulation experiments over multi-path frequency selective channels, the proposed
synchronization protocol is shown to outperform a benchmark approach from the recent literature over a wide range of conditions,
e.g., clock skew, number of devices, and network topology.
Index Terms—Distributed synchronization, phase locked-loops, timing-advance, Device-to-Device communication, half-duplex, 5G
I. INT ROD UC TI ON
The fifth generation (5G) of wireless networks is currently
being actively deployed in various parts of the world. It is
expected that new use cases will continue to be addressed
for years to come by introducing new features into the
specifications of 5G or future generations. Device-to-device
(D2D) communications [1–3], i.e., direct connection between
selected devices, is a functionality that has been introduced
recently in Release 16 of the 3GPP specifications in support
of vehicle-to-vehicle communications [4]. Hence, traffic load
on base-stations (BSs) can be significantly reduced since they
do not need to initiate, maintain or relay the connections
between such devices [5]. Moreover, this feature is expected
to be further developed to address use cases such as ad-
vanced vehicle-to-vehicle communications, extended coverage
via device relaying, industrial applications and virtual reality.
Specifically in [6], the authors study distributed learning for
D2D communications, whereas in [7], downlink resource
allocation and power control are considered for underlay
D2D networks. However, there remain several challenges of
their own, especially regarding how the devices initiate and
maintain data transmission.
Synchronization is an essential step in establishing a con-
nection in a digital communication system. In cellular net-
works, a fixed access point (AP) such as a BS regularly
broadcasts a time signal so that user devices can synchronize
themselves to a common reference clock. Such centralized
This work was supported in part by the Natural Science and Engineering
Research Council under the Discovery Grant program, and by InterDigital
Canada Lt´
ee and MITACS Canada under the MITACS Accelerate program.
schemes not only offer fast synchronization but also easily
maintain it by regularly correcting the device clocks, which
can diverge due to clock skews. In addition, the same AP can
coordinate the devices during communication to compensate
for propagation delays by adjusting their clocks, a technique
known as timing-advance. However, in distributed systems
such as wireless sensor networks (WSNs) or out-of-coverage
D2D networks, the latter being one of the use case for
D2D communications, no such fixed AP is available. In this
type of scenarios, the aforementioned benefits of centralized
synchronization can be retained by selecting, e.g., via an
“elect-a-leader” algorithm [8], one of the devices to serve
as the synchronization AP. Nonetheless, the synchronization
performance depends heavily on the choice of the AP and on
the quality of the channels between the AP and the rest of the
devices. In addition, if the AP loses connectivity with a part
of the network or leaves the network, then the AP selection
process should be re-initiated.
An alternative approach is distributed synchronization,
wherein devices exchange synchronization signals according
to a predefined strategy, or protocol, allowing them to reach
a consensus on a common reference time [9]. Although
typically slower than centralized synchronization, distributed
synchronization is more robust against connectivity failures
and network changes due to mobility. Hence, it may be better
suited for WSNs or out-of-coverage D2D networks where
such conditions are prevailing [10]. Nevertheless, the technical
aspects of a network determine the design of the synchroniza-
tion algorithm. Specifically, in a typical WSN, information
flows towards a single sink node, while data communication
is low rate and sporadic with relaxed guarantees in terms
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of latency and reliability. In contrast, D2D communication
by nature requires high data rate, low-latency and reliable
communication between arbitrary devices. Therefore, to satisfy
these requirements, distributed D2D networks must employ a
reliable, fast and efficient synchronization algorithm, which
should also mitigate the effect of propagation delays and
multipath channels by properly using timing-advance [11].
A. Related Works and Motivation
The prevalent approaches for distributed synchronization
can be divided into two main categories, namely: packet-
based and pulse-based [10]. Packet-based synchronization is
a medium access control (MAC) layer-based approach relying
on the exchange of timestamps encoded in packets [12–15]. It
requires collision-free transmission of the packets on a random
access channel and their subsequent successful decoding. As
such it suffers from delays due to packet queuing and re-
transmissions and, more importantly in the context of D2D
communications, it exhibits high energy expenditure, high
latency and poor scalability. Pulse-based synchronization, in
contrast, is a physical layer-based approach where the timing
information is encoded in the transmission time of physical
layer pulses. Local clock updates are done by processing
the received superposition of timing pulses transmitted by
neighbouring devices. This approach, which naturally cap-
italizes on the broadcast nature of wireless channels, can
overcome the above-mentioned limitations of packet-based
approach. Thus, pulse-based is often preferred over packet-
based synchronization in distributed wireless networks [9],
[10].
Pulse-based synchronization is typically implemented by
distributed phase locked-loops (DPLL) [16], [17]. The perfor-
mance of DPLL is affected by the duplexing scheme employed
by the devices. Full-duplex communication significantly de-
creases the synchronization time compared to half-duplex
due to simultaneous signal transmission and reception, and
has been considered by several authors [9], [18]. However,
implementation of full-duplex technology, especially at the
mobile devices poses a number of practical issues in terms
of cost, complexity and power consumption [16], [17]. Due to
the additional power required for self-interference cancellation
mobile devices with a limited battery life cannot currently
afford to operate in the full-duplex mode [19]. Hence, half-
duplex communication is a more practical implementation
choice for distributed networks and is likely to remain so in
the near future.
Several other factors limit the performance of DPLL, such
as the quality of the crystal oscillators whose frequency may
drift with temperature fluctuations. This effect, known as clock
skew, alters the perceived rate of signal transmission and
reception arbitrarily over time. Furthermore, the effects of
clock phase and propagation delays are entangled within the
superimposed timing pulses. In order to achieve synchroniza-
tion, the aforementioned effects should be estimated from the
received pulses and removed by updating the device clocks
accordingly [17]. However, this estimation becomes highly
challenging as the received pulses are not only altered by these
effects, but also by the very mechanisms used to correct them,
which could lead to instability.
In the literature, it is often assumed that: the device clocks
are frequency synchronized (i.e., there is no clock skew) [9],
[16–18], there are no propagation delays, and the network size
(i.e., the number of devices) is static [20]. However, signal
propagation delays do exist and D2D devices can arbitrarily
join or leave the network; hence, these assumptions are not
valid in a realistic scenario. In [21], a synchronization method
is proposed, in which clock skew and clock phases are cor-
rected with respect to a selected reference node which does not
participate in the synchronization process. Another approach
is proposed in [18], where the devices first estimate the
propagation delays to their neighbors and then transmit these
estimates to a centralized fusion center; in turn, the center
informs all the devices about the delay estimates within the
network. Consequently, synchronization is achieved after pre-
compensation for propagation delays is applied, i.e., timing-
advance. In the absence of a centralized fusion center as, for
example, in an out-of-coverage D2D network, such global
time-advance compensation is impractical. Clock phases, clock
skews and propagation delays in this case should be jointly
estimated in a distributed manner, thereby allowing devices
to synchronize their clocks individually by means of timing-
advance.
Furthermore, to initiate data communication in a distributed
D2D network, the participating devices should simultaneously
terminate the synchronization process. However, the devices
are not aware of the synchronization status of others in a
distributed network and the time it takes to reach synchroniza-
tion might vary for each device. If some of the devices stop
their synchronization process later than others, the presence of
ongoing timing pulses might trigger the synchronized devices
to re-start this process [17]. Thus, in a fully distributed
wireless network, the devices should be aware of the global
synchronization status, so that they can terminate the synchro-
nization process ideally at the same time and proceed to data
communication.
Once the synchronization process is completed, some of
the devices might become idle to conserve energy, while
others might begin data communication. In this case, the
idle devices may lose synchronization with respect to the
communicating ones since there is no mechanism to inform
them about their status. To prevent this, the devices must
periodically re-transmit timing pulses, i.e., discovery beacons,
to remain part of the network [22], [23]. However, this will
cause a disturbance among the synchronized devices and
increase energy consumption in the overall network. Hence,
synchronization should be maintained as long as possible
without exchanging timing pulses to reduce the frequency of
unnecessary re-initialization.
B. Contribution and Paper Organization
In this paper, motivated by the above considerations, we first
introduce a timing-advance synchronization algorithm wherein
each device alternates between the transmitter and receiver
modes in their exchange of synchronization pulses at each
clock period. Based on this algorithm, we then propose a
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novel fully-distributed pulse-based synchronization protocol
for half-duplex D2D communications in 5G networks. This
work significantly extends upon our previous contributions
in [17], [24], where we focus on a simplified version of
the problem by neglecting the presence of clock skew and
its influence on data communication. Specifically, our main
contributions in this work are summarized as follows:
•We propose an online estimation technique which jointly
tracks the synchronization errors due to clock phases,
clock skews and propagation delays in multipath chan-
nels. We incorporate the obtained estimates in the con-
ventional DPLL clock update and propose a half-duplex
timing-advance synchronization algorithm which com-
pensates for all these effects in a distributed manner.
In particular, we show analytically that the proposed
compensation mechanism contributes to reducing the
synchronization error at each iteration.
•We conceive a distributed synchronization protocol in
the form of a state diagram, which can be easily imple-
mented on each device. In this protocol, the participating
devices acquire the synchronization status of others by
a coordinated exchange of pulses, and terminate this
process as soon as the overall network is synchronized.
Our proposed protocol also allows the devices already in
operation to detect the presence of new devices joining
the network at any time, and to re-synchronize themselves
by including the new ones.
•After the network is synchronized, the devices can either
initiate data communication or stay idle and only operate
as a receiver to conserve power. At this point, to main-
tain synchronization in the network without exchanging
timing pulses, the devices predict their relative clock
time based on estimated values of the synchronization
parameters. Thus, they can preserve the already achieved
synchronization without unnecessarily re-initiating this
process.
•The complete integrated protocol is evaluated by means
of computer simulations based on 5G channel models and
under different conditions of operation, i.e., clock skew,
number of devices, and network topologies, including
full mesh and partial mesh. Our extended results show
that the proposed protocol offers better synchronization
performance than a benchmark approach from the current
literature [16], even for partial-mesh topology.
The rest of the paper is organized as follows. In Section II,
we present the system model and the problem statement for
distributed D2D synchronization. In Section III, we propose
a distributed half-duplex synchronization algorithm that uses
timing-advance. In Section IV the overall synchronization
protocol with its state diagram is described in detail. The
performance of the proposed protocol is evaluated by means
of computer simulations in Section V. Finally, Section VI
concludes the paper.
II. SY ST EM MO DE L AN D PROB LE M STATEM ENT
A. Network Setup and Clock Model
We consider a distributed overlaying D2D network, which
can be fully or partially connected, with Jwireless devices
indexed by j∈ J ={1, ..., J }as illustrated in Fig. 1. We
assume that the devices may join or leave the network at
any time and that they do not have any information about
the network, such as the number of nearby devices or their
locations. Since there is no BS to provide a common timing
reference, the devices synchronize their clocks in a fully
distributed manner by exchanging timing pulses over radio
frequencies at the physical layer.
Fig. 1. Fully or partially connected D2D networks. In the partial mesh
topology, common devices (shown in red), act as a relaying node during
synchronization.
The physical clock of the jth device is modeled as tj(t) =
αjt+θj[25], where tis the universal time, αjis the clock
skew, and θj∈[0, T0)is the clock phase with T0being the
clock period. A discrete logical clock is obtained by uniformly
sampling the physical clock at times t=νT0, that is:
tj[ν] = tj(νT0) = αjν T0+θj(1)
where ν∈Nis the discrete-time index. We refer to time
tj[ν]as the νth clock tick of the jth device. It is convenient
to partition the universal time axis into a sequence of non-
overlapping time slots [νT0,(ν+ 1)T0). In practice, αjdiffers
from 1 by a very small amount, on the order of a few parts
per million (ppm) [26], and it is therefore safe to assume that
each time slot contains a single clock tick tj[ν]as shown in
Fig. 2. In the ideal case of no propagation delay, we define
the time-offset (TO) between the ith and the jth devices as
the minimum clock tick difference, that is:
∆tij [ν] = min
η∈Vνti[η]−tj[ν](2)
where for convenience, we define the set Vν={ν, ν ±1}. In
effect, ∆tij[ν]can be interpreted (for this ideal case) as the
synchronization error between the devices iand j.
B. Half-duplex Signaling Model
We assume half-duplex communication, where a device can
only transmit or receive at any given time. We define the
transceiver mode of the jth device at the νth clock tick as
Mj
ν∈ {TX,RX}indicating whether the device operates in
transmitter mode (TX) or in receiver mode (RX), as depicted
in Fig. 2. We let Tνand Rνdenote the mutually exclusive
index sets of transmitter and receiver devices at the νth clock
tick, respectively.
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Fig. 2. Clock ticks of two devices relative to the partitioned universal time
axis. At the νth clock tick, device 1 is a transmitter as denoted by TX (upward
arrow) whereas device 2 is a receiver as denoted by RX (downward arrow).
If, at a given clock tick ν, a device operates as a transmitter,
i.e., i∈ Tν, it broadcasts a time-shifted synchronization signal
x(t−ti[ν]) with x(t)defined as:
x(t) =
Ns−1
X
n=0
s[n]g(t−nTp)(3)
where g(t)∈Ris a normalized baseband pulse and Tp
denotes the pulse spacing with NsTpT0. In (3), s[n]is
a synchronization sequence of length Ns= 2Nconstructed
by concatenating two Zadoff-Chu (ZC) sequences of length N
with root indices uand −u[18], that is:
s[n] = (ejπ
Nun2,0≤n≤N−1
e−jπ
Nu(n−N)2, N ≤n≤2N−1(4)
where uand Nare coprime, and j = √−1. By constructing
the synchronization sequences as in (4), the effect of carrier
frequency offsets (CFO) is decoupled from TO estimation [18].
A receiver device j∈ Rνlistens for broadcasted synchro-
nization signals over the reception period [tj[ν]−T0
2, tj[ν] +
T0
2), centered at its own clock tick tj[ν], as illustrated in Fig.
2. The received signal at the jth device is:
yj(t) =X
η∈VνX
i∈Tη
x(t−ti[η]) ∗hij (t) + wj(t)(5)
where hij (t) = Pp∈P ρijp δ(t−τijp )is the impulse response
of the multipath channel between the ith and jth device,
p∈ P ={1,··· , P }is the path index, Pis the number
of resolvable paths, assumed to be the same for all devices,
and δ(·)is the Dirac delta function. Additionally, ρijp ∈C
and τijp ∈R+are the complex gain and propagation delay,
respectively, of the pth path, while operator ∗denotes convolu-
tion and wj(t)is an additive noise term. Note that depending
on the clock phase of the receiver device, the received signal
may contain signal contributions not only from the νth clock
tick but also from the adjacent ones, i.e., (ν±1)th. Thus, the
outer summation in (5) takes all possible signal contributions
into account; however, it does not span beyond the (ν−1)th
time slot as the propagation delays are assumed to be much
smaller than the clock period, that is, τijp T0.
Finally, the jth receiver device samples (5) at time instances
kTsduring the reception period, where TsT0is the
sampling period, k∈ K ={−K, ··· ,−1,0,1,· ·· , K}is the
discrete-time index, and K=bT0
2Tsc. The resulting sampled
signal at the νth clock tick is expressed as:
yj[k;ν]=yj(kTs+tj[ν]) (6)
=X
η∈VνX
i∈TηX
p∈P
ρijp x(kTs+tj[ν]−ti[η]−τijp)+wj[k]
where wj[k]is the discrete-time noise process.
C. DPLL Clock Update
At the νth clock tick, the jth receiver device cross-correlates
(6) with the two distinct parts of the synchronization signal
(available locally) to decouple the effect of CFO in TO
estimation [18]:
Ryjx±[l, ν] = X
k∈K
yj[k;ν]x±[k−l]∗(7)
where lis the integer lag and superscript * denotes com-
plex conjugation. The first correlation is with x+[k] =
PN−1
n=0 s[n]g(kTs−nTp), which is obtained from (3) by
retaining pulses with index 0≤n≤N−1and sampling
every Ts, while the second correlation is with x−[k] =
P2N−1
Ns[n]g(kTs−nTp), which is obtained in a similar way
but for N≤n≤2N−1. Hence, the subscripts ±in the
signals x±[k]indicate which ZC root index (i.e., +uor −u)
is used to construct them.
The jth device then uses a weighted average across lags l
to obtain two different preliminary TO estimates [9]:
q±
j[ν] = Pll Ts|Ryjx±[l, ν ]|2
Pl|Ryjx±[l, ν]|2.(8)
Here, q+
j[ν]provides an estimate of the average TO seen by
the jth device, while q−
j[ν]provides a similar estimate but
with a positive offset of NTpdue to the definition of x−[k]
in (7). Then, the jth device combines the estimates in (8) to
obtain the desired weighted average TO estimate as:
c
∆tj[ν] = 1
2q+
j[ν] + q−
j[ν]−NTp.(9)
In the following, this quantity will be interpreted as the
synchronization error experienced by the jth receiver at the
νth clock tick. Hence, the jth device updates its clock tick for
the (ν+ 1)th time slot as dictated by DPLL [10]:
tj[ν+ 1] = tj[ν] + αjT0+c
∆tj[ν], j ∈ Rν(10)
where > 0is a scaling parameter. We note that by using
the DPLL clock update, the devices implicitly change their
clock phases, which makes the clock phase time-variant, i.e.,
θj≡θj[ν]. Therefore, to emphasize this point, we re-write the
discrete logical clock in (1) as tj[ν] = αjνT0+θj[ν],∀j∈ J .
In contrast to (10), for the ith transmitter device, no correction
is made and the clock tick is updated as:
ti[ν+ 1] = ti[ν] + αiT0, i ∈ Tν.(11)
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D. Problem Statement
When devices join the network, unpredictable differences
in clock phases, clock skews and propagation delays lead to
synchronization errors. To further elaborate on this point, let
us analyze the weighted average TO expression in (9). Based
on the signal model in (6), this can be approximated as [10]:
c
∆tj[ν]≈X
η∈VνX
(i,p)∈Dν,η
j
µijp (ti[η] + τijp )−tj[ν](12)
=X
η∈VνX
(i,p)∈Dν,η
j
µijp ti[η]−tj[ν]
| {z }
∆tj[ν]
+X
η∈VνX
(i,p)∈Dν,η
j
µijp τijp
| {z }
βj[ν]
where Dν,η
j=(i, p)∈ Tη× P :ti[η] + τijp −tj[ν]≤T0
2
is the set of pairs formed by the index of transmitter devices
and the path indices contributing to the received signal of the
jth receiver device during the reception period centered at
its νth clock tick. In (12), µijp is the normalized channel
gain of the pth path between the ith and jth devices given
by µijp =|ρij p|Pη∈VνP(i,p)∈Dν,η
j|ρijp |−1. Moreover,
c
∆tj[ν]can be written as a sum of two terms: the first term
∆tj[ν], is the weighted average of clock tick differences
between the contributing transmitters and the jth receiver,
which includes the effects of the relative clock phases and
clock skews. The second term βj[ν]is a weighted average of
the propagation delays seen from the jth device; we will refer
to this term as bias.
Using (12), the DPLL clock update in (10) becomes:
tj[ν+ 1] ≈tj[ν] +αjT0+∆tj[ν]+βj[ν], j ∈ Rν.(13)
Even if the device clocks were perfectly aligned initially, i.e.,
ti[0] = tj[0] ∀i, j ∈ J, and consequently ∆tj[0] = 0, the
clocks might start deviating from each other as νincreases due
to differences in clock skews, i.e., αi6=αj, so that ∆tj[ν]6= 0
for ν > 0in general. Furthermore, the propagation delays,
which are always positive by nature, introduce an additional
error due to the bias βj[ν]. Hence, our first objective in this
work is to reduce the effects of clock phases, clock skews and
bias by means of distributed timing-advance synchronization.
Ultimately, for νsufficiently large, the maximum synchroniza-
tion error for the overall network in the practical case with
propagation delays should not exceed a pre-defined threshold
λsync, that is:
max
i,j∈J
η∈Vνti[η] + τij1−tj[ν]≤λsync (14)
where τij1is the delay of the first path and the maximum is
over all i, j ∈ J as well as η∈ Vν.
In distributed networks, the devices are not aware of the
synchronization status of others and they do not generally ex-
perience the same synchronization error. Therefore, the devices
cannot stop the synchronization process simultaneously by just
relying on their own error estimates, as given by (9). In fact, if
some devices stop this process earlier than others, they might
become asynchronous with respect to the remaining devices
still running DPLL; while if some devices stop later than
others, the presence of ongoing timing pulses might trigger the
synchronized devices to re-start the process. Hence, our second
objective aims for distributed coordination among the devices
to let them be aware of the overall network synchronization
status and, ideally, terminate the synchronization process at
the same time.
After synchronization, some of the devices may become
idle to conserve energy instead of immediately initiating data
communication, in which case the idle devices may become
asynchronous with the rest of the network. To prevent this,
they must periodically re-initiate the synchronization process.
However, frequent re-initialization will lead to a disturbance
among the synchronized devices and increased energy con-
sumption in the overall network. Thus, our third and final
objective is to maintain synchronization as long as possible
without exchanging timing pulses to reduce the frequency of
re-initialization.
III. TIM IN G-ADVAN CE SY NC HRO NI ZATION ALGO RI TH M
In this section, we introduce a timing-advance synchro-
nization algorithm that will later be used to develop a full-
fledged synchronization protocol. First, we introduce a half-
duplex method, whereby each device alternates between the
transmitter and receiver modes in their exchange of timing
pulses at each clock tick. Second, we modify the DPLL
clock update to achieve timing-advance synchronization in a
distributed manner. Third, we present an online bias estimation
technique, which will be incorporated into the modified DPLL.
Finally, the overall algorithm is given from the perspective of
a single device.
A. Alternating Transceiver Mode
In distributed half-duplex synchronization, some devices
broadcast timing pulses, while the others listen for the broad-
casted signals during their own reception period to update
their clock. However, if the devices randomly decide their
transceiver mode at each clock tick as in [16], then the set
Dν,η
jof transmitter devices and path indices seen by the jth
receiver device, as defined in (12), will evolve unpredictably
over time. In turn, this will result in arbitrary fluctuations in
the weighted average TO estimates c
∆tj[ν][24].
To eliminate this source of randomness in the set Dν,η
j,
we propose a method called alternating transceiver mode,
which enables devices to determine their transceiver mode
independently in a systematic manner. The underlying concept
of the method is illustrated in Fig. 3. When a device first joins
the network at the νth clock tick, it randomly initializes its
transceiver mode, where the probability of being a transmitter,
denoted as ptr ∈(0,1), is pre-determined and the same for all
devices. If a device operates as a transmitter, it broadcasts
its synchronization signal and then for the next clock tick, it
changes its mode to become a receiver. If instead the device
operates as a receiver, it listens for broadcast synchronization
signals and attempts to determine whether or not such a
signal is present during its reception period. This detection
is performed by comparing the cross-correlation in (7) to a
threshold value, as further explained in Section IV. In the
case of signal detection (whose probability depends on several
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Fig. 3. Concept of the alternating transceiver mode.
factors, e.g., the number of devices, ptr, and the SNR) the
device alternates its mode at the next clock tick to operate
as a transmitter; otherwise, it randomly re-determines its
transceiver mode based on ptr as above.
Based on the diagram in Fig. 3 and assuming that the proba-
bility of signal detection for a receiver is high, the devices will
cluster themselves into TX and RX groups and alternate be-
tween them at each clock tick. We have observed this behavior
in our simulations under representative conditions of operation
for Long-Term Evolution (LTE) [27], as further discussed in
Section V. Hence, the synchronization signals are exchanged
between the same groups of transmitter and receiver devices,
which has two important implications. First, the clocks of each
device are corrected at every two clock ticks by using DPLL
as given in (10). Consequently, clock skew can only alter the
device clocks for no more than one clock tick before being
compensated, which helps speed up synchronization. Second,
in the case of time-invariant channels, the bias term in (12)
becomes constant, i.e., βj[ν] = βj[ν+2], since the jth receiver
is always affected by the same combination of transmitters
and propagation paths, i.e., SηDν,η
jremains constant as νis
incremented to ν+ 2.
B. Modified DPLL
Timing-advance synchronization can reduce the effect of
propagation delays. Under the alternating transceiver mode,
the receiver devices expect signals from the same group of
transmitters at every two clock ticks. Hence, we let the receiver
devices take proactive actions by modifying the DPLL clock
update in (10) as follows:
tj[ν+ 1] = tj[ν]+αjT0+c
∆tj[ν]−2b
βj[ν],∀j∈ Rν(15)
where b
βj[ν]is an estimate of the bias term in (12). Meanwhile
the clock update of transmitter devices remains unchanged, as
already given by (11).
To motivate the introduction of the term −2b
βj[ν]in (15),
we consider a simple case wherein two devices, labeled
as D1 and D2, exchange synchronization signals under the
alternating transceiver mode over a single path channel with
delay τ > 0. Assume that at the νth clock tick, D1 and
D2 operate as transmitter and receiver, respectively, and that
their clocks are perfectly aligned without clock skew, i.e.,
t1[ν] = t2[ν]and α1=α2= 1 as illustrated in Fig. 4.
After broadcasting its signal, D1 updates its clock based on
(11) as t1[ν+ 1] = t1[ν] + T0, and then switches to the
receiver mode. Meanwhile, due to the propagation delay, the
corresponding synchronization error at D2 is c
∆t2[ν] = τ.
Assuming that D2 has a perfect bias estimate, i.e., b
β2[ν] = τ,
it updates its clock based on the modified DPLL (15) as
t2[ν+ 1] = t2[ν] + T0−τ, where is set to 1 for simplicity.
At the (ν+ 1)th clock tick, D2 which now operates as a
transmitter, broadcasts its synchronization signal. Due to the
additional term −2b
βj[ν] = −2τ, the synchronization error at
D1, which now operates as a receiver, will be c
∆t1[ν+ 1] = 0.
More generally, by employing the modified DPLL along
with alternating transceiver mode, clocks of the receivers
will be advanced in time with respect to the clocks of the
transmitters at every tick. Therefore, the devices can achieve
timing-advance synchronization in a distributed manner.
Fig. 4. Timing-advance synchronization in a distributed manner with prop-
agation delay τ(upward dashed arrow represents the arrival time of a
synchronization signal).
C. Estimation of the Bias
Application of the modified DPLL in (15) requires an
estimate of the bias term βj[ν]. For estimating this term, the
jth device can only rely on its TO estimate c
∆tj[ν]from (9),
which includes contributions from both ∆tj[ν]and βj[ν], as
seen from (12). Furthermore, as each device updates its clock
based on c
∆tj[ν]by using the recursive DPLL in (15), future
TO estimations will be affected by previous clock corrections.
Hence, conventional time averaging techniques applied to
c
∆tj[ν]might fail to yield an unbiased estimate. Besides,
the averaging time required by conventional techniques to
achieve the desired accuracy may negatively impact the overall
synchronization time. Therefore, estimation of βj[ν]becomes
challenging.
Alternatively, we can capitalize on the fact that, by using
the alternating transceiver mode, the bias seen from a receiver
device over time-invariant channels becomes constant. By
exploiting this special property of b
βj[ν], the jth receiver device
may try to isolate it from c
∆tj[ν]while updating its clock
based on (15). Since by using DPLL, ∆tj[ν]tends to 0 as ν
increases in the absence of propagation delays [10], estimation
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of the bias can be achieved by seeking to iteratively reduce the
absolute synchronization error, i.e., |c
∆tj[ν+ 2]| ≤ |c
∆tj[ν]|.
To this end, we therefore propose the following online bias
estimation technique:
b
βj[ν] = b
βj[ν−2] + γjsgn(c
∆tj[ν]) (16)
where sgn(·)is the sign function, i.e., the jth receiver device
applies corrections to its bias estimate with a small step size
γj∈R+based on the sign of its current TO estimate.
Specifically, if c
∆tj[ν]>0(<0), then the weighted average
of the signal contributions from transmitters to the jth device
is advanced (is lagging) in time with respect to its own clock
tick. Hence, the jth device increases (decreases) its previous
estimate b
βj[ν−2] by γjin order to reduce its future TO
estimate |c
∆tj[ν+ 2]|. When a device joins the network at tick
ν0, it may initialize its bias estimate b
βj[ν0] = b
βinit based on
the expected physical delay in the network. For instance, the
initial value can be set to b
βinit =d
c, where dis the average
distance between the devices and cis the speed of light.
In Appendix A, we analytically show that the application
of (16) in a multi-device network leads to a reduction of the
synchronization error at each device as νincreases. In practice,
we have found that this technique can be improved further
by using a dynamic step size instead of a fixed one, that is,
γj[ν] = aγj[ν−2] + b, where a∈(0,1) and b∈R+is a
constant increment.
D. Proposed Algorithm
Each device independently implements the above proce-
dures for distributed timing-advance synchronization after
joining the network at the ν0th clock tick. In Algorithm 1,
these procedures are summarized and presented from the per-
spective of the jth device, assuming without loss in generality
that it joins the network at the ν0= 0th clock tick.
Algorithm 1 Timing-Advance Synchronization
1: Initialize Mj
ν0(based on ptr)and b
βj[ν0] = b
βinit
2: for ν= 0,1,2, ... do
3: if Mj
ν=TX then
4: Broadcast the synchronization signal (3)
5: Advance the clock as in (11)
6: Become receiver: Mj
ν+1 =RX
7: else
8: if Synchronization signal is detected then
9: Estimate the average TO (9)
10: Update the clock based on modified DPLL (15)
11: Update the bias estimate (16)
12: Become transmitter: Mj
ν+1 =TX
13: else
14: Mj
ν+1 =TX,with ptr
RX,with 1−ptr
15: Advance the clock as in (11)
16: end
17: end
18: end
In Appendix B, we study the rate of decrease of TO when
Algorithm 1 is applied to a simplified scenario consisting
of two devices. Furthermore, in Appendix C, we derive the
expected value of TO when the devices run Algorithm 1 in
the same simplified scenario. Therefore, based on the effect of
various parameters such as γj,ptr and used in the algorithm,
we can choose the values that yield the best performance in
terms of error reduction.
IV. PROPOSED SYNCHRON IZ ATIO N PROTOCO L
Based on the timing-advance synchronization algorithm, we
first propose a synchronization protocol and present it over
a state-transition diagram and then we give its complexity
analysis. The underlying idea of the protocol is to create
coordination among the participating devices to ensure a
simultaneous termination of the synchronization process and
let them initiate data communication. Therefore, to coordinate
the devices in a distributed manner, we propose to use two
different synchronization signals; the first signal is utilized for
error reduction, whereas the presence of the second signal is
a declaration of the synchronization status of a device to the
network.
We construct these two signals based on (3)-(4), which
can be distinguished by their ZC index u. Specifically, all
the transmitter devices broadcast the first signal by using the
ZC index u=u1to decrease their synchronization error
below a threshold. Once they achieve this, the devices start
broadcasting the second signal by switching to the ZC index
u=u2. If a receiver device detects only the second signal
but not the first one, then it knows that all the contributing
devices are synchronized. In other words, the use of the ZC
root index u2by a device serves as a declaration to the rest
of the network that it has deemed itself synchronized.
Since the devices use two synchronization signals, the cross-
correlated received signal at a device can be one of four kinds:
•It contains no synchronization signals at all (this may
occur when there are no transmitter devices).
•It only contains synchronization signals using root index
u1(this occurs when all transmitter devices try to reduce
their own synchronization errors);
•It only contains synchronization signals using root index
u2(this occurs when all the transmitter devices deem
themselves to be synchronized).
•It contains a mix of signals using u1and u2(this occurs
when some devices are still reducing their errors while
others are deem themselves to be synchronized).
Therefore, a receiver device should be able to reliably detect
the presence or absence of the ZC root index u1or u2within
the received signal by performing the cross-correlation in (7),
which we re-define as Ryjxu
±[l, ν] = Pk∈K yj[k;ν]xu
±[k−l]∗
to emphasize u.
Considering the properties of ZC sequences, auto-
correlation of two synchronization signals that have the same
root index yields a peak value Nat lag l, i.e., |Rxu1
±xu1
±[l, ν]|=
N[28]; however, cross-correlation of such two signals with
different root indices yields |Rxu1
±xu2
±[l, ν]|=√N[29].
Hence, after cross-correlating the received signal in (7) with
both xu1
±[k]and xu2
±[k]at the the νth clock tick, the jth
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receiver device calculates the following decision statistic for
each u∈ {u1, u2}:
ψ(ν, u) = max
l(|Ru
yjx±[l, ν]|)(17)
and compares it to a detection threshold λdet. Note that in LTE,
ZC sequence length Nis 839 [29], and considering the typical
noise levels, we set this detection threshold as λdet =N
2in
our work. Accordingly, the receiver makes one of the following
four decisions:
D00
ν:ψ(ν, u1)< λdet ∧ψ(ν, u2)< λdet
D10
ν:ψ(ν, u1)≥λdet ∧ψ(ν, u2)< λdet
D01
ν:ψ(ν, u1)< λdet ∧ψ(ν, u2)≥λdet
D11
ν:ψ(ν, u1)≥λdet ∧ψ(ν, u2)≥λdet
(18)
where ∧is the logical conjunction and the superscripts of the
decisions indicate the presence, i.e., 1, or the absence, i.e., 0,
of the ZC root indices u1and u2, respectively. Decision D00
ν
corresponds to the case where no synchronization signal is
detected. In response, the device re-establishes its transceiver
mode for the next tick based on ptr and advances its clock
by one clock period. For any of the other three decisions, the
receiver device forms its final TO estimate as follows:
c
∆tj[ν] =
c
∆tu1
j[ν],D10
ν
c
∆tu2
j[ν],D01
ν
1
2c
∆tu1
j[ν] + c
∆tu2
j[ν],D11
ν
(19)
In the above, the superscript to the weighted average TO
estimate c
∆tu1
j[ν]or c
∆tu2
j[ν]indicates from which ZC root
index it is obtained. In the case of D11
ν, the jth device forms its
final TO estimate by using the arithmetic mean of its individual
TO estimates c
∆tu1
j[ν]and c
∆tu2
j[ν], since it is consistent with
the definition of (9) as a weighted average.
In what follows we describe the proposed protocol over a
state-transition diagram as given in Fig. 5 from the point of
view of the jth device.
Fig. 5. State-transition diagram of the proposed protocol. Transitions happen
at each clock tick under different conditions; the conditions and their com-
plements are denoted by Ci and Ci, respectively, where i ∈ {1,2, ..., 5}.
Initialization: When the jth device joins the network, it stores
its initial transceiver mode Mj
ν0. Furthermore, the jth device
initializes Γj,ξjand ζj, which will be used as error level,
stopping and clock skew control counters, respectively, as:
Γj= 0, ξj= 0 and ζj= 0 (20)
The purpose of using the counters throughout the protocol is to
provide a controlled evolution between the states by comparing
them to pre-defined thresholds.
A. Bias Update State
In this state, the jth device tries to iteratively estimate its
bias to reduce its synchronization error while updating its
clock. Therefore, the device runs Algorithm 1 with u=u1
as long as the following condition is satisfied:
C 1: |c
∆tj[ν]| ≤|∆tj|min ∨ |∆tj|min > λsync
where ∨is the logical disjunction, |∆tj|min is the smallest
value of the weighted average TO encountered up to the νth
iteration and λsync is the pre-defined synchronization threshold.
Note that |∆tj|min can be less than λsync. Hence, if the
synchronization error stays above the desired threshold or it
keeps decreasing in absolute value, then the device does not
change its state.
B. Fixed Bias State
In this state, the absolute value of the synchronization error
of the device stops decreasing. Therefore, the device stops
updating its bias estimate and fixes it to the one that yields
the smallest error |∆tj|min as:
b
βj[ν+ 2] = b
βj[ν](21)
From then on, the device only uses this bias estimate in
Algorithm 1, i.e., (16) is replaced by (21). Meanwhile, the
device increases its error level counter Γjbut only when it
operates as a receiver device:
Γj= Γj+ 1 ,if Mj
ν=RX (22)
In order for a device to leave this state, there are two condi-
tions. The first condition captures the effect of a perturbation in
the system, e.g., a new device joining the network, which can
be detected by checking for a sudden change in the weighted
average TO estimate as follows:
C 2: |c
∆tj[ν]|−|∆tj|min> λsync
In this way, the proposed protocol can operate with dynamic
network size.
Whereas the second condition indicates whether or not the
device deems itself synchronized. Specifically, the decrease
in the weighted average TO of the jth device, i.e., |c
∆tj[ν]|,
might be temporarily due to noise in the TO estimate or some
devices leaving the network, hence, the device should not
consider itself to be synchronized immediately. Instead, the
device observes the change in |c
∆tj[ν]|by using condition
C 2 and assumes synchronization only after this condition is
satisfied for λcons consecutive clock ticks, that is:
C 3: Γj≥λcons
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C. Transition State
In this state the device declares its synchronization status
to the network. Although the device still continues to run
Algorithm 1, it changes its ZC index as follows:
u←u2if Mj
ν=TX (23)
Therefore, if the device in this state operates as a receiver at
the νth clock tick, i.e., Mj
ν=RX, and detects the presence
of the second synchronization signal but not the first one, it
assumes that other devices are also synchronized, hence, it
increases its stopping counter ξjas:
ξj=ξj+ 1 ,D01
ν∨(D00
ν∧ξj>0)
0,D10
ν∨D11
ν
(24)
Note that when (D00
ν∧ξj>0) is satisfied, the receiver
device does not detect any signals, i.e., D00
ν, yet it has a non-
zero stopping counter. Since the device is in the transition
state, this can be interpreted in two ways: either the previ-
ously detected devices left the network, or they switched to
Data Communication State, where they essentially stop their
synchronization process. In both cases, the device continues
to increase its counter.
In contrast, a device operating as a transmitter at the
νth clock tick, i.e., Mj
ν=TX, cannot detect any signals,
therefore, cannot make any decisions about the presence of
the synchronization signals. Hence, we propose to incorporate
the initial transceiver mode Mj
ν0to the decision process.
Specifically, when a device operates as a transmitter at the
νth clock tick and its initial mode was also transmitter, i.e.,
Mj
ν=Mj
ν0=TX, then it increases its stopping counter.
However, a transmitter device still needs to obtain decision
statistics at the νth clock tick (17), therefore, we propose to
rely on the decision statistic from the (ν−1)th clock tick,
where the device was a receiver.
If Mj
ν=TX:
ξj=ξj+ 1 ,(Mj
ν0=TX)∧D01
ν−1
0,(Mj
ν0=TX)∧(D10
ν−1∨D11
ν−1)(25)
Similar to the previous state, perturbations must be de-
tected, i.e., condition C 2. However, since not every device
necessarily has the same synchronization error, there might
be some devices that are still trying to reduce their error by
broadcasting the first signal with ZC index u=u1while not
triggering condition C 2. In this case, when the jth device in
this state detects the first synchronization signal, it resets its
stopping counter, i.e., sets ξj= 0. Therefore, it waits for the
other devices to first synchronize themselves, then switch to
the transition state, where they finally broadcast the second
synchronization signal.
Note that when proceeding to the communication state, the
devices should not lose synchronization with respect to each
other. Specifically, this is important to avoid re-initiating the
synchronization process for timing-advance communication,
which will be explained later. Therefore, the next condition not
only allows devices to terminate the synchronization process,
ideally at the same time, but also enables them to initiate
timing-advance data communication in a distributed manner.
C 4: C4.1 ∨C4.2
C4.1:(Mj
ν=Mj
ν0=RX)∧(ξj> λstop)∨(D00
ν∧ξj>0)
C4.2:(Mj
ν=Mj
ν0=TX)∧(ξj> λstop)
The device switches to the data communication state when its
stopping counter exceeds the pre-defined stopping threshold
λstop if and only if its current transceiver mode at the νth
clock tick, i.e., Mj
ν, is the same as its initial transceiver mode,
i.e., Mj
ν0. Specifically, if the device is a receiver (transmitter)
and the first (second) sub-condition C4.1 (C4.2) is satisfied,
the device stops its synchronization process as a receiver
(transmitter). Hence, the device is aware of whether or not
its clock is advanced or regressed with respect to others when
the synchronization process stops.
Note that in the case of no signal detection with a non-
zero stopping counter, the device can safely assume that the
contributing transmitter devices have already switched to the
data communication state or left the network, hence, it can
proceed to the next state.
D. Data Communication State
In this state, the device can conserve energy by only
operating as a receiver until it initiates data communication.
Therefore, the device sets its transceiver mode to receiver:
Mj
ν←RX (26)
and updates its clock similarly to (11). However, if the device
anticipates data communication, then it relies on how condition
C4 was satisfied, i.e., whether or not its clock is advanced
or regressed at the termination of synchronization process.
Specifically, Mj
ν0=RX means that the device is in the RX
group which is suitable for data reception, while Mj
ν0=TX
that the device in the TX group which is suitable for data
transmission. On the contrary, if the device is in the group
that does not match the anticipated communication type, i.e.,
Mj
ν0=RX but the device has data to transmit or Mj
ν0=TX
but it expects to receive data, then any two devices in this case
would need to re-initiate their own synchronization process for
proper timing-advance, which would cause a network-wide
perturbation. In order to avoid this, the proposed protocol
allows such devices to re-arrange their clocks for proper
timing-advance without actively transmitting and receiving
synchronization signals as follows:
tj[ν+ 1] = (tj[ν] +αjT0−b
βj[ν], Mj
ν0=RX ∧Bj= 1
tj[ν]+αjT0+b
βj[ν], Mj
ν0=TX ∧Bj= 0 (27)
where Bj∈ {0,1}indicates that the jth device anticipates data
transmission or reception, when it is one or zero, respectively.
By applying (27), the jth device uses its own bias estimate to
adjust its clock to approach the vicinity of the clocks of the
opposite group in time as shown in Fig. 6. Note that if the
device applies (27), then it can simply revert this procedure
to return its original TX or RX group after stopping data
communication.
Overall, (27) is useful in terms of extending the achieved
synchronization by allowing devices to use timing-advance
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Fig. 6. After synchronization, the devices are aware the group they are in, i.e.
TX or RX group. Hence, they can re-arrange their clocks by only using their
own bias estimate for timing-advance communication.
communication without unnecessarily exchanging timing
pulses. Therefore, for the proposed protocol, clock-skew is
the only factor affecting re-initialization of the synchronization
process. Indeed, in a practical system, the presence of clock
skew imposes an upper bound on how long devices can stay
synchronized. Since in the communication state, the jth device
does not apply the DPLL clock update in (15), its clock might
diverge from the clocks of other devices after some period of
time due to clock skew. To prevent this, the device keeps track
of how long it stays in this state by increasing its clock skew
control counter at each clock tick as ζj←ζj+1, which is then
compared to clock skew control threshold λskew as follows:
C 5: ζj≥λskew
If ζjexceeds the allowed limit, then the device re-initiates its
synchronization process by resetting its variables as follows:
Γj= 0, ξj= 0 and ζj= 0 (28)
|∆tj|min =c
∆tj[ν](29)
b
βj[ν] = b
βinit (30)
u←u1(31)
Mj
ν←Mj
ν0(32)
We note that the condition C5 is different than Initialization,
where the devices are setting all their variables to 0 and
determining Mj
ν0randomly. However, in C5, the jth device
sets its current transceiver mode to its initial transceiver mode
Mj
ν0. Hence, if the devices switch to the bias update state due
to the condition C5, then re-synchronization should take much
less time since the effect of clock skew cannot cause drastic
deviations on the device clocks.
E. Complexity Analysis
To derive the complexity analysis of the proposed protocol,
we first analyze the required operations in Algorithm 1. When
a device operates as a transmitter at the νth clock tick, i.e.,
Mj
ν=TX, constructing the synchronization signal as in
(3) requires O(2N)operations. Then, the clock update in
(11) only takes one multiplication and one addition, hence,
the complexity is relatively small. If a device operates as
a receiver at the νth clock tick, i.e., Mj
ν=RX, it first
estimates the average TO in (9), which requires computing
a cross-correlation as in (7), and then forming two different
preliminary TO estimates as given by (8). Hence, the total
operations needed for (7) have O(2K)complexity related to
complex multiplications, whereas each preliminary TO esti-
mate, i.e., q±
j[ν], in (8) takes O(8K2)operations. Therefore,
the overall computation complexity of Algorithm 1 at the νth
clock tick is O(16K2+ 2N). Now considering the overall
computation complexity of the proposed protocol, forming
the final average TO estimate in (19) doubles the amount of
operations due to utilization of two distinct ZC sequences,
hence, the computational complexity at the νth clock tick
becomes O(32K2+2N). However, the rest of the computation
complexity of the proposed protocol is relatively small since it
only requires memory registers and comparisons between the
assigned values.
V. SI MU LATI ON RE SU LTS
In this section, the proposed synchronization protocol is
evaluated by means of computer simulations based on METIS
5G channel models and under different conditions of op-
eration, i.e., clock skew, number of devices, and network
topologies, including full mesh and partial mesh.
The complete synchronization protocol for a dense sta-
tionary D2D network is implemented in MATLAB . Unless
otherwise is specified, we consider a network of 14 devices,
where 12 of them initialize at ν= 0 with 2 more devices
joining the network at ν= 33. We use a channel model
according to the Manhattan grid scenario in [30] with Rician
fading for the line of sight path (if present) and Rayleigh
fading for the other paths. The SNR at the input of the
correlator is fixed at 15dB. The rest of the system parameters
are chosen accordingly from [31] and given in Table I.
TABLE I. System parameters
Parameter Description Symbol Value
Number of Devices J2,5,8,14
Scaling Term of DPLL 1
Zadoff-Chu Index u1,u27,13
Zadoff-Chu Sequence Length N839
Clock Period T01ms
Pulse Spacing Tp0.1µs
Sampling Period Ts3ns
Maximum Network Distance d500 m
Operating Frequency f2GHz
Bias Estimate Initialization b
βinit .86 µs
Step Size Initialization γinit 33 ns
Step Size Slope a .98
Step Size Increment b3ns
Probability of Being a Transmitter ptr {0.1,0.5,0.9}
Signal Detection Threshold λdet N
2
Synchronization Error Threshold λsync 1.5µs
Consecutive Clock Tick Threshold λcons 2
Clock Skew Control Threshold λskew 10
Stopping Threshold λstop 2
Number of Resolvable Paths P4
Rayleigh Fading Scaling Parameter - 1
Rician Fading Noncentrality Parameter -1
Rician Fading Scaling Parameter - 1
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A. Clock Phase Convergence
First, we study how fast our protocol reduces the syn-
chronization error compared to [16] under the exact same
network conditions. In Fig. 7a we show a single realization
of the clock phase evolution for the algorithm in [16] where
the devices randomly choose their transceiver mode based
on ptr = 0.5. Similarly in Fig. 7b, the devices employ the
proposed protocol with ptr = 0.5. We note that the algorithm
in [16] transmits synchronization signals for the duration of the
experiment, while the proposed protocol only transmits until
Data Communication State as illustrated in Fig. 7b. As we can
see, during these states, the proposed protocol not only reduces
the difference in relative clock phases faster but also achieves
a smaller deviation. Furthermore, our protocol quickly reacts
to the perturbation that occurs at ν= 33 when new devices
join the network, and compensates for it better than [16].
(a) Random transceiver mode [16] (ptr = 0.5).
(b) Proposed synchronization protocol (ptr = 0.5).
Fig. 7. A single realization of clock phase evolution with a perturbation at
the 33rd clock tick.
Importantly, by using the proposed protocol, the devices
are aware of the global synchronization status which allows
them to terminate the synchronization process simultaneously
at ν= 22 and proceed to data communication state as shown
in Fig. 7b. However, when using the algorithm in [16], the
devices are not aware of the synchronization status of others,
hence, they cannot simultaneously terminate this process and
proceed to data communication as intended.
B. Synchronization Performance before Data Communica-
tion
To quantify the synchronization performance, we introduce
three synchronization performance metrics: maximum, mini-
mum and average synchronization errors at a given clock tick
ν, which take propagation delays into account. These metrics
are defined as follows:
∆tmax
sync [ν] = max
(η,i,j)∈Sνti[η] + τij 1−tj[ν](33)
∆tmin
sync [ν] = min
(η,i,j)∈Sνti[η] + τij 1−tj[ν](34)
∆tavg
sync[ν] = max
j∈Rν1
|Aν
j|X
(η,i)∈Aν
j
(ti[η] + τij1)−tj[ν](35)
In (33) and (34), Sν=Sη∈Vν(η, i, j ) : i∈ Tη, j ∈
Rν,ti[η] + τij1−tj[ν]≤T0
2is the set of triplets con-
taining the indices of transmitters from the ηth clock tick
that are contributing to the received signal of the jth device
at the νth clock tick. Furthermore in (35), we consider the
maximum of the average synchronization error, hence, the set
Aν
j=Sη∈Vν(η, i) : i∈ Tη,ti[η] + τij1−tj[ν]≤T0
2
includes the index of the transmitter devices from the ηth clock
tick detected by the jth device at the νth clock tick.
Fig. 8. Synchronization error comparison; the proposed protocol vs the random
transceiver mode in [16] when J= 14.
In Fig. 8 we compare the synchronization performance
of the proposed protocol to [16] using these metrics. Since
there is no stopping condition in [16], we set λcons =∞
in the proposed protocol for a fair comparison, hence, the
devices only operate in Bias Update State and Fixed Bias
State. Furthermore, in [16], it is stated that the lower the ptr,
the better the synchronization performance. We confirmed this
observation by trying several values of ptr ∈ {0.1,0.5,0.9}and
we found that ptr = 0.1indeed yields the best performance. So,
in Fig. 8 we use ptr = 0.1for the algorithm in [16]. We see that
the proposed protocol reduces the synchronization error and
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reaches the steady-state much faster, while outperforming [16]
in all performance metrics, i.e., (33), (34), (35). In addition,
the proposed protocol adapts to the change in the network
size, which occurs at ν= 33, more rapidly. Furthermore, we
can also observe that there is no fluctuation in the synchro-
nization error as the devices switch from Bias Update State
to Fixed Bias State, which shows that (19) produces reliable
TO estimates.
Fig. 9. Synchronization performance for dynamic and fixed step size under
different bias initializations.
In Fig. 9, we investigate the sensitivity of the proposed bias
estimation in (16) under various initialization of b
βinit
j=d
c
by assuming (±%80) over and underestimates of the average
distance d. We further study the performance of the dynamic
step size γj[ν] = aγj[ν−2] + band compare it to a fixed
step size γj. As shown in Fig. 9, the proposed protocol still
provides an average synchronization error of 3µs even in the
presence of severe errors in the estimates of d. Furthermore,
the dynamic step size leads to faster error reduction and a
lower error floor.
Fig. 10. Verification of the analysis with different number of devices.
In Fig. 10, we verify the analysis of the synchroniza-
tion error reduction by Monte-Carlo simulations for different
number of devices. It is shown that the analysis tracks well
the synchronization error during the steady-state regime. Not
surprisingly, the synchronization performance deteriorates as
the number of devices increases. However, the performance
is better with two devices compared to the setting for mul-
tiple devices since the TO estimate in (9) only includes the
contribution from a single transmitter device.
Fig. 11. Max. and Avg. synchronization performance based on (33) and (35)
for a partial mesh topology for one and eight common devices.
Next, we consider the performance of the proposed protocol
for the partial mesh topology as depicted in Fig. 1, where two
physically separated device groups are synchronizing through
the common devices that act as relaying nodes. In Fig. 11,
we compare our protocol to [16] with ptr = 0.1. We note
that when the number of common devices decreases, the
overall synchronization performance degrades as expected.
More specifically, if the common devices do not operate as
transmitters, which is more likely to happen in the case of
random transceiver mode in [16], especially if ptr is low, then
physically separated devices cannot synchronize themselves.
On the contrary, at each clock tick, the devices always alternate
their transceiver mode in the proposed protocol, hence, even
with a single common device, our protocol attains lower
steady-state error.
C. Timing Error during Data Communication
In Fig. 12, we consider the termination of the synchro-
nization process to let the devices initiate timing-advance
communication in a distributed manner. Thus, unlike Fig.
8, we set λcons = 2 so the devices leave State 2 after
2 consecutive clock ticks, and proceed to the next state,
i.e., Transition State, where they will eventually terminate
the synchronization process. We note that the performance
metrics in (33)-(35) are not useful after the devices terminate
synchronization since Tν=∅. Therefore, we investigate the
timing error between the communicating devices once they
initiate distributed timing-advance communication according
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to (27). To that end, we introduce two performance metrics.
The first one is the maximum timing error over all pairs of
potentially communicating devices:
∆tmax
comm[ν]= max
(η,i,j)∈Cν
ti[η]−κib
βi[η] + τij1−tj[ν] + ϑjb
βj[ν]
(36)
where Cν=(η, i, j )∈ Vν× J × J :i6=j∧ti[η] +
τij1−tj[ν]≤T0
2. In (36), the functions κiand ϑjindicate
whether a device regresses or advances its clock, respectively,
according to (27) and are defined as follows:
κi=0,if Mi
ν0=TX
1,if Mi
ν0=RX
ϑj=0,if Mj
ν0=RX
1,if Mj
ν0=TX
The set Cνin (36) contains all triplets (η, i, j )where jis the
index of a receiver device at clock tick ν, and iis the index
of a device that might transmit to device jfrom the clock tick
η∈ Vν.
The second metric is the maximum over all receivers of the
average timing error between a given receiver and all potential
transmitters:
∆tavg
comm[ν]= max
j∈Rν
1
|Hν
j|X
(η,i)∈Hν
j
(ti[η]−κib
βi[η]+τij1)−tj[ν]+ ϑjb
βj[ν]
(37)
where the set Hν
j=(η, i)∈ Vν×J −{j}:ti[η] + τij 1−
tj[ν]≤T0
2includes the pairs (η, i)where iis the index of
a device that might transmit to device jfrom the clock tick
η∈ Vν.
Fig. 12. Transitioning from synchronization to data communication in full
mesh topology.
Note that in Fig. 12, we compare the timing error in two
cases: with and without clock skew. We see that the timing
error slightly increases in both metrics when the devices stop
synchronization and use the clock arrangements in (27) as
they switch to data communication state at the 25th and 56th
clock ticks. Specifically, for the maximum timing error, the
degradation is higher since the devices synchronized their
clocks based on the weighted average TO and their bias
estimates are the approximation of the average propagation
delay with respect to the multiple transmitters.
In addition, clock skew increases the timing error since the
devices do not employ DPLL update in data communication
state. In Table II, we show the change in the timing error due
to the clock skew for different number of devices. We assume
20ppm crystal accuracy in our simulations. Here, the second
column indicates the timing error right before the synchro-
nization process stops and the third column is the timing error
when data communication state starts. As time elapses without
DPLL clock updates, the timing error increases. Specifically,
after 9T0, the timing error is more than 1.5 times the error
achieved at the end of the synchronization process. Hence, by
using Table II and assuming that the synchronization error
between any device should not exceed 2.5µs, we should
set λskew = 10 to re-initiate the synchronization process
after 10T0. However, if there would not be clock skew, then
the devices would use timing-advance data communication
without needing to re-initiate the synchronization process.
TABLE II. Timing-advance data communication performance with clock skew
Comm. Performance Sync. Stopped After 1T0After 5T0After 9T0
Max Sync. Error (14 Dev.) 1.5µs1.7µs1.98µs2.6µs
Avg Sync. Error (14 Dev.) .41µs.48µs.54µs.61µs
Max Sync. Error (8 Dev.) 1.35µs1.58µs1.79µs2.1µs
Avg Sync. Error (8 Dev.) .39µs.43µs.5µs.59µs
Max Sync. Error (2 Dev.) .1µs.13µs.18µs.21µs
Avg Sync. Error (2 Dev.) .1µs.13µs.18µs.21µs
VI. CO NC LU SI ON
In this paper, we proposed a novel, fully-distributed pulse-
based synchronization protocol for half-duplex D2D commu-
nications in 5G networks, specifically for the out-of-coverage
scenario. The new protocol allows devices to first synchronize
themselves in a distributed manner and then simultaneously
proceed to timing-advance data communication by maintaining
the achieved synchronization. Our protocol also rapidly adapts
the changes in the network size by allowing new devices to
easily synchronize themselves to the network without disrupt-
ing the ongoing synchronization process. Finally, we note that
the proposed protocol is not limited to out-of-coverage D2D
communications and it can be implemented for any distributed
system.
APP EN DI X A
RED UC TI ON O F TIM IN G OFFS ET IN MULTI DE VI CE
SET TI NG
We consider distributed multi-device pulse-based synchro-
nization over multipath channels with half-duplex technology.
Consequently, there is no single timing reference for the
clocks of the devices to converge to. Therefore, we analyze
the reduction of timing offset, which is interpreted as the
synchronization error by the devices. We assume each device
runs the proposed protocol and, based on Algorithm 1, the
devices keep alternating their transceiver mode at each clock
tick νafter initialization. We will use the index jto denote
a receiver device at clock tick νand ito denote a transmit-
ter device. These devices become transmitters and receivers,
respectively, at the next clock tick, i.e., j∈ Rν=Tν+1 and
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i∈ Tν=Rν+1. We further assume that the network remains
constant, i.e., no new devices join or leave the network, and
channels are time-invariant. Therefore, the cardinality of the
sets is |Tν|=Tand |Rν|=R. For simplicity of the
analysis and with no loss of generality, we assume that the
signal contributions are coming from the same time slot of
the receiver. Hence, we have η=νand the set of pairs
formed by the index of transmitter devices and the path indices
contributing to the received signal of the jth receiver device
becomes Dν,ν
j. In addition, we use the superscript Tand Ron
the device clock models to indicate their transceiver mode at
the corresponding clock ticks. Thus, in the high SNR region,
the weighted average TO estimate over multipath channels at
the device j∈ Rνequals to:
c
∆tj[ν] = X
(i,p)∈Dν,ν
j
µijp tT
i[ν] + τijp −tR
j[ν].(38)
For the ith device c
∆ti[ν+ 1] can be defined similarly. Then,
the average TO estimate of the jth device when it becomes a
receiver again is given as follows:
c
∆tj[ν+ 2] = X
(i,p)∈Dν+2,ν+2
j
µijp tT
i[ν+ 2] + τijp −tR
j[ν+ 2]
=X
(i,p)∈Dν+2,ν+2
j
µijp tR
i[ν+1] +αiT0−2b
βi[ν+1] + c
∆ti[ν+1]
+τijp −tT
j[ν+1] −αjT0
=X
(i,p)∈Dν+2,ν+2
j
µijp tT
i[ν]+ 2αiT0−2b
βi[ν+1] + c
∆ti[ν+1]
+τijp −tR
j[ν]−2αjT0+2 b
βj[ν]−c
∆tj[ν](39)
where tT
i[ν+2] and tR
j[ν+2] are obtained from (15) and (11)
at the clock tick (ν+1), respectively, knowing that the receiver
device becomes transmitter and vice versa (cf. Section III-A).
We have Dν,ν
j=Dν+2,ν+2
j, and using (38), the weighted
average TO estimate in (39) is further simplified to:
c
∆tj[ν+ 2] = X
(i,p)∈Dν+2,ν+2
j
µijp c
∆ti[ν+ 1] −2b
βi[ν+ 1] + 2αiT0
+ 2b
βj[ν]−2αjT0(40)
Similarly, the weighted average TO estimate at the ith device
is:
c
∆ti[ν+ 3] = X
(j,p)∈Dν+3,ν+3
i
µijp c
∆tj[ν+ 2] −2b
βj[ν+ 2] + 2αjT0
+ 2b
βi[ν+ 1] −2αiT0(41)
where it is simplified as in (40) by using c
∆ti[ν+ 1] and for
the sets Dν+1,ν+1
i=Dν+3,ν+3
i.
To track the error at the devices when they are receivers,
we can generalize (40) for the device j∈ Rνas follows:
y[ν]= Wx[ν−1] −2r[ν−1] + 2aT0+ 2p[ν−2] −2bT0(42)
whereas the generalization of (41) for the device i∈ Rν+1 is
given as:
x[ν+1] = Vy[ν]−2p[ν] + 2bT0+ 2r[ν−1] −2aT0(43)
where y[ν]and x[ν+ 1] are the vectors that contain the
weighted average TO estimates of the receiver devices in the
sets Rνand Rν+1, respectively. Here, the notation [·]>is the
transpose of a vector. In addition, Wand Vare the matri-
ces with compatible dimensions that contain the normalized
channel weights of the jth and the ith devices, i.e., µijp and
µjip , respectively. Note that the row sums of Wand Vare
normalized to one and since their product is a square matrix,
it becomes a right stochastic matrix [32]. This feature will be
used later in the proof. Furthermore, p[ν]and bare the vectors
that contain the biases and clock skews of the devices in Rν,
whereas r[ν−1] and aare the vectors that contain the biases
and clock skews of the devices in Rν−1.
For simplicity of the analysis, we assume fixed step sizes as
in (16), hence, online bias estimates are generalized for both
j∈ Rνand i∈ Rν+1 as follows:
p[ν] = p[ν−2] + msgn(y[ν−2])
r[ν+ 1] = r[ν−1] + nsgn([x[ν−1]) (44)
where is the Hadamard product, mand nare the vectors
with compatible lengths, which contain the step sizes of the
jth and the ith devices in the sets Rνand Rν+1, respectively,
To continue the analysis, we assume that the synchroniza-
tion error of each device is greater than the synchronization
threshold chosen in the network, i.e., |y[ν]|> λsync and
|x[ν+ 1]|> λsync, where the absolute values and comparisons
are element-wise. In other words, C1 is satisfied, hence, the
devices should try to decrease their errors until C1 is satisfied,
where they stop updating their bias estimates and maintain the
reduced error level.
In order to show the reduction in absolute value of the
synchronization error, we compare the weighted average TO
estimates at two consecutive clock ticks, i.e., |y[ν+ 2]|and
|y[ν]|as νincreases. Hence, by using (43) in (42) at the
(ν+ 2)th clock tick, we obtain the following:
y[ν+ 2] = Wx[ν+ 1] −2r[ν+ 1] + 2aT0+ 2p[ν]−2bT0
=WVy[ν]−2(WV−I)p[ν]−2Wn sgn(x[ν−1])
+2(WV −I)bT0(45)
where Iis the identity matrix with compatible size. By
subtracting y[ν]from the both sides, we further obtain:
y[ν+ 2] = y[ν] + WV−I
q[ν]
z}| {
y[ν]−2p[ν]+2bT0(46)
+ 2Wr[ν−1] −r[ν+ 1]
=y[ν]+WV−Iq[ν]−2Wnsgn(x[ν−1]).
The multiplication of (WV −I), which is a zero row-sum
matrix, with a vector that has identical elements yields a zero
vector. In this case, if all the elements in q[ν]approaches the
same values as νincreases, then (WV−I)q[ν]→0, which is
a zero vector. In order to prove that, we can re-arrange q[ν]
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by using (42) and (43) through recursive iterations as follows:
q[ν] =
q1[ν]
z }| {
WVWV
q2[ν]
z }| {
y[ν−4] −2p[ν−4] + 2bT0
−2WVWm sgn(x[ν−5])
−2WVn sgn(y[ν−4])
−2Wm sgn(x[ν−3])
−2nsgn(y[ν−2]) (47)
Note that by multiplying the same stochastic matrices recur-
sively, i.e., WVWV..., we obtain a right stochastic matrix
that has identical elements in each column. Then, multipli-
cation of WVWVq2[ν] = q1[ν]≈q1[ν], q1[ν], ..., q1[ν]>
approximates a vector that has identical elements. Thus,
WV −Iq1[ν]≈0. In addition, the remaining terms in
q[ν]include the fixed step sizes, which are the same for
each device, and the sign of the error remains unchanged1.
Therefore, they can be re-arranged such that -2(WV−I)z=0,
where z=Wmsgn(x[ν−5]) = Wmsgn(x[ν−3]). Hence,
we can conclude that (WV −I)q[ν]→0as νincreases and
we left with the following:
y[ν+ 2] = y[ν]−2Wnsgn(x[ν−1]) (48)
Note that sign of y[ν]is dominated by Wx[ν−1] as given
in (42). Then, sgn(y[ν]) = sgn(Wx[ν−1]), or equivalently
sgn(x[ν−1]) = sgn(W†y[ν]), where W†is the pseudo-inverse
of W. By multiplying both sides in (48) with W†, we obtain
the following:
y0[ν+ 2] = y0[ν]−2nsgn(y0[ν]) (49)
where y0[ν] = W†y[ν]. Since the step-sizes are always pos-
itive, we can conclude that the quantity in (49) is reducing
by 2nat each clock tick. In other words, the synchronization
error decreases in absolute value, that is |y0[ν+ 2]|<|y0[ν]|,
where the vectors are compared element-wise.
Finally, when the desired synchronization error is achieved,
i.e., C1 is satisfied, the devices switch to Fixed Bias State,
hence, stop updating their bias estimates. In this case, r[ν+
1] = r[ν−1] or equivalently the term nsgn(x[ν−1]) is
no longer present in (44). Hence, from (48), we can conclude
that the synchronization errors are reached a steady-state level
that is smaller than or equal to the pre-defined synchronization
error, i.e., y[ν+ 2] = y[ν]≤λsync as ν→ ∞.
APP EN DI X B
RATE OF TO REDUCTION
We consider a simplified scenario consisting of two devices
labeled as D1 and D2 communicating over a flat reciprocal
channel with propagation delay τ. We assume that the devices
follow the alternating transceiver mode and based on ptr, D1
operates as a transmitter, whereas D2 is a receiver at the νth
clock tick. We further assume that the relative clock skew
is negligible, i.e., ∆α12 =α1−α2= 0. Hence, the first
TO estimate of D2 is equal to c
∆t12[ν] = t1[ν]−t2[ν] + τ.
1Synchronization error must be decreased to zero before changing its sign
However, c
∆t12[ν]is the initialization error due to misaligned
clock phases. To observe the effect of the protocol, we consider
the next TO estimate of D2, which occurs at the (ν+2)th clock
tick (see Section III.A) as follows:
c
∆t12[ν+ 2] = t1[ν+ 2] −t2[ν+ 2] + τ
=t1[ν+1] +α1T0+c
∆t21[ν+ 1]−2b
β1[ν+1]
−t2[ν+1] −α2T0+τ
=t1[ν+1] −t2[ν+1]−τ+c
∆t21[ν+ 1]+2τ−2b
β1[ν+1]
= 2(τ−b
β1[ν+ 1]) (50)
Note that the corresponding clock simplifications, i.e., t1[ν+2]
and t2[ν+ 2], are derived respectively from (11) and (15) for
a transmitter and a receiver device when = 1. We further
note that b
β1[ν+ 1] = b
βinit and without loss in generality, we
assume c
∆t12[ν+ 2] >0. Similarly, at the (ν+ 4)th clock tick,
D2 estimates its TO again and it is given by
c
∆t12[ν+ 4] = 2(τ−b
β1[ν+ 3])
= 2(τ−b
β1[ν+ 1] −γsgn(c
∆t21[ν+ 3])
=c
∆t12[ν+ 2] −2γsgn(c
∆t21[ν+ 3]) (51)
where the bias estimate of D1, i.e., b
β1[ν+ 3], is simplified
accordingly from (16) and we assume a fixed step size, i.e.,
γ, for updating the bias estimate. Note that TO estimate
at each device must decrease to zero before changing sign,
consequently, we have sgn(c
∆t21[ν+ 3]) = sgn(c
∆t12[ν+
4]) = sgn(c
∆t12[ν+ 2]) = sgn(c
∆t12[ν]). Since we assume
c
∆t12[ν+ 2] >0, we can simplify (51) as c
∆t12[ν+ 4] =
c
∆t12[ν+ 2] −2γ. Finally, the change in the TO estimate of D2
for two consecutive clock ticks where it operates as a receiver
is given by:
m=c
∆t12[ν+ 4] −c
∆t12[ν+ 2]
(ν+ 4) −(ν+ 2) −1=−2γ(52)
Fig. 13. Synchronization performance based on the scenario in Appendix B
with remaining parameters chosen from Table I.
In Fig. 13, we plot the maximum synchronization error (33)
against a straight line with negative slope as given by (52).
The results show a very close match between the two curves,
thereby supporting our analysis. For comparison, we also plot
the synchronization error with adaptive step size.
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APP EN DI X C
EXP EC TATION OF TO EST IM ATE
We assume two devices labeled D1 and D2 communication
over a flat reciprocal channel with propagation delay τand the
relative clock skew is negligible, i.e., ∆α12 =α1−α2= 0. In
order for a device, say D2, to estimate the synchronization for
updating its clock, it should operate as a receiver, while D1
should be a transmitter or vice versa. Therefore, the probability
of this event is pe= 2ptr(1 −ptr). Then, the synchronization
error at the νth clock tick for D2 is ∆t12[ν] = t1[ν]+τ−t2[ν],
whereas for D1, it is ∆t21[ν] = t2[ν] + τ−t1[ν]. Hence,
the expected initial synchronization error can be given as
∆θ=|t1[ν]−t2[ν]|=|θ1−θ2|=|∆θ12|=|∆θ21 |.
Now, based on the alternating transceiver mode and the
clock updates according to (11) and (15), where we assume
b
β12[ν] = b
β21[ν]≈τ∀ν, the expected TO estimate at D2
(similar for D1) is equal to:
Ec
∆t12[ν]=(1 −pe)ν
|{z }
P1
+pe(1 −)(ν−1)
| {z }
P2
+
ν−1
X
k=1
(1 −pe)kpe(1 −)(ν−1−k)
| {z }
P3
∆θ, ∀ν≥1
(53)
Here, P1is the probability that the devices never operate at the
opposite modes, which is the worst scenario since they cannot
detect the error and update their clocks. Furthermore, P2is
the probability that the devices operate on the opposite modes
at the first clock tick and then start alternating between them,
hence, it is the best scenario. Finally, P3is the probability that
the devices start alternating their mode and update their clocks
once they operate at the opposite modes, which is a mixed
scenario. We numerically verify the validity of this analysis
for values of ptr ∈[0,1] and ∈(0,1], but did not to include
the results in the paper due to space limitations.
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