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The resilience of quantum random access memory to generic noise
Connor T. Hann,1, 2 Gideon Lee,1, 2, 3 S. M. Girvin,1, 2 and Liang Jiang1, 2, 4
1Departments of Applied Physics and Physics, Yale University, New Haven, Connecticut 06520, USA
2Yale Quantum Institute, New Haven, CT 06520, USA
3Yale-NUS College, 16 College Avenue West, 138527, Singapore
4Pritzker School of Molecular Engineering, The University of Chicago, Chicago, Illinois 60637, USA
Quantum random access memory (QRAM)—memory which stores classical data but allows queries
to be performed in superposition—is required for the implementation of numerous quantum algo-
rithms. While naive implementations of QRAM are highly susceptible to decoherence and hence
not scalable, it has been argued that the bucket brigade QRAM architecture [Giovannetti et al.,
Phys. Rev. Lett. 100 160501 (2008)] is highly resilient to noise, with the infidelity of a query scal-
ing only logarithmically with the memory size. In prior analyses, however, this favorable scaling
followed directly from the use of contrived noise models, thus leaving open the question of whether
experimental implementations would actually enjoy the purported scaling advantage. In this work,
we study the effects of decoherence on QRAM in full generality. Our main result is a proof that this
favorable infidelity scaling holds for arbitrary error channels (including, e.g., depolarizing noise and
coherent errors). Our proof identifies the origin of this noise resilience as the limited entanglement
among the memory’s components, and it also reveals that significant architectural simplifications
can be made while preserving the noise resilience. We verify these results numerically using a novel
classical algorithm for the efficient simulation of noisy QRAM circuits. Our findings indicate that
QRAM can be implemented with existing hardware in realistically noisy devices, and that high-
fidelity queries are possible without quantum error correction. Furthermore, we also prove that the
benefits of the bucket-brigade architecture persist when quantum error correction is used, in which
case the scheme offers improved hardware efficiency and resilience to logical errors.
I. INTRODUCTION
Numerous quantum algorithms have been proposed
that claim speedups over their classical counterparts.
Such algorithms typically require that classical data—
constituting a classical description of the problem
instance—be made available to a quantum processor.
Frequently, theoretical constructions called oracles (or
black boxes) are invoked to provide this access [1]. For
example, oracles can provide quantum access to classi-
cal descriptions of Hamiltonians in quantum simulation
algorithms [2–7], and they are used to encode classical
datasets into quantum states in quantum machine learn-
ing algorithms [8–12]. In practice, however, providing
quantum access to classical data can be nontrivial, and
in order to claim a genuine quantum speedup it is crucial
that the details of how such oracles are implemented be
specified [13].
Quantum random access memory (QRAM) [14–19] is
a general-purpose architecture for the implementation of
quantum oracles. QRAM can be understood as a general-
ization of classical RAM; the classical addressing scheme
in the latter is replaced by a quantum addressing scheme
in the former. More precisely, in the case of classical
RAM, an address iis provided as input, and the RAM
returns the memory element xistored at that address.
Analogously, in the case of QRAM, a quantum super-
position of different addresses |ψiniis provided as in-
put, and the QRAM returns an entangled state |ψouti
where each address is correlated with the corresponding
memory element,
|ψini=
N−1
X
i=0
αi|iiA|0iB
QRAM
−−−−→ |ψouti=
N−1
X
i=0
αi|iiA|xiiB,(1)
where Nis the size of the memory, and the superscripts
Aand Brespectively denote the input and output qubit
registers. (In this work, we restrict our attention to the
case where the memory elements are classical, though
in principle QRAM can also be used to query quantum
data.) Remarkably, QRAM can perform operation (1) in
only O(log N) time, albeit at the cost of O(N) ancillary
qubits. The short query time, together with the gener-
ality of operation (1), makes QRAM appealing for use
in many quantum algorithms, especially those that re-
quire O(log N) query times in order to claim exponential
speedups. Further, QRAM can serve as an oracle im-
plementation in quantum algorithms for machine learn-
ing [8–12,20–22], chemistry [7,23], and a host of other
areas [24–32].
The idea of QRAM has faced skepticism, however, and
the question of whether QRAM can be used to facilitate
quantum speedups, either in principle or in practice, has
not been definitively settled (see, e.g., Refs. [13,33], or
the excellent summary in Ref. [12]). A central practical
concern is the seemingly high susceptibility of QRAM
to decoherence [14,17]. As we discuss below, naive im-
plementations of QRAM perform operation (1) with an
infidelity that scales linearly with the size of the memory.
Such implementations are not scalable. As the memory
arXiv:2012.05340v1 [quant-ph] 9 Dec 2020
2
size increases, the infidelity grows rapidly without quan-
tum error correction, yet the overhead associated with
error correction can quickly become prohibitive because
all O(N) ancillary qubits need to be corrected [18].
Refs. [14,15] proposed the so-called “bucket-brigade”
QRAM architecture as a potential solution to this de-
coherence problem, though this solution has also faced
skepticism. Proponents argue that the bucket-brigade
QRAM is highly resilient to noise, in that it can perform
operation (1) with an infidelity that scales only polylog-
arithmically with the size of the memory. This favor-
able scaling could allow for high-fidelity queries of large
memories without the need for quantum error correction,
thereby mitigating the aforementioned scalability prob-
lem. This noise resilience, however, has only been derived
for contrived noise models that place severe constraints
on the quantum hardware [14,15,17], thus casting doubt
on the viability of the bucket-brigade architecture. In-
deed, while several proposals for experimental implemen-
tations of QRAM have been put forth [15,16,34–36],
to our knowledge there has yet to be an experimental
demonstration of even a small-scale QRAM [37]. Absent
from this debate has been a fully general and rigorous
analysis of how decoherence affects the bucket-brigade
architecture.
In this work, we study the effects of generic noise on
the bucket-brigade QRAM architecture. Our main re-
sult is that the architecture is far more resilient to noise
than was previously thought (our main scaling results are
summarized in Table I). We rigorously prove that the
infidelity scales only polylogarithmically with the mem-
ory size even when all components are subject to arbi-
trary noise channels, and we verify this scaling numeri-
cally. Remarkably (and perhaps counter-intuitively), this
scaling holds even for noise channels where the expected
number of errors scales linearly with the memory size.
Our analysis reveals that this remarkable noise resilience
is a consequence of the limited entanglement among the
memory’s components. We leverage this result to show
that significant architectural simplifications can be made
to the bucket-brigade QRAM, and that so-called “hy-
brid” architectures [18,19,32,38], which implement (1)
with fewer qubits but longer query times, can also be
made partially noise resilient. We also show that these
benefits persist when quantum error correction is used.
Importantly, the present work shows that a noise-resilient
QRAM can be constructed from realistically noisy de-
vices, paving the way for small-scale, near-term experi-
mental demonstrations of QRAM.
This paper is organized as follows. In Section II, we
give a detailed review of QRAM architectures, and an in-
tuitive explanation for the noise-resilience of the bucket-
brigade scheme is provided. We prove the noise-resilience
of bucket-brigade architecture in Section III for generic
mixed-unitary error channels, with the full proof for ar-
bitrary channels given in Appendix D. In Section IV,
we propose and implement an efficient classical algo-
rithm for the simulation of noisy QRAM circuits, and
Architecture Infidelity scaling
Fanout QRAM (Sec. II)Nlog N
Standard BB QRAM (Secs. II,III) log2N
Two-level BB QRAM (Sec. V) log3N
Hybrid fanout (Sec. VI)Nlog N+Mlog2N
Hybrid BB (Sec. VI)Mlog2N
TABLE I. Infidelity scalings of QRAM architectures. Nde-
notes the size of the classical memory being queried, and
bucket-brigade is abbreviated as BB. The first three architec-
tures have circuit depth O(log N) and require O(N) qubits.
For the hybrid architectures, M≤Nis a tunable parame-
ter that determines the circuit depth, O(Mlog N), and the
number of qubits, O(N/M + log N).
we use this algorithm to confirm that the bucket-brigade
QRAM is resilient to realistic errors. Next, in Section V,
we show that the use of three-level memory elements
in the original bucket-brigade architecture is superflu-
ous and that the architecture can be significantly simpli-
fied (while maintaining noise resilience) by instead using
two-level memory elements. In Section VI, we show that
the bucket-brigade architecture can also be employed to
imbue hybrid architectures with partial noise resilience.
In Section VII, we prove that error-corrected implemen-
tations of the bucket-brigade architecture are resilient to
logical errors, and we discuss the practical utility of error-
corrected QRAM. Finally, in Section VIII we conclude by
discussing potential applications.
II. QUANTUM RANDOM ACCESS MEMORY
In both classical and quantum random accesses mem-
ories, each location in memory is indexed by a unique
binary address. To read from the memory, an address
is provided as input, and the memory element located
at that address is returned at the output. In the clas-
sical case, transistors are the physical building blocks of
the addressing scheme: they act as classical routers, di-
recting electrical signals to the memory location specified
by the address bits. Analogously, in the quantum case,
quantum routers are the fundamental building blocks of
the addressing scheme. As shown in Fig. 1(a), a quan-
tum router is a device that directs incident signals along
different paths in coherent superposition, conditioned on
the state of a routing qubit. For example, if the routing
qubit is in state |0i(|1i), then a qubit incident on the
router is routed to the left (right). If the routing qubit
is in a superposition, then the incident qubit is routed
in both directions in superposition, becoming entangled
with the routing qubit in the process. Quantum routers
can also be understood through the language of quantum
circuits [Fig. 1(b)]; the routing operation is a unitary that
can be implemented via a sequence of controlled-SWAP
3
gates (Fredkin gates).
In this section, we review two QRAM architectures
based on quantum routers: the fanout architecture [39]
and the bucket-brigade architecture [14,15]. The fanout
architecture is highly susceptible to noise, and we dis-
cuss it in order to illustrate how the lack of noise-
resilience fundamentally limits QRAM scalability. The
noise-resilience of the bucket-brigade architecture is the
main focus of this work.
A. Fanout QRAM architecture
A QRAM can be constructed out of quantum routers
as shown in Fig 1(c) (see Ref. [39], Chapter 6). A col-
lection of routers is arranged in a binary tree, with the
outputs of routers at one level of the tree acting as in-
puts to the routers at the next level down. The memory
is located at the bottom of the tree, with each of the N
memory cells connected to a router at the bottom level.
To query the memory, all routing qubits are initialized
in |0i, and a register of log Naddress qubits is prepared
in the desired state (in this work, all logarithms are base
2). All routing qubits at level `of the tree are then
flipped from |0ito |1iconditioned on the `-th address
qubit. To retrieve the memory contents, a so-called bus
qubit is prepared in the state |0iand injected into the
tree at the top node. The bus follows the path indicated
by the routers down to the memory. Upon reaching a
memory cell, the contents of that memory cell are copied
into the state of the bus (see Appendix Bfor details).
Note that because we consider classical data, the data
can be copied without violating the no-cloning theorem.
For simplicity, we assume that each memory element xi
is a single bit, in which case a single bus qubit suffices to
store the memory element (higher-dimensional data can
be retrieved using multiple bus qubits). Finally, the bus
is routed back out of the tree via the same path, and
all routers are flipped back to |0iin order to disentangle
them from the rest of the system.
Importantly, because the routers operate coherently,
the above procedure allows one to query multiple mem-
ory elements in superposition, as in (1). If the address
qubits are prepared in a superposition of different compu-
tational basis states, the bus is routed to a superposition
of different memory locations.
In this architecture, the total time required to per-
form a query (or, equivalently, the circuit depth) is only
O(log N). The ability to perform queries in logarithmic
time can be crucial for algorithms that invoke QRAM in
order to claim exponential speedups over their classical
counterparts. However, this speed comes at the price of a
high hardware cost. To perform operation (1), both the
fanout and bucket-bridgade architectures require O(N)
ancillary qubits to serve as routers. We discuss practical
concerns associated with the high hardware cost more
thoroughly in Sections VII and VIII. For context, we
note that there is a space-time trade-off in implementing
operation (1). At the other extreme, there are circuits
which implement (1) in O(N) time using only O(log N)
qubits [5,40,41], and several implementations that lever-
age this trade-off have also been proposed [18,19,32,38].
We discuss the effect of decoherence on these implemen-
tations in detail in Section VI.
The fanout architecture is impractical due to its high
susceptibility to decoherence. Each address qubit is max-
imally entangled with all routers at the respective level
of the tree (similar to a GHZ state), so the decoherence
of any individual router is liable to ruin the query. As an
example, suppose that the routers are subject to ampli-
tude damping errors. The loss of an excitation from any
router at level `collapses all other level-`routers—and
the `-th address qubit—to the |1istate. Any terms in the
superposition where the `-th address qubit was in the |0i
state prior to the error are thus projected out, thereby
reducing the fidelity by a factor of 2 on average.
More generally, suppose that each router suffers an er-
ror with probability εat each time step during the query.
The final state Ω of the full system (address, bus, and
routers) can then be written as a statistical mixture
Ω = (1 −ε)T(N−1) Ωideal +. . . (2)
where Ωideal is the error-free state, T=O(log N) is the
number of time steps required to perform a query, and
“. . .” denotes all states in the mixture where at least one
of the N−1 routers has suffered an error. We define the
query fidelity as
F=hψout|TrR(Ω) |ψouti,(3)
where TrRindicates the partial trace over the routers.
The routers are traced out because only the address
and bus registers are passed on to whatever algorithm
has queried the QRAM; the routers are ancillae whose
only purpose is to facilitate the implementation of oper-
ation (1).
As illustrated by the amplitude-damping example, the
problem with the fanout implementation is that the no-
error state Ωideal is generally the only state in the mix-
ture (2) with high fidelity. Neglecting the low-fidelity
states, the query infidelity scales as
1−F∼εNT, (4)
to leading order in ε. We refer to this linear scaling of
the infidelity with the memory size as unfavorable be-
cause error probabilities ε1/NT are required to per-
form queries with near-unit fidelity. This stringent re-
quirement severely constrains the size of fanout QRAMs.
For example, error probabilities ε∼10−3would restrict
the maximum size of a high-fidelity fanout QRAM to
less than N∼100 memory cells. While quantum er-
ror correction can be used to suppress the error rates in
principle, the additional hardware overhead can be pro-
hibitive [18] because all O(N) routers must be error cor-
rected (see Section VII for a more detailed discussion of
4
Incident qubit
Router
Left output Right output
Incident
Router
Left
Right
(a) (b)
(c) (d)
Route left Route right
FIG. 1. QRAM implementations. (a) Quantum router. The router directs an incident qubit |biat its top port out of either
the left or right output ports conditioned on the state |aiof the router. When |ai=|0i(|1i), the incident qubit leaves out
of the left (right) port. (b) Example of a quantum circuit that implements the routing operation using two controlled-SWAP
gates, one conditioned on the control being |0i(open circle) and the other conditioned on the control being |1i(filled circle).
(c) Fanout QRAM. Each address qubit controls the states of all routers within the corresponding level of the binary tree. A
bus qubit injected at the top node then follows the path (blue) to the specified memory element. (d) Bucket-brigade QRAM,
utilizing routers with three sates: wait |Wi, route left |0i, and route right |1i. The address qubits themselves are routed into
the tree, carving out a path to the memory.
error correction and the associated overhead). Thus, be-
cause of its high susceptibility to decoherence, the fanout
architecture is not regarded as scalable.
B. Bucket-brigade QRAM architecture
In Ref. [14], two modifications to the fanout architec-
ture were proposed, and it was argued that the modified
architecture, termed the “bucket-brigade” [Fig. 1(d)], is
highly resilient to noise. The first modification is that
the two-level routing qubits are replaced with three-level
routing qutrits. In addition to the |0i(route left) and |1i
(route right) states, each router also has a third state,
|Wi(wait). We refer to the states |0i,|1ias active, and
the state |Wias inactive. We assume that all routers are
initialized in the |Wistate, and that the action of the
routing operation [Fig. 1(b)] is trivial when the routing
qutrit is in the |Wistate. (In Section V, we show that
these assumptions may be relaxed, but we make them
here for concreteness.) Each router’s incident and out-
put modes are also now taken to be physical three-level
systems, and each address qubit is encoded within a two-
level subspace of a physical three-level system.
The second modification is that the address qubits are
themselves routed into the tree during a query. When an
address qubit encounters a router in the |0i(|1i) state,
it is routed to the left (right) as usual. When an ad-
dress qubit encounters a router in the |Wistate, the
states of the router and incident mode are swapped, so
that the router’s state becomes |0i(|1i) when the inci-
dent address was |0i(|1i). The physical implementation
described in Ref. [14] provides a helpful example to visu-
alize how these operations could be realized: the authors
envisage the routers as three-level atomic systems, with
the address qubits encoded in the polarization states of
flying photons. (Note that the two polarization states
constitute a two-level subspace of a physical three-level
system, since the photonic mode may also be in the vac-
uum state.) When a photon encounters an atom in the
|Wistate, it is absorbed, and in the process it excites
the atom to the |0ior |1istate conditioned on its polar-
ization. When subsequent photons encounter the excited
atom, they are routed accordingly. These operations can
also be described using the conventional quantum circuit
model, and in Appendix Awe provide a full circuit dia-
gram.
To query the memory, the address qubits are sequen-
tially injected into the tree at the root node. The first
address qubit is absorbed by the router at the root node,
exciting it from |Wito the {|0i,|1i} subspace in the pro-
cess. The second address qubit is routed left or right, con-
ditioned on the state of the router at the root node. The
state of the first address qubit thereby dictates the rout-
ing of the second. The second address is subsequently
absorbed by one of the routers at the second level of the
tree. The process is repeated, with the earlier addresses
controlling the routing of later ones, carving out a path of
active routers from the root node to the specified memory
element. Once all address qubits have been routed into
5
the tree, the bus qubit is routed down to the memory and
the data is copied as before (see Appendix B). Finally,
the bus and all address qubits are routed back out of
the tree in reverse order to disentangle the routers. Here
again, we emphasize that multiple memory elements can
be queried in superposition, as in (1), because all routing
operations are performed coherently.
C. Noise resilience: overview and conceptual
explanation
The bucket-brigade architecture is clearly resilient to
certain types of noise. For example, Ref. [17] studied the
bucket-brigade QRAM with routers subject to |0i ↔ |1i
bit-flip errors, with the |Wistates assumed to be error
free. In this case, the expected number of errors is only
εlog N, because only the log Nactive routers are prone
to errors [42]. The expected number of errors also scales
with log Nfor the error model considered in Refs. [14–
16], where gates involving inactive routers are assumed
to be error free.
For these error models, the query infidelity is
1−F∼εT logαN. (5)
to leading order in ε, where αis some constant, and we
recall that T=O(log N) is the number of time steps.
We refer to this logarithmic scaling of the infidelity with
the memory size as favorable because queries can be per-
formed with near-unit fidelity so long as the error rate
satisfies ε1/T logαN. This is a much more forgiving
requirement; memories of exponentially larger size can
be queried relative to the fanout architecture. Indeed,
the exponential improvement in scalability suggests that
quantum error correction is not required to query large
memories with high fidelity, provided physical error rates
are sufficiently low.
Unfortunately, the above error models can be poor ap-
proximations of the noise in actual quantum hardware.
In these contrived models, inactive routers are assumed
to be completely free from decoherence. More realis-
tically, all routers will be prone to decoherence, inde-
pendent of whether they are active or inactive. For ex-
ample, though several proposals for experimental imple-
mentations of the bucket-brigade scheme have been put
forth [15,16,34–36], none have proposed a method of
engineering routers that are free from decoherence when
inactive. While one can conceive of implementations in
which inactive routers have decoherence rates which are
nonzero but far smaller than those of active routers, it is
not obvious whether such implementations would enjoy
the favorable infidelity scaling. Indeed, Ref. [14] con-
jectured that decoherence of inactive routers could sig-
nificantly increase the infidelity in this case, owing to
the exponentially larger number of inactive routers. Fur-
thermore, Refs. [14,17] portray the favorable infidelity
scaling as a direct consequence of the assumption that
inactive routers are decoherence-free.
It is thus natural to ask whether the favorable scal-
ing still holds when inactive routers are not assumed
to be decoherence-free. Relaxing this assumption causes
the expected number of errors to increase exponentially,
from O(log N) to O(N). Because the expected number
of errors in the fanout architecture is also O(N), one
might naively expect that the favorable infidelity scal-
ing no longer holds. However, in the next section we
prove that this is not the case. Perhaps surprisingly, the
infidelity of the bucket-brigade architecture still scales fa-
vorably despite the exponential increase in the expected
number of errors. Moreover, the favorable scaling holds
for arbitrary error channels.
The noise-resilience of the bucket-brigade architecture
can be understood intuitively as a consequence of the
minimal entanglement among the routers, see Fig. 2.
Suppose one queries all memory locations in equal su-
perposition. Then in both the fanout and bucket-brigade
architectures, all of the routers are entangled. However,
the degree to which each router is entangled with the rest
of the system is quite different between the two architec-
tures. This difference can be quantified by computing
the entanglement entropy for a given router
S(ρ) = −Tr [ρlog ρ] (6)
where ρis the reduced density matrix of the router, ob-
tained by tracing out the rest of the system. In the fanout
architecture, each router is maximally entangled with the
rest of the system; the reduced density matrix is the max-
imally mixed state ρ=I/2 (recall the fanout architecture
employs two-level routers), for which S(ρ) = 1. In con-
trast, in the bucket-brigade architecture, the entangle-
ment entropy of a router depends on its location within
the tree. A router at level `(0-indexed) of the tree is
only active in N2−`of the Ndifferent branches of the
superposition. As a result, the entanglement entropy de-
creases exponentially with depth, S(ρ)∼2−`. Routers
deeper down in the tree are nearly disentangled from the
system, and their decoherence only reduces the query
fidelity by an exponentially decreasing amount. Thus,
despite the fact that exponentially many such errors typ-
ically occur, the overall fidelity can remain high. More
precisely, if we posit that the infidelity associated with
an error in a router at level `scales as ∼2−`due to the
limited entanglement, and that εT 2`such routers suffer
errors on average, then the total infidelity scales as
1−F∼
log N
X
`=1 2−`εT 2`=εT log N. (7)
The infidelity scales only logarithmically with Nbecause
the exponential increase in the expected number of errors
with `is precisely cancelled by the exponential decrease
in the infidelity associated with each. We rigorously jus-
tify these claims in the next section.
6
+ + + + + ...
FIG. 2. Conceptual picture of noise resilience. Each ket represents the state of the QRAM when a different memory element is
queried, with the superposition of kets representing a superposition of queries to different elements. When a router rsuffers an
error (red lightning bolt), it corrupts only the subset of queries where ris active (indicated by thick red kets); other queries in
the superposition succeed regardless. Because most routers are only active in a small fraction of queries, most queries succeed
and the total infidelity is low.
III. PROOF OF NOISE RESILIENCE
In this section, we prove that the query infidelity of
the bucket brigade architecture is upperbounded by
1−F≤AεT log N, (8)
where T=O(log N) is the time required to perform a
query, εis the probability of error per time step, and A
is a constant of order 1. This bound holds even when all
Nmemory elements are queried in superposition, and it
holds for arbitrary error channels, including, e.g., depo-
larizing errors and coherent errors. Moreover, through-
out this paper we assume no special structure in the clas-
sical data xi, so our bounds hold independent of the data.
We begin by defining our error model. We suppose
that each routing qutrit is subject to an error channel in
the form of a generic completely-positive trace-preserving
map,
ρ→ E(ρ) = X
i
KmρK†
m,(9)
where the Kraus operators Kmobey the completeness
relation PmK†
mKm=I. The error channel is ap-
plied simultaneously to all routers at discrete time steps
throughout the query (see Eq. (15) below). In Ap-
pendix D, we prove that the bound (8) holds for arbitrary
error channels of the form (9). For the sake of brevity
and simplicity, however, here we restrict our attention
to channels where (i) there is a no-error Kraus operator,
K0, that is proportional to the identity, and (ii) the re-
maining Kraus operators are proportional to unitaries,
K†
mKm∝I. Under these restrictions,
E(ρ) = (1 −ε)ρ+X
m>0
KmρK†
m,(10)
for some ε∈[0,1]. An operational interpretation of this
channel is that one of the errors Km>0occurs with proba-
bility ε, and no error occurs with probability 1−ε. Exper-
imentally relevant examples include bit-flip, dephasing,
and depolarizing channels. The restriction to this form
of mixed-unitary channel allows us to make two assump-
tions that greatly simplify the proof: (i) the probability
that an error occurs is independent of the router state,
and (ii) the no-error backaction K0∝Iis trivial.
It is important to note that this error model only de-
scribes decoherence of the routing qutrits; a router’s in-
cident and output modes may also decohere, and there
may be errors in the gates that implement the routing
operation. At the end of this section, we prove that the
bound (8) still holds when including these other errors,
but we neglect them for now to simplify the discussion.
The proof proceeds by direct calculation. To bound
the infidelity, we first write the final state Ω as a sum
over different error configurations,
Ω = X
c
p(c)Ω(c),(11)
where an error configuration cspecifies which Kraus op-
erator is applied to each router at each time step. Here,
p(c) is the probability of configuration c, and the pure
state Ω(c) = |Ω(c)ihΩ(c)|is the corresponding final state
of the system (both quantities are defined more formally
below). The fidelity is thus given by,
F=X
c
p(c)F(c),(12)
where
F(c) = hψout|TrRΩ(c)|ψouti(13)
is the query fidelity of the state Ω(c). Our approach is
to place an upper bound on the infidelity by deriving an
upper bound on 1 −F(c).
Let us formally define Ω(c) and p(c). A QRAM query
consists of O(N) routing operations [Fig. 1(b)] performed
in a predetermined sequence. By design, many of these
operations commute and can be performed in parallel, so
that the entire operation can be written as a quantum
circuit with depth T=O(log N) (see Appendix Afor
circuit diagram). More precisely, operation (1) can be
written as,
|ψouti |Wi =UT. . . U2U1|ψini |Wi ,(14)
where |Wi =|Wi⊗(N−1) is the initial state of the
routers, and Utis a constant-depth circuit. Now, let
Kc(r,t)denote the Kraus operator applied to router r
at time step t, and define the composite Kraus opera-
tor Kc(t)=NN−1
r=1 Kc(r,t)[see Fig. 3(a)]. The final state
7
(a) (b)
Good BadBad
FIG. 3. Error configurations. (a) Example composite Kraus
operator Kc(t). The single-router Kraus operators Kc(r,t)
comprising the tensor product Kc(t)are arranged geometri-
cally according to the routers on which they act. Branches
of the tree are classified as either good or bad according to
the locations of the errors Km>0. (b) Query to an element
k6∈ g(c). Routers are labelled with their ideal, error-free
states, and routers outlined in red suffer errors. Because one
of the active routers suffers an error, the query is liable to fail.
|Ω(c)iis
|Ω(c)i=1
pp(c)UTKc(T). . . U1Kc(1)|ψin i|Wi,(15)
The requirement that |Ω(c)iis normalized defines the
probability p(c) of obtaining state Ω(c) in the mix-
ture (11). Note that Pcp(c) = 1 follows from the Kraus
operators’ completeness relation.
For a given error configuration c, it is convenient to
classify branches of the tree as either good or bad, de-
pending on whether errors Km>0are ever applied to the
routers in the branch [Fig. 3(a)]. More precisely, let i
denote the set of all routers in the i-th branch of the
tree (corresponding to address i), and let cdenote the
set of all routers which have an error Km>0applied to
them at some time step. A branch iis defined to be
good if i∩c=∅, and bad otherwise. To keep the nota-
tion simple, we use g(c) to denote set of good branches.
As illustrated in Fig. 3(b), queries to addresses i6∈ g(c)
are liable to fail because they rely on routers that suffer
errors.
The main observation underlying our proof is that the
propagation of errors is constrained when memory ele-
ments ∈g(c) are queried. Roughly speaking, errors do
not propagate from bad branches into good branches.
More precisely, for any i, j ∈g(c), errors do not propa-
gate into branch jduring a query to element i. We illus-
trate this fact with two examples, shown in Figs. 4(a,b).
In general, errors in the bad branches can propagate.
They can even propagate into an output mode of a router
rin branch j∈g(c), but they can never propagate into
branch j. Fig. 4(a) shows an example of how such an
error propagates through r’s routing operation in the
case where a memory element i6=jis queried. Be-
cause j∈g(c), r’s routing qutrit suffers no errors and
is thus in |Wi. The action of the routing operation is
trivial for a router in |Wi, so the error does not propa-
gate to other modes. (We reiterate that we are assuming
error-free gates; gate errors are discussed at the end of
Incident
Router
Left
Right
Incident
Router
Left
Right
(a)
(b)
Incident
Router
Left
Right
(c)
FIG. 4. Error propagation. (a,b) Constrained propaga-
tion during queries to elements ∈g(c). The error in the left-
most router can propagate upward into the left output of the
router indicated by the dashed box. The circuits on the left
show that the error does not propagate further, regardless of
whether the router is inactive (a) or active (b). In the cir-
cuit diagrams, red boxes denote errors Km>0, and the red
arrows indicate how the error propagates (i.e. how the error
transforms under conjugation by the routing operation). (c)
Error propagation is not constrained during queries to ele-
ments 6∈ g(c). Note that the state of the router dictates how
the error propagates in these examples.
this section.) Similarly, Fig. 4(b) shows an example of
how errors propagate in the case where jis queried. The
error-free routing qutrit is in |1i, so the routing operation
acts non-trivially on only the incident and right output
modes. The error in the left output mode does not prop-
agate upward. For comparison, in Fig. 4(c) we illustrate
that the propagation of errors is not constrained in this
way when memory elements k6∈ g(c) are queried. As
an aside, we note that the constrained error propagation
can be understood as a sort of error transparency [43–
45]: when elements ∈g(c) are queried, the errors in the
bad branches commute with the routing operations in the
good branches.
The constrained propagation of errors has two impor-
tant consequences. The first is that a query to memory el-
ement i∈g(c) always succeeds, meaning that the address
and bus registers are in the desired state |iiA|xiiBat the
end of the query. This follows from the fact that errors
cannot propagate to any of the routers in branch i. The
second consequence is that, if multiple memory elements
i, j, . . . ∈g(c) are queried in superposition, the address
8
and bus registers are disentangled from the routers at the
end of the query. This follows from the fact that errors
are restricted to propagate within the bad branches, and
their propagation is unaffected by routers outside these
branches. Figs. 4(a,b) provide an example. As a result,
even though errors can propagate non-trivially among
the bad branches during the query, the final state of the
routers is independent of which memory element in g(c)
is queried.
It follows that the final state |Ω(c)ican be written as
|Ω(c)i=|good(c)i+|bad(c)i,(16)
with
|good(c)i=
X
i∈g(c)
αi|iiA|xiiB
|f(c)iR.(17)
Here, |f(c)iRdenotes the final state of the routers with
respect to the good branches, and |bad(c)icontains the
i6∈ g(c) terms. We now use the expression (16) to place
a lower bound on F(c). First notice that
F(c)≥ |hψout, f (c)|Ω(c)i|2,(18)
which can be obtained by performing the partial trace in
Eq. (13) using a basis that contains the state |f(c)iand
neglecting the contributions from other states. Then,
defining Λ(c) as the weighted fraction of good branches,
Λ(c) = hgood(c)|good(c)i=X
i∈g(c)|αi|2(19)
we have that
hψout, f (c)|good(c)i= Λ(c) (20)
|hψout, f (c)|bad(c)i| ≤ 1−Λ(c).(21)
To obtain the inequality (21) we have used the fact that
|Ω(c)iis normalized and that hgood(c)|bad(c)i= 0. The
latter follows from the orthogonality of different initial
address states, hi|jiA= 0 for i6=j, and the fact that
all subsequent operations, including the Kraus operators,
are unitary and thus preserve inner products (this fol-
lows from our earlier restriction to mixed-unitary error
channels; general channels are covered by the proof in
Appendix D). Plugging Eqs. (16), (20) and (21) into the
bound (18) and applying the reverse triangle inequality
allows us to bound the infidelity as a function of Λ(c),
F(c)≥((2Λ(c)−1)2,Λ(c)≥1/2,
0,Λ(c)<1/2.(22)
To proceed further, we compute the expected fraction
of good branches, E(Λ), where the expectation value is
taken with respect to the distribution of error configu-
rations, i.e. E(f) = Pcp(c)f(c). This expectation value
can be computed recursively for trees of increasing depth.
Let Ed(Λ) denote the expected fraction of good branches
for a depth-dtree. For a depth-1 tree, expected frac-
tion is equivalent to the probability that the lone router
never suffers an error, E1(Λ) = (1−ε)T. For deeper trees,
the expected fraction of error-free routers at each level is
(1 −ε)T, so we have the recursive rule
Ed+1(Λ) = (1 −ε)TEd(Λ).(23)
Applying this rule to the initial condition E1(Λ), we ob-
tain
Elog N(Λ) = (1 −ε)Tlog N.(24)
We can now combine the above results to bound the
infidelity. We have that
F=E(F)≥E(√F)2(25)
≥[2Elog N(Λ) −1]2(26)
=2(1 −ε)Tlog N−12,(27)
where the second inequality follows from (22) under the
assumption that E(Λlog N)≥1/2. Applying Bernoulli’s
inequality yields the desired result,
1−F≤4εT log N, (28)
which holds for εT log N≤1/4. We stress that this
bound holds even when all Nelements are queried in
superposition.
We offer three remarks on the proof. First, we reit-
erate that while the above proof holds only for mixed-
unitary error channels, in fact the favorable infidelity
scaling holds for arbitrary error channels, which we prove
in Appendix D. Second, the favorable scaling can be in-
terpreted as a consequence of the limited entanglement
among the routers, as discussed in Section II. This lim-
ited entanglement manifests in Eqs. (16) and (17). The
fact that a router at level `is active in only N2−`of the
Nbranches implies both that the router’s entanglement
entropy decreases exponentially with `, and that only
N2−`branches are corrupted when it suffers an error.
The third remark is that the proof can be easily ex-
tended to cover a variety of other of errors, including
initialization errors and gate errors. In the case of ini-
tialization errors, one supposes that each router has some
probability εof not being initialized to |Wiprior to the
query. Such errors can be viewed as router errors of the
form (9) that occur duing the 0-th time step. As such,
they are also covered by the proof provided one replaces
T→T+1 in the equations above. In Section V, we show
that, in fact, one can make an even stronger statement:
the infidelity scales favorably even when the QRAM is
initialized in an arbitrary state. In the case of gate er-
rors, a faulty implementation of the routing operation
can be described without loss of generality as a composi-
tion D◦R, of some error channel Dfollowed by the ideal
routing operation R. Provided that D’s Kraus operators
are proportional to unitaries, and that there is a no-error
9
Kraus operator proportional to the identity, then Dcan
also be written in the form (10), and the proof proceeds
as above. Note that the propagation of errors is still
constrained in the case of gate errors because all routing
gates in good branches are error-free by construction.
IV. CLASSICAL SIMULATION OF NOISY
QRAM CIRCUITS
In this section, we verify the bound (28) through nu-
merical simulation of noisy QRAM circuits. While full
state vector simulations require exp(N) memory and
quickly become intractable as the QRAM size grows, our
simulations are enabled by a novel classical algorithm
with space and time complexity poly(N).
The main observation underlying the algorithm is that
any quantum circuit consisting of the following elements
can be simulated efficiently classically: state prepara-
tion in the computational basis, and gates from the set
{SWAP, controlled-SWAP}. Such circuits are essentially
classical—the system begins in a definite computational
basis state, and the SWAP-type gates act only as permu-
tations so that the system remains in a computational
basis state through every step of the circuit. The sim-
ulation proceeds simply by tracking the (classical) state
of the system. Furthermore, for initial states that are
a superposition of polynomially-many different computa-
tional basis states, it follows from linearity that the action
of any circuit composed of these SWAP-type gates can
also be efficiently simulated. QRAM circuits can thus be
efficiently simulated because they consist of SWAP-type
gates acting on O(N) qubits or qutrits, and the system
is initialized in a superposition of only O(N) computa-
tional basis states (one for each address). In fact, QRAM
circuits are examples of so-called efficiently computable
sparse (ECS) operations, whose efficient classical simula-
tion is described in Ref. [46].
For context, we note that this approach is similar in
spirit to the Gottesman-Knill theorem [47], which states
that any Clifford circuit with preparation and measure-
ment in the computational basis can be simulated clas-
sically in polynomial time. Because QRAM circuits nec-
essarily employ non-Clifford gates (controlled-SWAP),
however, the theorem does not directly apply. Still, the
similarities are apparent: restricting the allowed gates
and state preparations enables an efficient classical de-
scription of the system, making efficient simulation pos-
sible.
In addition, for a wide variety of error models, noisy
QRAM circuits can be simulated efficiently using Monte
Carlo methods. To simulate noisy circuits, the space of
error configurations is randomly sampled according to
the distribution p(c). For each sampled configuration
cfrom a set of samples S, we compute the final sys-
tem state |Ω(c)i, and we obtain the fidelity by averaging
F=1
|S|Pc∈SF(c). This sampling procedure is efficient
provided that two criteria are satisfied: first, that the
state |Ω(c)iis efficiently computable, and second, that
sampling from p(c) is efficient. A sufficient condition
for satisfying these two criteria is that the error channel
maps computational basis states to other computational
states, i.e., the channel’s Kraus operators Kmsatisfy
Km|ii∝|i0i,(29)
for all m, and where |ii,|i’i ∈ {|0i,|1i,|Wi} are com-
putational basis states. The first criterion is satisfied
because Eq. (29) guarantees that a QRAM circuit inter-
spersed with applications of the Kraus operators Kmis
still ECS. The second criterion is satisfied because the
distribution p(c) can be sampled efficiently by applying
errors independently to each router (with appropriate
probability) at each time step as the simulation proceeds.
In detail, suppose that at time tthe system is in a state
|ψ(t)ithat is a superposition of polynomially-many com-
putational basis states,
|ψ(t)i=X
{i1,...iN−1}∈C
αi|i1, i2, . . . , iN−1i,(30)
where |iridenotes the state of router r, and the cardi-
nality of the set Cis O(polyN). The probability that a
Kraus operator Kmis applied to router ris
Tr K†
mKmρr,(31)
where ρr(t) = Tr¯r(|ψ(t)ihψ(t)|) is the reduced density
matrix of router r, with Tr¯rdenoting the partial trace
over the rest of the system. Eq. (29) guarantees that this
probability is efficiently computable, so sampling from
the possible errors at time tis also efficient. This sam-
pling procedure is repeated at each time step in order to
sample from the full error configuration.
We apply this algorithm in order to compute the query
infidelity for QRAM circuits with routers subject to a va-
riety of noise channels. The results (Fig. 5) confirm that
the QRAM query infidelity scales favorably in the pres-
ence of realistic noise channels acting on all of the mem-
ory’s components. We stress that, for such channels, the
expected number of errors generally scales linearly with
N. Results for qutrit depolarizing, bit-flip, and dephas-
ing channels are shown in panels (a), (b), and (c), respec-
tively (see Appendix Cfor Kraus decompositions for each
channel). These channels are all of the form (10), so the
query fidelity is subject to the bound (28). The numerical
results are all clearly consistent with this bound, and the
expected 1 −F∝log2Nscaling is evident on the log-log
scale. In panels (d) and (e), we show numerical results
for qutrit decay and heating channels (Appendix C). We
find that the query fidelities for these channels also sat-
isfy the bound (28). Note, however, that the decay and
heating channels are not mixed-unitary channels, so the
query fidelities are subject to the general bound derived
in Appendix D, rather than Eq. (28).
10
10-2
10-1
10-3
10-4
1 105
Depolarizing
(a)
1 105
(b)
Bit-flip
Depth
1 105
(c)
Dephasing
1 105
(d)
Damping
1 105
(e)
Heating
Depth Depth Depth Depth
FIG. 5. Favorable error scaling. For a variety of error channels, the query infidelity (black dots) is calculated numerically
and plotted as a function of the tree depth log N(note the logarithmic scaling on both axes). The region defined by the upper
bound (28) is shown in gray in each plot. Plotted infidelities are averages over many randomly generated binary data sets
{x0,...xN−1}. Each such data set is generated by randomly choosing each xito be 0 or 1 with equal probability. Error bars
are smaller than the dot size. The error rate for all plots is ε= 10−4.
V. NOISE RESILIENCE WITH TWO-LEVEL
ROUTERS
In Section III, we proved that the query infidelity of
the bucket-brigade QRAM scales favorably, even when
inactive routers are subject to decoherence. It is thus
natural to ask whether distinguishing between active and
inactive routers is useful, and in fact whether the use
of three-level routers is necessary in the first place. In
this section, we show that the answer is no—the query
fidelity still scales only logartihmically for QRAMs con-
structed from noisy two-level routers. Furthermore, the
arguments presented to justify this claim reveal that the
noise resilience also persists when the QRAM is initial-
ized in an arbitrary state, and when the routing circuit
[Fig. 1(b)] is modified. Taken together, the results in
this section show that the noise resilience of the bucket-
brigade scheme is a robust property that is insensitive to
implementation details. They also show that existing ex-
perimental proposals [16,34] employing two-level routers
are noise-resilient.
Consider a QRAM constructed from routers with only
two states: |0i(route left) and |1i(route right). Routers
are thus always active. For concreteness, we suppose
that the routing operation is implemented using the cir-
cuit in Fig. 1(b), and that all routers are initialized in
|0i, though these assumptions can be relaxed. Unfor-
tunately, the proof from Section III cannot be directly
applied to show that the query fidelity also scales favor-
ably in this case. The proof fails in the case of two-level
routers because the propagation of errors is no longer so
highly constrained. Recall that in the case of three-level
routers, errors do not propagate from bad branches into
good branches. More precisely, for any i, j ∈g(c), errors
do not propagate into branch jwhen branch iis queried.
This is not the case for two-level routers: while errors
do not propagate into branch iwhen branch iis queried,
they can propagate into other branches j, as illustrated
in Fig. 6. Because of this difference, when multiple mem-
ory elements i, j, . . . ∈g(c) are queried in superposition,
it is not guaranteed that the address and bus registers
will be disentangled from the routers at the end of the
query. Thus, Eqs. (16) and (17) no longer hold. Instead,
(a)
(b)
Incident
Router
Left
Right
Incident
Router
Left
Right
FIG. 6. Error propagation with two-level routers. (a) A
query to memory element j∈g(c), with an error Km>0ap-
plied to the red-outlined router. The circuit on the left shows
how the error propagates through the router indicated by the
dashed box. In this case, the error does not propagate into
branch j. (b) A query to a different memory element i∈g(c).
In this case, the error propagates upward into branch j, in
contrast to the situation in (a).
the final state |Ω(c)iis given by
|Ω(c)i=X
i∈g(c)
αi|iiA|xiiB|fi(c)iR+|bad(c)i,(32)
where |fi(c)idenotes the now address-dependent final
state of the routers, and |fi(c)i 6=|fj(c)iin general. As
a result, the i, j ∈g(c) terms are no longer guaranteed to
be in coherent superposition after tracing out the routers.
Rather, the final state of the address-bus system is li-
able to contain an incoherent mixture of these terms.
That is, the final density matrix can contain terms of the
form |i, xiihi, xi|and |j, xjihj, xj|without |i, xiihj, xj|
or |j, xjihi, xi|terms. This loss of coherence reduces the
fidelity.
We now proceed to estimate this reduction in fidelity.
We find that the reduction is mild, such that the infi-
delity still scales only polylogarithmically with the mem-
11
ory size. Our approach is to isolate the subset of branches
in g(c) for which the sort of damaging error propagation
described above does not occur. Explicitly, we define the
subset ˜g(c)⊆g(c) as the largest subset such that for any
i, j ∈˜g(c) errors do not propagate into branch jduring
a query to element i. We then have that |fi(c)i=|fj(c)i
by the same argument as given in Section III. It follows
that, if multiple memory elements in ˜g(c) are queried in
superposition, the address and bus registers will be dis-
entangled from the routers at the end of the query.
Having defined ˜g(c) as the subset of good branches
without damaging error propagation, we are free to define
all other branches as bad and then proceed exactly as in
Section III. In particular, we analogously define
˜
Λ(c) = X
i∈˜g(c)|αi|2(33)
as the weighted fraction of good branches, and
F≥[2E(˜
Λ) −1]2,(34)
follows as the analog of Eq. (26). Because ˜g(c)⊆g(c),
we have that
E(˜
Λ) = (1 −δ)E(Λ),(35)
for some δ∈[0,1] to be determined. Proceeding as
in Section III, it follows that the infidelity satisfies the
bound
1−F≤4εT log N+ 4δ(36)
assuming εT log N+δ≤1/4.
We can estimate δby computing the average proba-
bility that errors propagate from bad branches into good
branches. More specifically, we compute the probability
that an error propagates into a branch i∈g(c) when
some other branch j∈g(c) is queried. Suppose that a
router rsuffers an error at time step t, and let Pr→i(t) de-
note the probability of this error propagating into branch
i. Then to leading order in ε,
δ=εX
r,t
Pr→i(t) + O(ε2),(37)
which can be understood as the total probability that an
error occurs and propagates into branch i. To compute
Pr,t Pr→i(t) to leading order, we observe that errors are
generally free to propagate from a router’s left output
to its input, as illustrated in Fig. 6(b). This is because,
by default, all routers are initialized in |0i, for which the
routing operation swaps the states at the incident and
left ports. In contrast, for an error to propagate upward
from a router’s right output, an additional error would
be required to flip the router from |0ito |1i. Thus, only
the errors which can reach branch iby propagating up-
ward exclusively through the left outputs of routers con-
tribute to Pr,t Pr→i(t) to leading order in ε. A conser-
vative overestimate is thus obtained by first enumerating
all routers rthat are connected to ithrough the left ports
of other routers, then pessimistically taking Pr→i(t) = 1
for each. There are at most log2Nsuch routers, so
δ≤εT log2N+O(2).(38)
Substituting this expression into Eq. (36), we obtain
1−F.4εT log N+ log2N.(39)
Here we use the symbol .to contrast this bound with
Eq. (28); we proved the bound (28) rigorously, while we
have obtained Eq. (39) through a scaling argument. As
such, it is appropriate to focus only on the scaling of
Eq. (39). We see that the infidelity still scales only poly-
logarithmically with the memory size, indicating that
a bucket-brigade QRAM constructed from noisy two-
level routers also exhibits noise resilience. Note, how-
ever, that the infidelity here scales with log3N[recall
T=O(log N)], as opposed to log2Nin the case of three-
level routers. Both scalings are still favorable accord-
ing to our definition, but the discrepancy indicates that
three-level routers impart better noise resilience than
two-level routers.
We simulate noisy QRAM circuits with two-level
routers in order to verify this noise resilience. Simula-
tion results are shown in Fig. 7. For all noise channels
simulated, the query infidelity is observed to scale poly-
logarithmically with the memory size, as expected. More-
over, the observed scaling exponents are ≤3 in all cases,
consistent with the pessimistic 1 −F∼log3Nscaling
given above.
It is interesting to note that two-level routers are more
resilient to certain noise channels than others, as quan-
tified by the observed differences in scaling exponents.
For example, the infidelity under the dephasing channel
is observed to scale approximately as 1 −F∼log2N.
This relatively mild scaling can be explained by the fact
that dephasing errors do not flip the routers from one
computational basis state to another, so the final state
of the routers is the same for every address (up to a pos-
sible relative phase), i.e., |hfi(c)|fj(c)i| = 1 for all i, j .
Hence ˜g(c) = g(c) and the bound from Section III applies.
For the other channels, ˜g(c)6=g(c) in general, consistent
with observed scaling exponents >2. The case of ampli-
tude damping is also interesting to consider: the expected
number of errors for this channel is only εT log Nbecause
only log Nexcitations are injected into the tree. Because
T=O(log N), one expects the infidelity to scale with
log2N. The observed slope of 1.86 is somewhat smaller
owing to the fact that, in our simulations, excitations are
only susceptible to damping while they reside in the tree.
The scaling argument presented in this section also suf-
fices to show that the noise resilience persists in two other
interesting situations: when the QRAM is initialized in
an arbitrary state, and when the routing circuit is mod-
ified. Regarding initialization, observe that the above
argument is straightforwardly modified to cover the case
where all routers are initialized in |1irather than |0i.
12
10-2
10-1
10-3
10-4
Bit-flip Dephasing Damping Heating
1 105
(a)
Depolarizing
slope = 2.42
1 105
(b)
1 105
(c)
1 105
(d)
1 105
(e)
slope = 2.57
Depth Depth Depth Depth Depth
slope = 1.97 slope = 1.86 slope = 2.68
FIG. 7. Favorable error scaling with two-level routers. For a variety of error channels, the query infidelity (black dots) is
calculated numerically and plotted as a function of the tree depth log N. Linear fits for each data set are shown as dashed lines,
with the corresponding slopes given on each plot. Fits are performed only on data points with log N≥3 so that the slopes are
not skewed by finite-size effects at small log N. Slopes ≤3 are consistent with the scaling argument in the text. The error rate
for all plots is ε= 10−4.
Indeed, such an argument holds regardless of whether a
given router is initialized in |0ior |1i. It follows that
the query infidelity scales favorably when the QRAM is
initialized in an arbitrary state [48] (though some ad-
ditional care must be taken when copying data to the
bus—see Appendix Bfor details). This observation has
great practical utility, as it means that QRAM can be
constructed even from physical components that cannot
reliably be initialized to a particular state.
Regarding modifications to the routing circuit, it is
helpful to consider an example. In Ref. [34] a modi-
fied routing circuit was proposed in which one of the
controlled-SWAP gates in Fig. 1(b) is replaced by a
SWAP gate. This modification has nontrivial effects on
how errors propagate. With the modified circuit, errors
can propagate from bad branches into good branches
even when three-level routers are used. However, this
is the same sort of damaging error propagation as is il-
lustrated in Fig. 6. Indeed, from the perspective of error
propagation, the effect of this modification to the rout-
ing circuit is equivalent to replacing three-level routers
with two-level routers. Accordingly, the argument above
can be directly applied to show that the favorable scaling
persists with the modified circuit. This example demon-
strates that noise resilience is not a specific feature of the
routing circuit [Fig. 1(b)].
Taken together, the results from this section demon-
strate that the noise resilience of the bucket brigade ar-
chitecture is a robust property that is insensitive to im-
plementation details. This observation affords a great
deal of freedom to experimentalists in deciding how the
routers and routing operations could be implemented in
practice.
VI. HYBRID ARCHITECTURES
The bucket-brigade architecture allows one to perform
queries in O(log N) time using O(N) qubits. This allo-
cation of resources represents one extreme; at the other
extreme are architectures [5,40,41] that perform queries
in O(Nlog N) time using O(log N) qubits. In fact, there
exists a family of architectures that interpolate between
01234567
Add.
Bus
FIG. 8. QROM circuit. The circuit implements operation (1)
by iterating over all Npossible states of the address register.
The j-th gate flips the state of the bus qubit if the address
register (Add.) is in state |jiand xj= 1, otherwise the gate
acts trivially.
these two extremes to leverage this space-time trade-
off [18,19,32,38]. We refer to these as hybrid architec-
tures, and in this section we study their noise resilience.
We find that hybrid architectures can be imbued with
a partial noise resilience when they employ the bucket-
brigade QRAM as a subroutine. As a result, these hybrid
bucket-brigade architectures can have significantly higher
query fidelities than other architectures that require the
same resources.
One of the primary benefits of the bucket-brigade
architecture is that queries can be performed in only
O(log N) time. These fast query times are essential for
algorithms that must rapidly load large classical data
sets in order to claim exponential speedups over their
classical counterparts, e.g., quantum machine learning
algorithms [8–12]. However, the O(N) hardware over-
head that enables such fast queries is practically daunt-
ing, and not all algorithms require such fast queries in
the first place. In algorithms that only require compara-
tively small data sets to be loaded, e.g. simulating local
Hamiltonians [2–7], slower query times can be sufficient.
Circuits that use fewer qubits at the price of longer query
times are better suited for such algorithms.
Fig. 8provides a straightforward example of such a
circuit. To query a memory of size N, a sequence of N
multiply-controlled Toffoli gates is applied, where each
gate has log Ncontrols (the address qubits) and one
target (the bus qubit). The circuit sequentially iter-
ates over all Npossible addresses, flipping the bus qubit
13
conditioned on the corresponding classical data. The
circuit requires only O(log N) qubits, but it has depth
O(Nlog N), since each multiply-controlled Toffoli gate
can be performed in depth O(log N) [49]. Adopting the
nomenclature introduced in Ref. [5], we refer to such cir-
cuits as Quantum Read-Only Memory (QROM). We note
that this circuit can be further optimized to reduce the
depth, as shown in Ref. [5]. We omit these optimizations
for simplicity, as they do not affect our main conclusions
concerning the effects of noise.
More generally, circuits can be constructed that trade
longer query times for fewer qubits by combining QROM
and QRAM, as shown in Fig. 9. We introduce a tunable
parameter M≤N, defined to be a power of 2. That is,
M= 2m, with man integer in the interval [0,log N]. The
idea is to divide the full classical memory into Mblocks,
each with N/M entries. These blocks are queried one-
by-one using a QRAM of size N/M concatenated with
a QROM-like iteration scheme. The total hardware cost
of the scheme is O(log N+N/M), comprising O(log N)
qubits for the address and bus registers and O(N/M)
ancillary qubits for the QRAM. The total circuit depth
is O(Mlog N) because each of the Miterations in the
circuit can be performed in depth O(log N). There-
fore, by tuning the parameter M, one can interpolate
between large-width, small-depth circuits like QRAM,
and small-width, large-depth circuits like QROM. The
hybrid circuit reduces to QRAM for M= 1, and QROM
for M=N. We note that the circuits we introduce in
Fig. 9are very similar to those in Refs. [18,19,32,38].
The main difference is that our circuits explicitly invoke
QRAM as a subroutine, which makes the analysis of their
noise resilience more straightforward.
Let us consider the effects of noise on these circuits.
We first consider QROM, then turn to the hybrid cir-
cuits. One can easily observe that QROM does not pos-
sess any intrinsic noise resilience. For example, when
all memory elements are queried in equal superposition
[αi= 1/√Nin Eq. (1)], a single dephasing error at any
location in the QROM circuit reduces the query fidelity
to 0. The effects of bit flips are similarly detrimental,
assuming there is no contrived redundancy in the clas-
sical data. More generally, we can follow the approach
of Section III and express the QROM query fidelity as
F=Pcp(c)F(c), where the error configuration cspeci-
fies which Kraus operators are applied at each location in
the circuit, and F(c) is the final state fidelity of the ad-
dress and bus registers given configuration c. In the case
of QROM, only the error configuration with no errors is
guaranteed to have unit or near-unit fidelity in general
[50]. There are O(Nlog2N) possible error locations, so
it follows that the QROM query infidelity scales as
1−FQROM ∼εN log2N, (40)
to leading order. Therefore, QROM is not noise re-
silient, since near-unit query fidelities generally require
ε1/N, neglecting logarithmic factors.
Similarly, the hybrid circuits do not exhibit noise re-
silience when the QRAM subroutines are implemented
with the fanout architecture. Recall from Section II that
the fanout architecture is not noise resilient; only the
fanout’s no-error configuration is guaranteed to have high
fidelity in general. Because neither QROM nor the fanout
QRAM are noise resilient, only the no-error configuration
of the hybrid fanout circuit is guaranteed to have high fi-
delity. Since the number of possible error locations is
O(Mlog N(log N+N/M)), the query fidelity scales as
1−Fhybrid,fanout ∼ε(Nlog N+Mlog2N),(41)
to leading order. Here again, error rates ε1/N are re-
quired for near-unit query fidelity, neglecting logarithmic
factors.
In contrast, the hybrid circuits do exhibit partial
noise resilience when the QRAM subroutines are imple-
mented with the bucket-brigade architecture. Because
the bucket-brigade QRAM is resilient to noise, error
configurations with errors occurring exclusively in the
QRAM subroutines can still have high fidelities. We can
obtain a lower bound on the query fidelity by neglecting
all other configurations. Doing so allows us to bound the
query fidelity by a product of two factors
Fhybrid,BB &(1 −ε)O(Mlog2N)×(1 −ε)O(Mlog Nlog N/M)
(42)
The first factor is simply the probability that no errors
occur outside the QRAM. The second factor is the ex-
pected fraction of error-free branches within the QRAM
(each branch contains log N/M routers, and there are
T=O(Mlog N) possible time steps at which errors
may occur). We have related this expected fraction to
Fhybrid−BB by the same argument as in Section III. Thus,
to leading order,
1−Fhybrid,BB .εM log N(log N+ log N/M),(43)
∼εM log2N. (44)
Note that we have not kept track of prefactors since we
are only interested in how the infidelity scales; a strict
upper bound could be rigorously derived following the
approach of Section III. Near-unit query fidelities only re-
quire error rates ε1/M, neglecting logarithmic factors
(cf. the ε1/N requirement for the other cases). Be-
cause M≤N, the infidelity of the hybrid bucket-brigade
architecture scales more favorably than both QROM and
the hybrid fanout architecture. Of course, the extent of
the scaling advantage depends on M. For example, if
one chooses M=√N, so that the number of qubits and
circuit depth are comparable, then the hybrid bucket-
brigade architecture yields a quadratic improvement in
the infidelity scaling. Note that we assume three-level
routers above for simplicity; for two-level routers, one
should replace log N/M →log2N/M in the above ex-
pressions, in accordance with the argument from Sec-
tion V.
14
QRAM QRAM
Add.
Bus ...
FIG. 9. Hybrid circuit. All M= 2mpossible states of the first maddress qubits are iterated over sequentially, as in QROM.
Conditioned on these qubits, the remaining address qubits are used to query an (N/M)-cell classical memory via QRAM. In
the circuit shown, log N= 4 and m= 2. The boxes labelled QRAM implement (1), using either the fanout or bucket-brigade
architecture. At the j-th iteration (j∈[1, M ]), the data elements {x[(j−1)N/M ],...,x[j(N/M)−1] }are queried by the QRAM.
Only the first two iterations are shown. The circuit depth is O(Mlog N), and the circuit uses O(N/M + log N) qubits, which
includes the O(N/M) ancillary qubits required by the QRAM (not shown). The initial state of the QRAM can be arbitrary
(see Section V).
VII. ERROR-CORRECTED QRAM
In this section, we show that the benefits of the bucket
brigade scheme persist when quantum error correction is
used. When the bucket-brigade QRAM is implemented
using error-corrected routers and fault-tolerant routing
operations [39,51], the logical query infidelity scales only
polylogarithmically with the memory size. Thus, error-
corrected implementations of the bucket-brigade scheme
can offer improved fidelity or reduced overhead relative
to other implementations. In practice, these improve-
ments may be tempered by the overhead associated with
the fault-tolerant implementation of the routing opera-
tions, and we discuss the utility of the bucket-brigade
architecture in light of such considerations.
While we have shown that the query infidelity of the
bucket-brigade scheme scales favorably with the memory
size, strategies to further suppress the infidelity are desir-
able, and quantum error correction provides one possible
approach. Indeed, error correction may be required in
cases where the physical error rate cannot be made suffi-
ciently small, or when many queries must be performed
in sequence. For example, Ref. [17] argued that error
correction is likely to be needed for any algorithm that
requires a number of QRAM queries that scales super-
polynomially in log N, e.g., Grover’s algorithm [24].
It is thus natural to ask whether an error-corrected
bucket brigade QRAM offers any advantages over other
architectures. Indeed, this question was previously con-
sidered in Ref. [17], where the authors argue in the neg-
ative. Their argument is based on the canonical attribu-
tion [10,12,14–17] of the bucket brigade’s noise resilience
to the limited number of active routers. Error-corrected
routers must be considered active, they argue, and so the
number of active routers is the same in both the fanout
and bucket brigade schemes. Hence, the bucket brigade
scheme was not believed to provide any advantage if error
correction were used.
As we have shown, however, the noise resilience of the
bucket brigade scheme is not a function of the number
of active routers, but rather a function of the limited
entanglement among the routers. As a direct corollary
of this result, we find that, in fact, the benefits of the
bucket brigade scheme do persist when error correction
is used. The proof from Section III is agnostic to whether
the routers are composed of uncorrected physical qubits
or error-corrected logical qubits, provided that uncor-
rectable logical errors occur independently with some
probability εL(which can be guaranteed by implement-
ing the routing operations fault tolerantly). Physical er-
rors occurring with probability εcan simply be replaced
by logical errors occurring with probability εL, and one
obtains the corresponding bound
1−FL≤4εLTLlog N, (45)
where FLis the query fidelity of the logical QRAM cir-
cuit, and TLis the circuit depth. Thus, when imple-
mented fault-tolerantly, the logical bucket-brigade cir-
cuits possess an intrinsic resilience to logical errors, in
that the logical infidelity scales only polylogarithmically
with the the size of the memory (This scaling assumes
TL=O(log N); see further discussion at the end of this
section).
To provide further exposition, we give a concrete
example of an error-corrected quantum router. Con-
sider a quantum error correcting-code, with logical code-
words |0Liand |1Lisatisfying the Knill-Laflamme con-
ditions [39,52],
P K†
iKjP=hij P, (46)
where Pis the projector onto the code space, the {Ki}
are the set of correctable errors, and his a Hermitian
15
matrix. A logical two-level quantum router then consti-
tutes a single logical qubit (similarly, a logical three-level
quantum router can be constructed from a pair of log-
ical qubits, for example). Crucially, the logical routers
comprising the QRAM can be corrected without reveal-
ing any information about which memory elements are
being accessed. This is because the conditions (46) guar-
antee that errors can be corrected without revealing any
information about the encoded state. Even when the
logical router is in a superposition of different states, or
entangled with other routers, syndrome measurements
do not reveal information about the router state. Note
that the conditions (46) also guarantee that information
is not leaked to the environment; the states |0Liand |1Li
necessarily have equal probability of suffering errors.
Because of the favorable logical error scaling Eq. (45),
error-corrected implementations of the bucket-brigade
scheme can offer improved fidelity or reduced overhead
relative to other implementations. For instance, if the
same error-correcting code is used in fault-tolerant im-
plementations of the bucket-brigade and fanout QRAMs,
the logical infidelity of bucket brigade QRAM will be
lower than the logical infidelity of the fanout QRAM by
a factor of ∼1/N in general. Alternatively, if a given
application requires that QRAM have a logical infidelity
below some threshold, the error-correction overhead re-
quired to realize such high-fidelity queries can be sig-
nificantly smaller for the bucket-brigade scheme relative
to the fanout scheme. Indeed, even if the reduction in
error-correction overhead is fairly small for each router,
the total overhead reduction considering all Nrouters
can be significant. Such reductions could be of signifi-
cant practical benefit.
We conclude this section with an important caveat
concerning fault-tolerant QRAM. The routing opera-
tion [Fig. 1(b)] is non-Clifford, so magic state distilla-
tion [53,54] is required to implement the routing fault-
tolerantly in the usual Clifford+T fault-tolerance model.
In total, O(N) magic states are required to perform a
query. If queries are to be performed in time TL=
O(log N), these magic states must be distilled in par-
allel, so O(N) magic state factories are required. The
additional overhead associated with these factories could
be prohibitive for large N, however, potentially limiting
the extent to which such parallelism can be exploited.
That said, it should be noted that though the routing
operation is non-Clifford, it is also not universal for quan-
tum computing. An important open question concerning
fault-tolerant QRAM is thus whether fault-tolerant im-
plementations of this specific operation can be designed
that are more efficient than generic fault-tolerant opera-
tions. Schemes for pieceable fault-tolerance [55] or noise-
bias preserving gates [56–58] may prove useful in this
regard.
VIII. DISCUSSION
We have shown that the bucket-brigade QRAM archi-
tecture possesses a remarkable resilience to noise. Even
when all O(N) components comprising the QRAM are
subject to arbitrary error channels, the query infidelity
scales only polylogarithmically with the memory size. As
a result, the bucket-brigade architecture can be used to
perform high-fidelity queries of large memories without
the need for quantum error correction, provided physi-
cal error rates are low. Importantly, we prove that this
noise resilience holds for arbitrary error channels, demon-
strating that a noise-resilient QRAM can be implemented
with realistically noisy devices.
In the near-term, this noise resilience could facili-
tate experimental demonstrations and benchmarking of
numerous quantum algorithms. We are presently in
the Noisy, Intermediate-Scale Quantum (NISQ) era [59],
when making more qubits is easier than making bet-
ter qubits. The same is likely to be true even in the
era of early fault-tolerance. In these eras, the bucket-
brigade architecture—with its larger overhead and noise
resilience—could actually prove to be more practical than
alternatives like QROM (see Section VI) that have a
lower overhead but are less tolerant to noise. The bucket-
brigade architecture thus more readily enables small-
scale, near-term implementations of algorithms, and im-
portant practical insights are likely to be gained from
such demonstrations.
In the long-term, this noise resilience may prove useful
in facilitating speedups for certain quantum algorithms,
but it is important that the required resources be care-
fully assessed before a speedup via QRAM is claimed.
Consider an oracle-based algorithm that requires nqubits
(not including ancillary qubits needed to implement the
oracle). As we show in Table II, such algorithms can be
conveniently classified according to how the size of the
classical memory being queried, N, and the total num-
ber of queries, Q, scale with n. Assuming poly(n) query
times are required, the memory size Ndictates whether
QRAM (as opposed to QROM or a hybrid architecture)
is required to implement the oracle. The number of
queries Qdictates whether error correction is necessarily
required [17]. The noise resilience of the bucket-brigade
has the biggest potential impact in case of N= exp(n)
and Q= poly(n). In this case, QRAM is required, and
the noise-resilience of the bucket-brigade architecture, to-
gether with the comparatively small number of queries,
allows for the possibility that the QRAM could be im-
plemented without error correction. Of course, the noise
resilience can also be advantageous in the other cases,
where hybrid architectures may be employed (Section VI)
or when error correction is used (Section VII).
Finally, it is worth emphasizing that the results in this
paper constitute general statements about the bucket-
brigade architecture, independent of its application to
particular algorithms. In fact, the architecture may prove
useful in applications other than facilitating algorithmic
16
N Q Applicable architectures QEC required? Paradigmatic example
exp(n) exp(n) QRAM Yes Searching an unstructured database [24]
exp(n) poly(n) QRAM Maybe not Solving linear systems of equations [29]
(sparse, well-conditioned systems)
poly(n) poly(n) QRAM, QROM, Hybrid Maybe not Simulating local Hamiltonians [60]
TABLE II. Algorithm categorization. Algorithms are sorted based on how the size of the classical memory, N, and the number
of queries, Q, scale with the number of qubits, n. When N= exp(n), QRAM is the only suitable architecture, assuming
poly(n) query times are required. When Q= poly(n) quantum error correction may not be required, depending on the physical
error rates. For the examples in the last two rows, Qalso depends on the particular algorithm used and the desired precision;
we assume these are chosen such that Q= poly(n). We omit the case of N= poly(n) and Q= exp(n), for which the query
complexity is exponential in the problem size.
speedups. For example, Ref. [28] employs the bucket-
brigade architecture in a quantum cryptographic proto-
col. The architecture may similarly prove useful for quan-
tum communication or metrology. Exploring applica-
tions of the bucket-brigade architecture—and the utility
of its noise resilience—in these other contexts represents
an interesting direction for future research. In particular,
applications involving quantum queries of quantum data
remain largely unexplored.
IX. ACKNOWLEDGEMENTS
We thank Shruti Puri and Xiaodi Wu helpful discus-
sions. We acknowledge the Yale Center for Research
Computing for use of its high-performance computing
clusters. CTH acknowledges support from the NSF
Graduate Research Fellowship Program (DGE1752134).
We acknowledge support from the ARO (W911NF-18-
1-0020, W911NF-18-1-0212), ARO MURI (W911NF-
16-1-0349), AFOSR MURI (FA9550-19-1-0399), DOE
(DE-SC0019406), NSF (EFMA-1640959, OMA-1936118,
EEC-1941583), NTT Research, and the Packard Foun-
dation (2013-39273).
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18
Appendix A: Bucket-brigade QRAM circuit
Fig. 10 shows a circuit diagram for the bucket-brigade
QRAM in the case of an N= 8 cell memory. In contrast
to the T=O(log2N) depth circuits described implic-
itly in Refs. [14,15,17], the circuit depth here is only
T=O(log N). The quadratic speedup is due to addi-
tional parallelization of the routing operations that we
now describe.
In Refs. [14,15,17], address qubits are routed into the
tree one at a time; the (`+ 1)-th address qubit is only
injected into the tree once the `-th address qubit has
taken its position at level `of the tree. If each routing
operation takes one time step, then one waits `time steps
between the injection of the `-th and (`+ 1)-th address
qubits. The total circuit depth is obtained by summing
the number of time steps that it takes for each address
to reach the corresponding level,
T∼
log N−1
X
`=0
`=O(log2N).(A1)
However, it is not necessary to wait for an address qubit
to reach its destination before subsequent address qubits
are sent into the tree, and this realization enables the
circuit depth to be reduced to O(log N). Notice that the
routing operations for routers located at even levels of the
tree act on mutually disjoint qubits and hence mutually
commute (the same is true for the odd levels). Thus,
all routing operations at either even or odd levels can be
performed in parallel. In practice, then, once an address
qubit has reached level `= 2, the next address qubit
can be sent into the tree at level `= 0, and the two can
be routed in parallel. This way, the wait time between
the injection of subsequent address qubits into the tree is
constant (cf. the O(`) wait time above). Exploiting this
additional parallelism, the total circuit depth is reduced
to T=O(log N).
The circuit diagram in Fig. 10 illustrates how such
T=O(log N) bucket-brigade QRAM circuits are struc-
tured. The circuit is a sequence of Tconstant-depth
circuits Ut. During each block Ut, a subset of the possi-
ble routing operations is performed (orange boxes in the
figure), with routing operations at even levels performed
before routing operations at odd levels. Importantly, be-
cause the operations at even levels can be performed in
parallel (sim. for odd levels), each orange box constitutes
only two layers of parallel gates. In principle, new ad-
dress qubit can then be injected into the tree at the
beginning of each orange box, with routing performed
in parallel whenever multiple address qubits are being
routed through the tree. The case of N= 8 shown in the
figure is too small to demonstrate this parallelism, but to
see how the parallelism would manifest at larger memory
sizes, notice that it would be possible to inject another
qubit into the tree during U5and route this qubit (at
level `= 0) in parallel with one at level `= 2.
Appendix B: Copying data to the bus
In this section, we explicitly describe how classical data
can be copied into the state of the bus. Slightly differ-
ent procedures are required depending on whether the
QRAM is implemented with two-level or three-level sys-
tems, and whether the QRAM is initialized in a known
state or in some arbitrary state (see Section V).
We begin with the case where the QRAM is imple-
mented with two-level routers, as described in Section V.
Each router’s incident and output modes are also taken
to be physical two-level systems. All routers and their re-
spective modes are initialized to |0i. For reasons that will
become apparent shortly, we suppose that the bus qubit
is initialized to |+i ≡ (|0i+|1i)/√2 prior to the query.
During the query, this bus qubit is routed down the tree,
to an output mode of some router at the bottom level.
At this point, classical data is encoded into the state of
the bus qubit by applying classically controlled Zgates,
as illustrated in Fig. 11(a). If the memory element being
queried is 1, a Zgate is applied, and the state of the bus
is flipped from |+ito |−i ≡ (|0i−|1i)/√2. If the memory
element queried is 0, no Zgate is applied, and the bus
remains in |+i. In this way, the classical bit is encoded
in the |±i basis of the bus qubit. Note, however, that
because the location of the bus is not known, classically
controlled Zgates must be applied to the output modes
of all routers at the bottom level of the tree.
This data copying operation has a crucial property,
which we call no extra copying: in the absence of errors,
the copying operation acts trivially on all modes that do
not contain the bus qubit. In the above case, all modes
that do not contain the bus are in |0i, so they are un-
affected by the Zgates, hence why we use the |±i basis
for the bus [34]. The no extra copying property is crucial
because it guarantees that the final state of the tree is the
same across all good (error-free) branches, as required by
the arguments in the main text. Were this property not
to hold, the final state of the tree would depend on which
element was queried, so the bus would remain entangled
with the routers after the query, even in the absence of
errors.
Now let us consider the case where the QRAM is im-
plemented with three-level routers, as described in Sec-
tions II and III. Each router’s incident and output modes
are taken to be physical three-level systems, whose basis
states we also label as |0i,|1i, and |Wi. The address
and bus qubits are encoded within the |0,1isubspace of
such three-level systems. Prior to the query, all routers,
as well as their incident and output modes, are initialized
to |Wi, and the bus is initialized to |0i. During the query,
the bus is routed to an output mode of some router at
the bottom level of the tree. Data is copied into the bus
by applying classically controlled ˜
Xgates to the output
modes [Fig. 11(b)], where
˜
X=|1ih0|+|0ih1|+|Wi hW|.(B1)
If the memory element being queried is 1, the ˜
Xgate is
19
Address
Bus
Input
Routers
=
Routing
circuit
...
...
...
...
FIG. 10. Bucket-brigade QRAM circuit for N= 8. The bus and address register are indicated by rails at the top of the
diagram, and the routers are indicated by the rails below. The “input” rail is an extra ancilla, included only to simplify the
circuit diagram. For each router shown on the left, there are three rails: one for the router’s internal state, and two for the
router’s two output modes. All rails represent qubits (qutrits) when the variant of the bucket-brigade architecture with two-
level (three-level) routers is used; the circuit is the same in either case. To simplify the circuit we use a shorthand notation for
the routing operation (top right). Each orange box contains routing operations for a subset of routers in the tree, with routing
operations for the even levels first (white background), followed by the odd levels (gray background). Though only a subset of
the possible routing operations are actually applied at each time step, in principle all routing operations at even (odd) levels
can be applied in parallel. The first part of the circuit, U3U2U1, routes the addresses into the tree, as in Fig. 1(d). The next
part, U5U4, routes the bus to the appropriate memory cell. The path of the bus is highlighted in blue for the case where the
three address qubits are initialized to |010i. The last layer of gates copy data into the state of the bus (see Appendix B). To
route the addresses and bus out of the tree and complete the query, the inverse operation, (U5U4U3U2U1)†, must subsequently
be applied (not shown).
applied, and the state of the bus is flipped from |0ito |1i.
If the memory element queried is 0, no ˜
Xgate is applied,
and the bus remains in |0i. In this way, the classical bit
is encoded in the |0,1ibasis of the bus qubit (one could
also choose to encode the information in the |±i basis
by constructing an analogous ˜
Zgate). Here again, the
classically controlled gates must be applied to the output
modes of all routers at the bottom of the tree. This
operation satisfies the no extra copying property because,
in the absence of errors, all modes not containing the bus
are in |Wi, on which ˜
Xacts trivially.
In order to enforce the no extra copying property, both
of the above data copying operations rely on the fact that
the routers, as well as their input and output modes, are
initialized to some known state. When the QRAM is ini-
tialized in an arbitrary state (see Section V), however,
additional care must be taken to ensure this property
still holds. The challenge is that the mode that actually
contains the bus must somehow be distinguished from all
the other modes, which may have been initialized in the
same state as the bus. This problem is solved by the cir-
cuit in Fig. 11(c). The QRAM is queried twice, and the
no extra copying property is guaranteed by the fact that
the entire QRAM unitary operation is idempotent. In
particular, even if the process of copying data during the
first query acts non-trivially on modes not containing the
20
Output
Data
Output
Data
(a) (b)
QRAM QRAM
Add.
Bus
(c)
FIG. 11. Circuits for copying classical data. (a) Two-level
circuit. The bus qubit is encoded within a physical two-level
system and initialized in |+i. A Zgate flips the bus to |−i
conditioned on the classical data. (b) Three-level circuit. The
bus qubit is encoded within a two-level subspace of a physical
three-level system and initialized in |0i. The ˜
Xgate (see
text) flips the bus to |1iconditioned on the classical data. (c)
Query circuit for QRAM initialized in an arbitrary state. The
circuits assumes three-level routers, so the bus is initialized in
|0iand circuit (b) is employed within each QRAM block to
copy data to the bus. An analogous circuit can be constructed
for two-level routers. The ancillary qubits comprising the
QRAM’s routers (not shown) can be initialized in an arbitrary
state.
bus, these modes are always reset to their initial states
by the second query. In fact, even the bus is reset to its
initial state by the second query. Thus, the information
stored in the bus is copied to an ancillary qubit in be-
tween the two queries, then swapped back into the bus
after the second query. We emphasize that the query fi-
delity of this circuit scales favorably, which can be shown
by simply replacing T→2Tin the scaling argument
from Section Vto account for the fact that the QRAM
is called twice.
As an aside, let us distinguish between our observation
that QRAM is resilient to noise even when initialized in
an arbitrary state (Section V), and the observation of
Refs. [32,38] that the ancillary qubits used to perform
a query can be “dirty.” The latter states that circuits
can be designed such that, in the absence of errors, any
ancillary qubits used during the query are returned to
their initial state after the query, regardless of what the
initial state was (note the circuit in Fig. 11(c) has this
property). In contrast, our observation concerns what
happens when errors occur during the query: the query
infidelity of the circuit Fig. 11(c) scales favorably even
when the QRAM is initialized in an arbitrary state.
Appendix C: Error channel Kraus decompositions
In this Appendix, we give the Kraus decompositions
for the channels used in our simulations. We specify a
generic channel Eas via a list of its Kraus operators as
E={K0, K1, K2, . . .}.(C1)
1. Qubit error channels
Let X, Y, Z denote the Pauli matrices. The decompo-
sitions of the qubit error channels are
Depolarizing = √1−εI , rε
3X, rε
3Y, rε
3Z(C2)
Bit-flip = √1−εI, √εX(C3)
Dephasing = √1−εI, √εZ(C4)
Damping = |0ih0|+√1−ε|1ih1|,√ε|0i h1|(C5)
Heating = |1ih1|+√1−ε|0ih0|,√ε|1i h0|(C6)
2. Qutrit error channels
We follow the definitions for qutrit depolarizing, bit-
flip, and dephasing channels given in Refs. [61], [17], and
[62], respectively. Define the operators
A1=
010
001
100
, A2=
1 0 0
0ω0
0 0 ω2
,(C7)
where the matrices are written in the {|Wi,|0i,|1i} ba-
sis, and ω=ei2π/3. The decompositions of the qutrit
error channels are
21
Depolarizing = √1−εI , rε
8A1,rε
8A2,rε
8A2
1,rε
8A2
2,rε
8A1A2,rε
8A2
1A2,rε
8A1A2
2,rε
8A2
1A2
2(C8)
Bit-flip = √1−εI, √ε(|0ih1|+|1ih0|)(C9)
Dephasing = √1−εI, rε
2A2,rε
2A2
2(C10)
Damping = |WihW|+√1−ε(|0ih0|+|1i h1|),√ε|Wi h0|,√ε|Wih1|(C11)
Heating = |0ih0|+|1ih1|+√1−ε|Wi hW|,rε
2|0ihW|,rε
2|1ihW|.(C12)
Appendix D: Proof of noise resilience for arbitrary
error channels
In this Appendix, we prove that, for arbitrary error
channels, the QRAM query infidelity satisfies the bound
1−F≤AεT log N, (D1)
where Ais a constant of order 1 (defined below). We
begin by defining the error model and introducing some
convenient notation.
1. Error model
We suppose that at each time step, every router in the
QRAM is subject to an error channel Eof the form
ρ→ E(ρ) = X
m
KmρK†
m.(D2)
One could also consider situations where different routers
are subject to different error channels; the proof straight-
forwardly extends to such situations. For the moment, we
make two additional assumptions that simplify the proof.
First, we restrict our attention channels with Kraus rank
two, i.e. channels that can be expressed with only two
non-zero Kraus operators, K0and K1. Second, we as-
sume that each router is subjected to the error channel
Eonly once, at the time step t∗after all addresses have
been routed into place and immediately before the bus
enters the tree (this time step is the one illustrated in
Figs. 1and 2). We relax both of these assumptions later
on.
Let us define the error rate, ε. For a generic state |ψi,
we may write
K0|ψi=aψ|ψi+bψ|ψ⊥i(D3)
where hψ|ψ⊥i= 0, and aψ,bψare complex numbers. We
define εas the smallest positive real number such that,
for any |ψi, we have
|bψ| ≤ √ε, (D4)
and for any collection of arbitrary states |ψii, we also
have
<"m
Y
i=1
aψi#≥(1 −ε)m/2,for any m≤log N. (D5)
This definition is unconventional, so let us emphasize
that εcan be understood as quantifying the distance be-
tween Eand the identity channel. Specifically, for any
given ε0∈[0,1], there always exists some δ∈[0,1] such
that, whenever |E − I|< δ according to some distance
metric, then ε<ε0.
We adopt this definition of εbecause it turns out to
be very convenient for the proof. For example, it follows
that
hψ|K†
0K0|ψi ≥ 1−ε(D6)
hψ|K†
1K1|ψi ≤ ε. (D7)
and, for a generic product state, |ξmi=Nm
i=1 |ψii,
K⊗m
0|ξmi=aξm|ξmi+bξm|ξ⊥
mi,(D8)
where it follows from Eqs. (D4) and (D5) that
<(aξm)≥(1 −ε)m/2(D9)
|bξm| ≤ εm/2(D10)
for m≤log N.
2. Notation
We now define some convenient notation. As in the
main text, we use the shorthand
Kc≡
N−1
O
r=1
Kc(r)(D11)
to denote the composite Kraus operator acting on all
routers in the tree. Here, Kc(r)∈ {K0, K1}denotes the
Kraus operator applied to router rat time t∗as specified
22
by the error configuration c. For the i-th branch of the
tree, we also define the operator Kc6∈ias that obtained
by taking Kcand replacing Kc(r)→Ifor any router r
in branch i:
Kc6∈i≡
N−1
O
r=1 (I, r ∈i,
Kc(r),otherwise. (D12)
Similarly, for a pair of branches, iand j, we analogously
define
Kc6∈i,j ≡
N−1
O
r=1 (I, r ∈i∪j,
Kc(r),otherwise. (D13)
where r∈i∪jdenotes the set of routers in either branch
ior j.
Additionally, we define |Riito be the ideal state of the
routers at time t∗assuming the i-th memory element is
queried. Specifically, |Riiis a computational basis state
for which all routers r6∈ iare in the state |Wi, and
routers r∈iare in either |0ior |1iand carve out a
path to the memory element i. As examples, |R101iis
illustrated in Fig. 1(d), and the superposition
|R000i+|R010 i+|R011i+|R101 i+|R110 i
is illustrated in Fig. 2.
Finally, throughout the proof it will be convenient to
work with unnormalized quantum states. We distinguish
between normalized states |ψiand unnormalized states
|ψiwith an overbar.
3. Proof
Our proof of QRAM’s noise resilience for generic error channels follows the same outline as the proof for mixed-
unitary error channels given in the main text. We again begin by defining the final state of the system Ω as an
incoherent mixture over final states for different error configurations c,
Ω = X
c
Ω(c) (D14)
in analogy to Eq. (11). Here, the final system state given error configuration cis Ω(c) = |Ω(c)ihΩ(c)|, where |Ω(c)i
is the unnormalized state
|Ω(c)i=V"|0iA|0iBKc X
i
αi|RiiR!#,(D15)
where the superscripts A, B, R denote the addresses, bus, and routers, respectively. In accordance with the error model
described in Appendix D 1, the quantity in square brackets is the ideal state of the system at time t∗with errors
Kcsubsequently applied to the routers. The unitary Vcomprises all operations performed after time t∗. Namely,
Vroutes the bus to memory, copies data into the bus, then routes the bus and all address qubits out of the tree.
Note that Kcis not unitary, and the states |Ω(c)iare not normalized. The probability p(c) of error configuration c
occurring is
p(c) = Tr[Ω(c)].(D16)
The query fidelity is given by
F=X
c
F(c) (D17)
where
F(c) = hψout|TrRΩ(c)|ψouti(D18)
in analogy to Eqs. (12) and (13). As in the main text, we proceed by placing a lower bound on F(c). To do so, we
write
|Ω(c)i=|good(c)i+|bad(c)i,(D19)
in analogy to Eq. (16), and where the definitions of |good(c)iand |bad(c)iwill be given shortly.
Let us recall the definition of good and bad branches given in the main text. There, a branch iwas defined to be
good if and only if i∩c=∅, where iis the set of routers in the i-th branch of the tree, and cis the set of routers
23
which have Km>0applied to them according to error configuration c. We retain this definition here. Now, in main
text we considered the case of mixed-unitary error channels, for which K0∝I, and for these channels we have that
Kc|Rii=Kc6∈i|Rii,for K0∝I(D20)
for all i∈g(c), where g(c) denotes the set of good branches. In words, Eq. (D20) says that effect of the of no-error
operators on the active routers is trivial. However, in the present case of general channels, for which K06=Iin
general, the no-error backaction associated with K0can alter the states of active routers. In particular,
Kc|Rii=Kc6∈iaRi|Rii+bRi|R⊥
ii,for general K0(D21)
for all i∈g(c), and where |R⊥
iidenotes an orthogonal state, hRi|R⊥
ii= 0. It follows from Eqs. (D8) to (D10) that
the coefficients aRiand bRisatisfy
<(aRi)≥(1 −ε)log N/2(D22)
|bRi| ≤ εlog N/2.(D23)
In words, Eq. (D21) says that effect of the of no-error operators on the active routers is nontrivial and places the active
routers in a superposition of the ideal state and some orthogonal state. Eqs. (D22) and (D23) bound the coefficients
in this superposition; in the relevant regime of εlog N1, this nontrivial, no-error backaction is small, and the state
Kc|Riiis close to Kc6∈i|Rii.
Now, let us define |good(c)iand |bad(c)iin Eq. (D19). Given Eq. (D21), it will be convenient to separate the ideal
and non-ideal components of Kc|Rii, retaining only the ideal components in |good(c)i. We thus define
|good(c)i ≡ V
|0iA|0iBX
i∈g(c)
αiaRiKc6∈i|RiiR
(D24)
in analogy to Eq. (17), and
|bad(c)i≡|Ω(c)i−|good(c)i=V
|0iA|0iB
X
i∈g(c)
αibRiKc6∈i|R⊥
iiR+X
j6∈g(c)
αjKc|RiiR
.(D25)
Note that |bad(c)inot only contains a contribution from the bad branches, j6∈ g(c), but also from the no-error
backaction in the good branches, i∈g(c).
We now seek to prove analogous statements to Eqs. (20) and (21) (given by Lemmas 2and 3below). To do so, we
first show that the overlap of |good(c)iand the ideal state is large in the following sense.
Lemma 1. The overlap between |good(c)iand the ideal final state, |ψout, f (c)i, satisfies the bound
<hψout, f (c)|good(c)i≥pq(c) Λ(c)1−ε
1−εW
3
2log N
(D26)
where Λ(c) = Pi∈g(c)|αi|2is the weighted fraction of good branches, |f(c)iis some fixed final state of the routers
(defined below), and
q(c)≡(1 −εW)(N−1)−|c|ε|c|
W,(D27)
with εW≡1− hW|<