Article

A DSP Architecture for Distortion-Free Evoked Compound Action Potential Recovery in Neural Response Telemetry System

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Abstract

Abstract: This paper presents a digital signal processing (DSP) architecture for real-time and distortion-free recovery of electrically-evoked compound action potentials (ECAPs) from stimulus artifacts and periodic noises in bidirectional neural response telemetry (NRT) system. In this DSP architecture, a low computation-cost bidirectional-filtered coherent averaging (BFCA) method is proposed for programmable linear-phase filtering of ECAPs, which can be easily combined with the alternating-polarity (AP) stimulation method to reject stimulus artifacts overlapped with ECAP responses. Design techniques including the configurable folded infinite-impulse-response (IIR) filter and division-free averaging are also presented for efficient hardware implementation. Implemented in 180-nm CMOS process, the proposed DSP architecture consumes 10.03-mm2 area and 2.35-mW post-layout simulated power. The efficacy of the DSP architecture in recovering ECAPs from recorded neural data contaminated by overlapped stimulus artifacts and periodic noises is validated in in-vivo electrical nerve stimulations. Experiment results show that compared with the previous coherent averaging technique, the proposed DSP architecture improves the signal-to- noise ratio (SNR) of ECAP responses by 11 dB and achieves an 3.1% waveform distortion that is 17.1× lower.

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We describe an algorithm for suppression of stimulation artifacts in extracellular micro-electrode array (MEA) recordings. A model of the artifact based on locally fitted cubic polynomials is subtracted from the recording, yielding a flat baseline amenable to spike detection by voltage thresholding. The algorithm, SALPA, reduces the period after stimulation during which action potentials cannot be detected by an order of magnitude, to less than 2 ms. Our implementation is fast enough to process 60-channel data sampled at 25 kHz in real-time on an inexpensive desktop PC. It performs well on a wide range of artifact shapes without re-tuning any parameters, because it accounts for amplifier saturation explicitly and uses a statistic to verify successful artifact suppression immediately after the amplifiers become operational. We demonstrate the algorithm's effectiveness on recordings from dense monolayer cultures of cortical neurons obtained from rat embryos. SALPA opens up a previously inaccessible window for studying transient neural oscillations and precisely timed dynamics in short-latency responses to electric stimulation.
Article
Electrical stimulus artifact corrupting electrophysiological recordings often makes the subsequent analysis of the underlying neural response difficult. This is particularly evident when investigating short-latency neural activity in response to high-rate electrical stimulation. We developed and evaluated an off-line technique for the removal of stimulus artifact from electrophysiological recordings. Pulsatile electrical stimulation was presented at rates of up to 5000 pulses/s during extracellular recordings of guinea pig auditory nerve fibers. Stimulus artifact was removed by replacing the sample points at each stimulus artifact event with values interpolated along a straight line, computed from neighbouring sample points. This technique required only that artifact events be identifiable and that the artifact duration remained less than both the inter-stimulus interval and the time course of the action potential. We have demonstrated that this computationally efficient sample-and-interpolate technique removes the stimulus artifact with minimal distortion of the action potential waveform. We suggest that this technique may have potential applications in a range of electrophysiological recording systems.
Conference Paper
The FFT processor is one of the key components in the implementation of wideband OFDM systems. Architectures with a structured pipeline have been used to meet the fast, real-time processing demand and low-power consumption requirement in a mobile environment. Architectures based on new forms of FFT, the radix-2i algorithm derived by cascade decomposition, is proposed. By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized. Progressive wordlength adjustment has been introduced to optimize the total memory size with a given signal-to-quantization-noise-ratio (SQNR) requirement in fixed-point processing. A new complex multiplier based on distributed arithmetic further enhanced the area/power efficiency of the design. A single-chip processor for 1 K complex point FFT transform is used to demonstrate the design issues under consideration
Article
This paper presents a general-purpose computer program which is capable of designing a large Class of optimum (in the minimax sense) FIR linear phase digital filters. The program has options for designing such standard filters as low-pass, high-pass, bandpass, and bandstop filters, as well as multipassband-stopband filters, differentiators, and Hilbert transformers. The program can also be used to design filters which approximate arbitrary frequency specifications which are provided by the user. The program is written in Fortran, and is carefully documented both by comments and by detailed flowcharts. The filter design algorithm is shown to be exceedingly efficient, e.g., it is capable of designing a filter with a 100-point impulse response in about 20 s.
Article
A method for designing finite-duration impulse-response (FIR) linear-phase digital filters is presented in which the four possible cases for such filters are treated in a unified approach. It is shown how to reduce each case to the proper form so that the Remez exchange algorithm can be used to compute the best approximation to the desired frequency response. The result is that a very flexible and fast technique is available for FIR linear-phase filter design.
Article
A new modified circuit for implementing high performance IIR filters based on a pipelined multiply-accumulate (MAC) processor is proposed. Clever deployment of latches in the circuit allows the results to be generated once every cycle thereby providing increased performance with reduced size and power consumption over previously designed circuits
Article
A novel approach to designing approximately linear phase infinite-impulse-response (IIR) digital filters in the passband region is introduced. The proposed approach yields digital IIR filters whose numerators represent linear phase finite-impulse-response (FIR) filters. As an example, low-pass IIR differentiators are introduced. The range and high-frequency suppression of the proposed low-pass differentiators are comparable to those obtained by higher order FIR low-pass differentiators. In addition, the differentiators exhibit almost linear phases in the passband regions
Article
A real-time IIR filter structure is presented that possesses exact phase linearity with 10~1000 times fewer general multiplies than conventional FIR filters of similar performance and better magnitude characteristics than equiripple or maximally flat group delay IIR filters. This structure is based on a technique using local time reversal and single pass sectioned convolution methods to realized a real-time recursive implementation of the noncausal transfer function H ( z -1). The time reversed section technique used to realize exactly linear phase IIR filters is described. The effects of finite section length on the sectional convolution are analyzed. A simulation methodology is developed to address the special requirements of simulating a time reversed section filter. A design example is presented, with computer simulation to illustrate performance, in terms of overall magnitude response and phase linearity, as a function of finite section length. Nine example filter specifications are used to compare the performance and complexity of the time reversed section technique to those of a direct FIR implementation
Article
This paper presents a new method for designing digital linear phase, finite impulse response filters with loose frequency response characteristics, but with good time resolution as is required in biological signal conditioning. The design is very simple and has been used with success in the microcomputer implementation of filters for the automated processing of electroencephalographic (EEG) data. Examples and a discussion of possible filter implementations are included. Copyright © 1986 by The Institute of Electrical and Electronics Engineers, Inc.
Article
The electrical stimulus pulse and the surface electrodes commonly used to study compound action potentials of peripheral nerves give rise to an artifact consisting of an initial spike and a longer lasting tail which often interferes with the recorded signal. The artifact has four sources: 1) the voltage gradient between the recording electordes caused by stimulus current flowing through the limb, 2) the common-mode voltage of the limb caused by current escaping through the ground electrode, 3) the capacitive coupling between the stimulating and recording leads, and 4) the high-pass filtering characteristics of the recording amplifier. This paper models these sources and presents several methodological rules for minimizing their effects. Also presented are three computer-based methods for subtracting the residual artifact from contaminated records using estimates of the artifact obtained from: 1) subthreshold stimulation, 2) a second recording site remote from the nerve, or 3) stimulation during the refractory period of the nerve.
Discrete Wavelet Transformations: An Elementary Approach With Applications