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Dissertations and Theses Dissertations and Theses
6-17-2020
Design of a 7-MHz Portable Direct Conversion Design of a 7-MHz Portable Direct Conversion
Transceiver with Digitally Controlled Keying Transceiver with Digitally Controlled Keying
Abram Morphew
Portland State University
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Morphew, Abram, "Design of a 7-MHz Portable Direct Conversion Transceiver with Digitally Controlled
Keying" (2020).
Dissertations and Theses.
Paper 5548.
https://doi.org/10.15760/etd.7422
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Design of a 7-MHz Portable Direct Conversion Transceiver with Digitally
Controlled Keying
by
Abram Morphew
A thesis submitted in partial fulfillment of the
requirements for the degree of
Master of Science
in
Electrical and Computer Engineering
Thesis Committee:
Robert Bass, Chair
Branimir Pejcinovic
Erik Sanchez
Portland State University
2020
Portland State University
Abstract
Department of Electrical and Computer Engineering
Maseeh College of Engineering and Computer Science
Master of Science
by Abram Morphew
This thesis outlines the design of a portable direct conversion transceiver system for
the 7-MHz (or 40m) band. This band is popular due to its propagation characteris-
tics, which allow for world-wide communication with very low power. The transceiver
utilizes a crystal-stabilized local oscillator optimized for frequency agility, low power
consumption, and an optimal drive level of +7 dBm. A low power 8-bit microcontroller
acts as an interface for either a straight key providing manual Morse code operation or
digital logic control from a personal computer. It also acts as a sidetone oscillator pro-
viding audio feedback to the operator during keying and reducing circuit complexity.
Switching field-effect transistors (FETs) were used to change from transmit to receive
with a switching speed of less than 300 microseconds and allowing for full break-in
functionality. For the transmitter portion of the design, a dual-stage power amplifier
was developed capable of power output levels greater than 30 dBm. Transmission tests
were received at several locations ranging from Calgary, Canada to Tucson, Arizona
having a maximum propagation distance of 1103.5 miles from the transmitter source.
i
For Bethany, Gracie, and Isabella. . .
ii
Acknowledgments
I’d certainly like to acknowledge the contribution by my thesis advisor, Dr. Richard
Campbell, for continually fueling my already existing interest in RF applications. Much
appreciation also goes to the thesis committee members, Dr. Robert Bass, Dr. Erik
Sanchez, and Dr. Branimir Pejcinovic for their feedback and contribution to my work.
I’d also like to thank the countless amateur operators who have provided access to
their software-defined radios over the internet and the development team of the Reverse
Beacon Network. Using their tools has allowed for over-the-air testing in a way that
wouldn’t have been possible otherwise.
Lastly, I’d like to thank my partner, Bethany, for her constant and continued support
in all aspects of life. Without her, this work would never have been possible.
iii
Table of Contents
Abstract i
Acknowledgments iii
List of Figures vi
List of Tables viii
Abbreviations ix
1 Introduction 1
1.1 Direct Conversion Receiver . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation .................................. 4
1.3 ResearchObjectives ............................. 5
1.4 Organization ................................. 6
2 Direct Conversion Receiver 7
2.1 Receiver Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 DiodeRingMixer............................... 8
2.3 LocalOscillator................................ 9
2.4 Low-PassFilter(LPF)............................ 16
2.5 Low-Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 AudioAmplifier................................ 21
3 Transmitter and Switching Circuitry 24
3.1 Transmitter Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 DriverStage.................................. 25
3.3 FinalStage .................................. 28
3.4 Digital Transmit/Receive Switching . . . . . . . . . . . . . . . . . . . . 31
4 Receiver Module Characterization 34
4.1 LocalOscillator................................ 34
4.2 Low-Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3 AudioAmplifier................................ 41
5 Transmitter and Switching Module Characterization 45
5.1 Power Amplifier Characterization . . . . . . . . . . . . . . . . . . . . . . 45
iv
5.2 RF Switch Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3 DigitalControl ................................ 49
5.4 MCU as a Side-tone Oscillator . . . . . . . . . . . . . . . . . . . . . . . 50
6 Results and Discussion 52
6.1 Schematic and Board Layout . . . . . . . . . . . . . . . . . . . . . . . . 52
6.2 Board-levelTesting.............................. 52
6.3 On-AirTestResults ............................. 55
6.4 FutureWork ................................. 57
6.5 Conclusion .................................. 59
A AVR Controller Program 60
A.1 Keying Control Code for AVR Microcontroller . . . . . . . . . . . . . . 60
B Bill of Materials 66
B.1 List of Materials Used in the Final Transceiver . . . . . . . . . . . . . . 66
Bibliography 68
v
List of Figures
1.1 Block Diagram of a Direct Conversion Receiver . . . . . . . . . . . . . . 2
1.2 Frequency Offset in a Direct Conversion Receiver . . . . . . . . . . . . . 3
1.3 Block Diagram of the Direct Conversion Transceiver Design . . . . . . . 5
2.1 Receiver Section of the Direct Conversion Transceiver Block Diagram . 7
2.2 Commutation in a Diode Ring Mixer at the LO Frequency . . . . . . . . 8
2.3 Circuit Model of an Ideal Crystal Resonator . . . . . . . . . . . . . . . . 10
2.4 Basic Colpitts-Clapp Oscillator . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Basic Colpitts-Clapp Oscillator with Crystal Resonator . . . . . . . . . 13
2.6 Voltage-Controlled Colpitts-Clapp Oscillator with Parallel Resonators . 15
2.7 5th Order Butterworth Low-Pass Filter Designed for 7 MHz . . . . . . . 17
2.8 Simplified Single-Tuned Amplifier Schematic . . . . . . . . . . . . . . . . 18
2.9 RLC Bandpass Filter Circuit . . . . . . . . . . . . . . . . . . . . . . . . 19
2.10 Simplified Dual-Stage Audio Amplifier Schematic . . . . . . . . . . . . . 21
3.1 Transmitter Section of the Direct Conversion Transceiver Block Diagram 25
3.2 Simulated I-V Characteristics for a BS170 MOSFET . . . . . . . . . . . 26
3.3 Simplified Schematic for a Class A Driver Stage . . . . . . . . . . . . . . 28
3.4 Plot of Theoretical Amplifier Efficiency . . . . . . . . . . . . . . . . . . 30
3.5 Simplified Schematic of the IRF510 Final Stage Power Amplifier . . . . 31
3.6 Schematic for RF Switch Using a Common-gate JFET Amplifier . . . . 32
3.7 Pinout for the ATTiny85 8-bit Microcontroller . . . . . . . . . . . . . . 33
4.1 LTSpice Schematic for the Local Oscillator . . . . . . . . . . . . . . . . 35
4.2 Simulated FFT of Local Oscillator Output . . . . . . . . . . . . . . . . . 36
4.3 Build of Local Oscillator Module . . . . . . . . . . . . . . . . . . . . . . 37
4.4 Measured Power Output of Local Oscillator Build . . . . . . . . . . . . 37
4.5 Measured Harmonic Content of Local Oscillator . . . . . . . . . . . . . . 38
4.6 LTSpice Schematic for the Single-tuned Low-noise Amplifier . . . . . . . 39
4.7 Build of Low-noise Amplifier Module . . . . . . . . . . . . . . . . . . . . 40
4.8 Simulated S-parameters for Single-tuned LNA . . . . . . . . . . . . . . . 40
4.9 Measured S-parameters for Single-tuned LNA . . . . . . . . . . . . . . . 41
4.10 LTSpice Schematic for the Receiver Audio Stage . . . . . . . . . . . . . 42
4.11 Audio Output Capture at 1 kHz into a 32Ω Load . . . . . . . . . . . . . 42
4.12 Simulated and Measured Amplifier Frequency Response . . . . . . . . . 43
5.1 LTSpice Schematic of the Power Amplifier Design . . . . . . . . . . . . . 46
5.2 Simulated and Measured Comparison of Power Amplifier Output . . . . 46
5.3 Measured Spectral Content of the Power Amplifier Output . . . . . . . 47
vi
5.4 Measured Switching Time of JFET Transistor Switch . . . . . . . . . . 48
5.5 Schematic of MCU Transceiver Application Circuit . . . . . . . . . . . . 49
6.1 Full Transceiver Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2 Full Transceiver Circuit Board Layout . . . . . . . . . . . . . . . . . . . 54
6.3 Transmitter Signal Received on a Software-Defined Radio . . . . . . . . 55
6.4 Stations Reporting Received Transmissions on the Reverse Beacon Net-
work...................................... 56
6.5 Logarithmic Audio Spectrograph with and without Multi-stage Filtering 57
6.6 Assembled PCB Mounted in the Aluminum Enclosure . . . . . . . . . . 58
6.7 Completed Transceiver and On-air Test Station . . . . . . . . . . . . . . 59
vii
Abbreviations
DC Direct Current
DCR Direct Conversion Receiver
DCT Direct Conversion Transceiver
DDS Direct Digital Synthesizer
HF High Frequency
IC Integrated Circuit
IF Intermediate Frequency
LPF Low Pass Filter
LSB Lower Side Band
LO Local Oscillator
PA Power Amplifier
RF Radio Frequency
RIT RXIncremental Tuning
RX Receive
TX Transmit
USB Upper Side Band
XIT TX Incremental Tuning
ix
Chapter 1
Introduction
1.1 Direct Conversion Receiver
Since the mid-1960s, a common activity amongst amateur radio operators is to home-
brew radio equipment capable of portable use. The desire for small, portable radios
to use while mobile or hiking saw renewed interest in the direct conversion receiver
due to its lack of multiple intermediate frequency (IF) stages and inherent simplic-
ity. Though originally developed in the 1930s, the first recorded application of direct
conversion as a technique is owed to the electronic musical instrument known as the
Theremin [1]. By the time this technique was adopted for the purpose of communica-
tions, the direct conversion receiver was practically abandoned in favor of other design
techniques until around 1961 [2]. The appeal to most amateurs at the time was that a
solid-state receiver could be constructed using a minimum number of parts with basic
construction techniques and be small enough to slip into a pocket or backpack. While
the simplicity of this topology makes it attractive, there are a number of advantages
and disadvantages to direct conversion that have to be overcome during the design
process.
The block diagram shown in Figure 1.1 gives the outline for a direct conversion receiver
(DCR). At the heart of the DCR is a balanced product mixer. The mixer generates
1
Figure 1.1: Block Diagram of a Direct Conversion Receiver
the product of the incoming RF signal with the local oscillator (LO). The product of
two sinusoids can be broken down into the sum and difference of the two signals by
the following trigomometric identity [3].
cos(ω1t)cos(ω2t)=1/2[cos(ω1t+ω2t) + cos(ω1t−ω2t)] (1.1)
From this identity, the output of the product mixer includes both the sum and differ-
ence of the two input frequencies. Using the direct conversion technique, the frequency
of the LO and incoming RF signal beat together to produce an intermediate frequency
(IF) in the audio range. The additional IF signal that is around twice the frequency
of the LO is discarded via a low-pass filter at the input to an audio amplifier. This
process is sometimes referred to as downconversion whereby the frequency of an RF
signal is converted to a lower frequency. Converting the incoming signal directly into
the audio range makes for a highly selective receiver front-end. This is in contrast to
superheterodyning, which converts the received signal to an intermediate frequency for
further processing. Direct conversion is sometimes referred to as zero-IF or homodyne
receiving due to its lack of an IF stage.
2
Figure 1.2: Frequency Offset in a Direct Conversion Receiver
The lack of additional IF stages and image rejection filters can also make direct con-
version systems tricky to use. Figure 1.2 shows the upper and lower side bands (USB
and LSB respectively) surrounding the LO frequency that would be generated from
downconversion process. An incoming RF signal with a frequency offset of 700 Hz
above the LO would produce a 700 Hz tone in the audio range. Changing the fre-
quency of the LO to match that of the incoming signal would produce a 0 Hz tone
or silence. This is known as zero-beating and is often used to match the frequency
of a transmitting signal so that both parties are transmitting on the same frequency.
The problem here is that two stations transmitting on the same frequency can’t hear
each other in the direct conversion system. Therefore, automatic switching between
the transmit and receive frequencies is usually desired in order for both stations to use
the same frequency to exchange information. Additionally, filtering of one of the side
bands is also a common feature of modern commercial receivers in order to prevent
the incoming signal from appearing twice as the LO changes frequency.
3
1.2 Motivation
There are many amateur radio operators that pursue portable operation with home-
built transceivers. A state-of-the-art transceiver loaded with features like the Elecraft
KX3 can be used as a portable transceiver and even comes in a kit form. However,
a base package sold as a kit has a base price of $1149 USD and might be a bit steep
for someone looking to experiment on the high-frequency (HF) bands. Cheaper single
band kits are available for sale from overseas distributors for under $20 USD, but
these kits often have either a lack of features or such poor performance that they
are hardly usable when it comes to contacting other people on the air. The Elecraft
KX1 was a 4-band CW transceiver that was originally sold around $400 USD, which
offered good performance, a sturdy package, and a variety of features making it ideal for
portable use in the field. However, the KX1 was discontinued in 2017 due to component
availability issues, further increasing the price gap in low-power HF transceivers [4].
QRP Labs in the United Kingdom has taken to filling this price gap with their 5-watt
QCX mono-band transceiver for $50 USD on a single printed circuit board without
any form of enclosure [5]. Due to its use of a direct digital synthesizer (DDS) and
other digital components, the QCX pulls more than 120 mA during receive. While
these middle-of-the-road designs are making a lot of progress in the realm of cost,
better power management is desired for long-duration portable use. The primary
motivation behind this research is to develop a single-band transceiver that achieves
power efficiency and the performance similar to analog direct conversion designs of the
past while incorporating cost-effective and commonly available components. This will
advance the state-of-the-art by determining if analog design blocks can be controlled
by a low-cost and power-efficient microcontroller. A block diagram for this type of
design can be seen in Figure 1.3.
4
Figure 1.3: Block Diagram of the Direct Conversion Transceiver Design
Referring to Figure 1.3, the diagram can be divided into an upper and lower section
compromising the receiver (Rx) and transmitter (Tx), respectively. These two sections
must be switched on and off very quickly as the key makes contact with ground. A
microcontroller unit (MCU) uses separate control busses to turn off one section before
enabling the other. A microcontroller with a clock speed of a few megahertz is necessary
in order to make this switching action happen within microseconds. An additional
feature of the Tx control bus is to supply a signal to shift the frequency of the LO
by a few hundred Hertz. This automatic frequency adjust applies the frequency offset
discussed previously and shown in Figure 1.2.
1.3 Research Objectives
While substantial research has been done previously regarding the direct conversion
technique, the overall objective of this paper is to determine if adequate performance
can be obtained by using modern low-cost digital components while also reducing
circuit complexity. Being a design for portable use, this typically implies that the
design should be lightweight and have small footprint. Being limited on size means
5
that circuity complexity should be reduced whenever possible in order to accomodate
space in the transceiver’s enclosure. The overall design criteria for this project are as
follows:
•Design a 7-MHz direct conversion transceiver for portable use with a 12 V battery.
•Transmitter should be capable of power output levels greater than 30 dBm.
•Receiver should be able to detect RF power levels down to -120 dBm.
•Utilize a microcontroller for precision controlled transmit/receive switching.
•Determine if adequate RF performance can be obtained using modern digital
circuitry.
1.4 Organization
This thesis is orgainzed into seven main chapters. The first section (Chapter 1) pro-
vides a brief introduction in to the basic principles and history behind the direct
conversion receiver along with a modular block diagram describing the entire system
design. Chapter 2 outlines the circuit topologies chosen for the receiver section of the
design, while Chapter 3 focuses on the transmitter design. Chapters 4 and 5 outline the
performance acheived from each module in the receiver and transmitter sections. The
results of the whole transeiver system are discussed in Chapter 6, along with additional
work that could be done to improve the system.
6
Chapter 2
Direct Conversion Receiver
2.1 Receiver Functionality
In Figure 2.1, the receiver and transmitter are divided into the upper and lower chains
respectively. Both sections share the functionality of the local oscillator thanks to a
switch controlled by the MCU. When in the Rx state, the path of RF flows into the
system from the antenna, is downconverted to the audio range, and then amplified into
a loudspeaker or low-impedance head phone set. The following sections will detail the
theory and design decisions made for each individual block of the receiver system.
Figure 2.1: Receiver Section of the Direct Conversion Transceiver Block Diagram
7
Figure 2.2: Commutation in a Diode Ring Mixer at the LO Frequency
2.2 Diode Ring Mixer
The real action of the direct conversion receiver (DCR) is the action of the product
mixer downconverting the RF singal into the audio range. This fairly simple trigono-
metric identity is exactly what allows the end user to “receive” a signal, and the
requirements of the product mixer dictate the design requirements for the other mod-
ules in the system. Product mixing is a result of two signals applied to any device with
square law curvature such as a diode or FET [6]. Therefore, mixers tend to come in two
varieties: active and passive. Active mixers can be developed from a single or dual gate
FETs and have some advantanges over passive mixers but can suffer from intermodula-
tion (IM) products if not designed with specific considerations [6]. An active mixer in
this application would draw additional current and would require a higher number of
components if designed from discrete components. Therefore, a Mini-Circuits ADE-1
diode ring mixer was chosen due to its small size and availability.
The ADE-1 is a class-1 doubly-balanced mixer with a +7dBm LO drive level and an
operational frequency range of 0.1 to 500 MHz [7]. A doubly-balanced mixer is ideal as
it provides superior dynamic range and with minimal intermodulation (IM) products
8
[8]. The electrical schematic for the ADE-1 shows (Figure 2.2) the LO acts on the
diodes as switches biasing one pair of diodes and then the other as the polarity of the
LO changes. This switching action is known as commutation, and it permits the RF
signal to pass through one half of the coupling transformer or the other, effectively
multiplying the RF signal by ±1 at the LO frequency [9]. The signal present on the
IF port is then the sum and difference of the signals present on the LO and RF ports.
A wideband termination of 50 Ω at the IF port is useful to ensure that IM products
aren’t reflected back into the mixer [10].
2.3 Local Oscillator
The local oscillator is a crucial element in virtually any radio system. As a result, nu-
merous design techniques have been developed to acheive both frequency stability and
selectivity. When choosing an oscillator circuit for this project, several considerations
were made. The initial concerns were that the LO needed to be frequency agile across
the CW portion of the 7-MHz band, frequency stable within ±5 ppm for narrow-band
tuning, and have a fairly low current draw to extend battery life for portable operation
with a 12 V battery. Additionally, the LO needed to have some voltage control capabil-
ity in order to apply the frequency offset needed between transmit and receive. Given
that the overall design was intended to work within a single band having a tuning
range of only 100 kHz, the decision was made to employ a variable crystal oscillator
(VXO) as the system LO.
Crystal resonators are typically produced from quartz. Quartz has a crystalline atomic
structure that can be deformed when acted on by a force. If that force is removed,
the quartz structure returns to is previous state almost immediately and acts as a
restoring force. When exposed to an electric field, an applied force then acts on the
9
Figure 2.3: Circuit Model of an Ideal Crystal Resonator
electrical charges that are trapped inside the lattice creating a physical distortion in
the material known as the piezoelectric effect. Application of an RF signal can cause
reflections inside the crystal structure that resonate at specific frequencies realtive to
phase shifts created by the crystal’s thickness. The piezoelectric property of quartz
allows it to be resonant at fundamental as well as overtone frequencies, resulting in
little energy loss and a high quality factor (Q). The atomic structure of the crystal also
winds up having a very low frequency drift temperature thanks to very small changes
that occur as the material expands and contracts [11].
In order to design a crystal osciallator, an electrical circuit aproximation of a quartz
crystal is necessary. This idealized model is shown in Figure 2.3. In the model, there
are two main paths. The bottom path contains a series RLC circuit for modeling
the fundamental resonant frequency of the crystal [12]. The fundamental frequency is
usually the frequency labeled on the outer package for ranges of 1 to 30 MHz. The
series resistance (Rs), inductance (Ls), and capacitance (Cs) parameters describe the
motional characteristics related to the mechanical deformation of the crystal while
Cprepresents the parallel capacitance created by the electrodes. Having both series
and parallel paths allows the crystal to be resonant at more than one frequency [13].
Overtone frequencies at odd harmonics are also possible but not necessary for the scope
of this design.
10
Figure 2.4: Basic Colpitts-Clapp Oscillator
Having such a high motional inductance, it is common practice to see a quartz crystal
used in place of an inductor in an LC oscillator. An LC oscillator is a type of feedback
oscillator that utilizes resonance of an inductor and capacitor to select the frequency
of oscillation. Feedback oscillators are governed by the Barkhausen stability criteria,
which require that the gain of the amplifier be greater than or equal to unity and
the input signal from the feedback path be in phase with the output [14]. To take
advantage of the series inductance that accompanies a quartz crystal, a Colpitts-Clapp
oscillator was chosen for its simplistic design.
Figure 2.4 shows a circuit diagram for a simple Colpitts-Clapp oscillator. Looking at
the circuit from the point of AC analysis, there are four main reactive components. Be-
ing an LC oscillator, resonance is achieved by a tank circuit whose frequency selectivity
is expressed by the following relationship.
f0=1
2π
pLsCeq
(2.1)
11
Equation 2.1 gives the expression for the resonant frequency of the tank circuit, f0, as
a function of the inductor, Ls, and the equivalent capacitance, Ceq . Combining all the
capacitors in series results in Equation 2.2.
Ceq = ( 1
Cs
+1
C1
+1
C2
)−1(2.2)
From the point of AC analysis, C1and C2create a reactive voltage divider at the
emitter of the transistor. The ratio of the two capacitors control the amount of positive
feedback being directed back into the amplifier. This is convenient as the closed loop
gain of the amplifier can then be expressed by equation 2.3.
Av=XC2
XC1
(2.3)
The fundamental frequency of the crystal resonator is set by the series inductance and
capacitance values given by the model shown in Figure 2.3. The crystal model then
can be used to replace the series LC tank circuit comprised of Lsand Csin Figure 2.4.
Being a drop-in replacement for the LC tank, it becomes clear as to why this circuit
topology is then a typical choice for a crystal oscillator. The values of Lsand Cs
can be substituted by the motional inductance and capacitance in the crystal. Since
the motional inductance is very large (likely in mH) and motional capacitance very
small (likely in fF), external components can be used to alter the resonant frequency
of the circuit, “pulling” the resonant frequency away from the intrinsic frequency of
the crystal [15]. The substitution of the crystal model and addition of external tuning
elements can be seen in Figure 2.5.
12
Figure 2.5: Basic Colpitts-Clapp Oscillator with Crystal Resonator and External Tun-
ing Elements
The pulling range of the crystal-controlled oscillator with the variable capacitor (Ct) is
likely limited by the extremely small capacitance of Csinside the resonator. Being on
the order of femtofarads, the Csterm dominates the total equivalent capacitance in the
circuit. Additionally, the inductor external to the crystal resonator (Lt) would need
to to be a very large, high Q inductor in order to be able compete with the motional
inductuance of the crystal. By placing one or more additional crystals in parallel at
the cost of sacrificing space on the circuit board, the motional inductance is decreased
while the motional capacitance is increased [16]. This should make the external tun-
ing elements more effective at pulling the frequency and extending the pulling range.
The value of Ltand Ctwill likely need to be determined either experimentally or by
component availability since the motional inductance and capacitance in the crystal is
unknown.
13
With a suitable plan of attack developing a tuning range across the band of interest, a
voltage control method was still needed in order to allow the MCU to switch between
transmit and receive frequencies. A method for acheiving this goal would be to place
a voltage-controlled capacitor (also known as a varactor) in parallel with the tuning
capacitor, Ct. The small signal junction capacitance (Cj) for a diode is given in
Equation 2.4.
Cj=Cj0
√ψ0+VR
(2.4)
In this equation, Cj0represents the intrinsic junction capacitance, ψ0is the built-in
potential, and VRis the reverse bias voltage [17]. One method of adding voltage-control
frequency tuning to this design would be to apply a voltage to a reverse biased Zener
diode in parallel with Ct. The Zener diode in this case acts as a voltage controlled
capacitor adding parallel capacitance to the tuning ciruit. This technique has been
employed in other direct conversion transceivers using a voltage regulator and poten-
tiometer acting as an incremental tuning system for zero-beating incoming signals [18].
Figure 2.6 shows the addition of the voltage-controlled tuning elements and parallel
crystal resonators.
Having developed an outline for a tunable oscillator, there still lies the issue of load
impedance and output power. The oscillator needs to be able to drive the ADE-1 ring
mixer with a 7 dBm into the 50 Ω LO port. In keeping with a design optimal for
battery usage, the transistor needs to have a DC biasing scheme resulting in around 1
to 3 mA of current draw. An RF choke (RFC) should also be added to Vcin order to
prevent RF leakage to power supply. Voltage across an inductor can be expressed in
the following form.
14
Figure 2.6: Voltage-Controlled Colpitts-Clapp Oscillator with Parallel Resonators
VL=LdIC
dt (2.5)
Equation 2.5 states that the voltage across an inductor is the product of its inductance
times the derivative of the current with respect to time [19]. By placing a large inductor
on the order of tens of mH at VC, a high impedance of a few kΩ is presented at the
collector. If ICis modelled as the sum of the DC and AC currents, then there is the
potential for VCto exceed the power supply voltage (Vcc), provided a transistor with
enough gain is chosen. A general purpose bi-polar junction transistor such as 2N3904
or BC547 having a βvalue in the 100 to 300 range would likely suffice for this purpose.
VC=Vcc +VLsin(ωt) (2.6)
15
This action has the potential for creating a very large voltage at the collect output
but with a high impedance. A simple technique for dropping this impedance is to
capacitively couple the output from the collector to an emitter-follower stage. Emitter
resistance for an NPN transistor can be calculated by equation 2.7 [21].
re=0.026
IE
(2.7)
By taking the output of an emitter-follower buffer stage, a modest current around 2
mA or less should provide an output impedance around 50 Ω or lower. This should be
suitable for reaching the drive levels needed by the product mixer.
2.4 Low-Pass Filter (LPF)
Looking back at Figure 2.1, the receiver design calls for two low-pass filters. The first is
an RF filter before the LNA stage intended to attenuate out-of-band signals above the
cutoff frequency and attenuate additional harmonics from the transmitter. The second
is an audio frequency (AF) filter intended to attenuate the 14 MHz RF signal coming
out of the mixer. The RF filter was designed first to have a characteristic impedance
of 50 Ω starting with equations 2.8 and 2.9 [9]. A table of normalized filter values is
shown in Table 2.1.
L(n) = g(n)Z0
2πf (2.8)
C(n) = g(n)
2πf Z0
(2.9)
16
N g(1) g(2) g(3) g(4) g(5) g(6) g(7)
2 1.414 1.414
3 1.0 2.0 1.0
4 0.765 1.850 1.850 0.765
5 0.618 1.618 2.0 1.618 0.618
6 0.518 1.414 1.932 1.932 0.141 0.518
7 0.445 1.247 1.802 2.0 1.802 1.247 0.445
Table 2.1: Normalized Values for Butterworth Low-Pass Filters
Figure 2.7: 5th Order Butterworth Low-Pass Filter Designed for 7 MHz
Using the values in Table 2.1, design of the LPF is fairly trivial providing both loads
at the input and output of the filter have a characteristic impedance of Z0. Being that
the transistors chosen for this design are mostly general purpose, datasheets supplied
by the manufacturer don’t typically include S-parameter data. Therefore, it’s very
likely that some impedance matching will need to be done experimentally to ensure
optimal performance. Figure 2.7 shows a 5th-order low-pass Butterworth filter design
with commonly-available component values.
For the audio filter, the same technique could be used for a third-order low-pass filter
at audio frequency. This is useful because the ADE-1 mixer needs to be properly
terminated with a 50 Ω load. A third-order filter should provide around 50 to 60
dB of attenuation at 10 kHz with some possible ripple in the pass band. Additional
filtering may also be achieved by inclusion in the design of the audio amplifier. Some
experimentation with component value here may be necessary to find an optimal level
17
Figure 2.8: Simplified Single-Tuned Amplifier Schematic
of attenuation above 1 kHz.
2.5 Low-Noise Amplifier (LNA)
The low-pass filter introduced in the previous section is a passive circuit. Undoubtedly,
there would be some loss in the the pass band of the filter even with components having
a relatively high Q value. Additionally, some attenuation for frequencies around 1 MHz
is desired since this is the range of the AM broadcast band [22]. Signals in this band
can be excessively strong and have the potentional to overwhelm the receiver. A simple
solution to this would be to use a single-tuned circuit as a low-noise amplifier to ensure
weak signal detection over the band of operation.
The single-tuned amplifier has seen use commonly as an IF amplifier in various forms of
superheterodyne receivers [23]. Design of this circuit generally begins with a resonant
RLC bandpass filter with a given center frequency and bandwidth[24]. Bandwidth
considerations can be made by choosing specific bias resistor values, thereby altering
the Q of the filter. Figure 2.8 shows a simplified schematic of this circuit topology.
18
Figure 2.9: RLC Bandpass Filter Circuit
From the point of an AC analysis looking at the node of the collector of the transistor,
the ratio of the voltage here to the bias current of the transistor appears as a resistance
(Rp). The schematic can then be simplified into the components of a basic RLC circuit
like that shown in Figure 2.9. The transfer function in the s-domain is shown in
Equation 2.10.
H(s) = 1
RC
s
s2+s
RC +1
LC
(2.10)
Analysis into the frequency domain produces the separate equations that are key pa-
rameterizations of a typical bandpass filter. There are the expressions of resonant
frequency (f0), bandwidth (B W ), and quality factor (Q), which are given in Equa-
tions 2.11, 2.12, and 2.13 [19]. A bandpass filter has two cutoff frequencies at the band
edges where the attenuation drops to 3 dB. These frequencies are the upper (fU) and
lower (fL) cutoff frequencies.
f0=1
2πpLpCp
(2.11)
19
BW =fU−fL=1
2πRpCp
(2.12)
Q=f0
fU−fL
(2.13)
By chosing a center frequency and bandwidth, the values of Lpand Cpcan be found by
picking a value for one and solving for the other. In this case, a 470 pF capacitor was
chosen initially, and the inductor value was calculated as a result. From the vantange
point of the collector, Rpis the ratio of the collector voltage (Vc) and collector current
(Ic). This expression is given below.
Rp≈Vc
Ic≈Vc
βIb
(2.14)
Equation 2.14 then represents a current-controlled resistance by way of the base current
of the transistor. Decreasing the base current increases the overall Q of the circuit,
making it a variable Q amplifier. By solving for a particular biasing scheme, the
parameters of the filter can now be established. An impedance transformation and
isolation of the RF signal from the collector will likely need to be added in order to
ensure a good 50 Ω match. Some frequency shift may also occur due to the internal
capacitance of the transistor, but this gives a sound method for the foundation of the
design work. Design of the input and output matching networks in Figure 2.8 will be
determined by the characteristics of the transistor over the operating frequency range
and the loading requirements of the product mixer.
20
Figure 2.10: Simplified Dual-Stage Audio Amplifier Schematic
2.6 Audio Amplifier
The final section of the receiver is the audio amplifier where RF downconverted into the
audio spectrum gets delivered to a speaker of some kind. The target load in this case
would be somewhere around 300 to 500 mW into a small 8 Ω speaker. In order to save
space, an NE5532 dual operation amplifier was chosen to act as a dual-stage voltage
amplifier to drive a class AB complimentary transistor output stage. A simplified
diagram of this technique is shown in Figure 2.10.
The entire audio amplifier schematic can be broken into three make sections from left
to right. The first section is comprised of an active first-order low-pass filter using the
first half of the NE5532 opamp. Utilizing the inverting input of the opamp, there are
two main equations for the design [20].
Av=−Rf
Rs
(2.15)
21
fc=1
2πRfCf
(2.16)
The voltage gain (Av) of the input stage is set by the ratio of Rfand Rs, as shown
in equation 2.15. Equation 2.16 sets the cutoff frequency of the low-pass filter. The
filter provides additional attenuation in the audio range with a gentle slope of 6 dB per
octave combining with the passive filter between the input of the audio amplifier and
the mixer. This was included in the design to provide a way of dialing in an optimal
amount of filtering in the event more or less was needed. The output of the active
filter is then fed to a voltage-controlled mute switch that allows the MCU to mute the
audio when switching between transmit and receive.
The next stage is the second half of the NE5532, which acts as a voltage driver for
a class-AB output stage. According to the datasheet for the device, the maximum
short-circuit output current is 60 mA, which means that the opamp itself isn’t ideal
for driving a low-impedance load at the desired power level. It can, however, produce a
very high voltage gain into a high-impedance load. Utilizing two BJTs for the output
stage with a high βpresents a high-impedance to the output of the opamp. A feedback
network is then taken from the output of the next stage and fed to the input. Using
Equations 2.15 and 2.16, this amplfier can also act as another active filter if additional
filtering is desired.
The output stage is a class-AB complementary symmetry amplifier stage composed
of PNP and NPN BJTs. This acts as a current amplifying device that takes the
small current output from the opamp and delivers the current to the loudspeaker or
headphones. The class of power amplifier is ultimately determined by its conduction
angle and class-AB is really a combination of two separate classes [25]. Class A is when
22
the conduction angle is a full 360◦of the input signal. This means that the transistor
is biased on through the entire cycle of a sinusoidal input. Class B by comparison is
when the conduction angle is 180◦of the input signal or half of the input signal. By
splitting the input signal into two halves, the efficiency of the amplifier can be increased.
However, a bias voltage of around 0.6 V is needed to turn the transistor on. Therefore,
Class-B operation produces noticeable distortion products in the audio range known as
crossover distortion. Class-AB is the compromise to this where the conduction angle
for both transistors is greater than 180◦but less than 360◦[25]. The DC bias network
shown in Figure 2.10 sets the bias so that crossover distortion products are eliminated
while also keeping efficiency in the 60-70% range. This technique should provide a very
clean audio output keeping distortion products to a minimum and providing less audio
distortion over a commercially available IC audio amplifier like the LM386 [26].
23
Chapter 3
Transmitter and Switching Circuitry
3.1 Transmitter Functionality
In this section, the design specification for the transmitter and switching sections of the
transceiver are outlined. This transceiver system is centered around the local oscillator
being switched between the transmit and receive circuitry. When the keyer switch is
open, the system is in receive mode and the LO is connected directly to the product
mixer. For transmit, the LO is connected to the input of the amplifier. The drive level
of the LO, however, is design to deliver +7 dBm or 5 mW of power. A desired transmit
level would be somewhere around +30 dBm (1 Watt) or greater. In order to acheive
at least 23 dB of gain, a dual-stage power amplifier design will likely be required. The
first stage will provide voltage gain using a small signal transistor while the second
stage will provide the current gains for deliviering power to a 50 Ω load.
The design techniques and theory used for switching between transmit and receive will
also be outlined in this chapter. This will include design of the RF switches them-
selves as well as discussion of control bus management with the MCU. The MCU has
multiple fuctions that tie the system together including the sidetone oscillator, which
provides keying feedback to the operator. Being a programmable MCU, a discussion
of additional features that are purely based in software is also warranted.
24
Figure 3.1: Transmitter Section of the Direct Conversion Transceiver Block Diagram
3.2 Driver Stage
As mentioned previously, the power amplifier section needs to first contain a small
signal voltage driver. Being a portable radio transceiver operated by battery power,
some forethought should be given to amplifier effeciency.
η=Pout
PDC
=Pout
Pout +Pdiss
(3.1)
Equation 3.1 is the expression for amplifier efficiency (η) where Pout is the RF power
output and PDC is the total power drawn from the power supply [27]. The efficiency of
a power amplifier is usually associated with its class of operation. A discussion of the
audio power amplifier in the previous chapter gives a description of classes A, B, and
AB in terms of conduction angle for the active device delivering power to the load. By
exploiting the conduction angle, amplifier efficiency can be increased since the amount
of time that the transistor is conducting is reduced. In turn, this decreases the power
dissipated (Pdiss). For the design of the voltage driver, a BS170 MOSFET was chosen
25
Figure 3.2: Simulated I-V Characteristics for a BS170 MOSFET
due to availability, maximum Vds rating of 60 V, and power dissipation capability given
its package size. The I-V characteristics for this transistor are shown in Figure 3.2.
Using the I-V curves, loadline analysis for a class A amplifier can be performed in
order to start the design. Design of this class of amplifier starts by using two simple
equations based around the quiescent current and DC supply voltage.
Ropt =VDC
Imax/2=VDC
IDC
(3.2)
Popt =1
2VDC IDC (3.3)
The two expressions given for Equations 3.2 and 3.3 can be used under the assumption
26
that the amplifier efficiency is 50% [27]. According to the transistor datasheet, the
device can handle up to 500 mA of continous current draw and dissipate up to 800 mW
[28]. Given a 12 V power supply, Equation 3.3 can be solved for IDC and subsequently
Imax. This provides the operating conditions for the driver and a way to draw the load
line using a realistic device [29]. However, a method of matching the output impedance
to the load is still needed in order to extract the RF power. Conversion of Ropt to a
complex impedance can be performed given the following relationships.
Zopt =Ropt +jXopt (3.4)
Xopt =rR2
opt(1 −1
p2) (3.5)
Looking at Equation 3.5, the term prefers to the efficiency factor of the amplifier. Being
class A offers 50% efficiency so phas a value of 2. From here, a complex impedance
(Z) can be calculated and matched to a complex load via a matching network [27].
Additionally, load-pull contours could also be plotted on a Smith chart and used for
matching purposes. Being a driver stage, there is an advantage in the fact that an
impedance higher than 50 Ω for driving the next stage can be used mainly since the
next stage will also be a MOSFET stage. Increasing the load seen at the output of the
driver stage to a few hundred ohms could effectively produce a larger voltage swing,
thus providing more voltage gain at the output of the next stage depending on the
drive requirements of the MOSFET. Figure 3.3 gives a simplified schematic for the
driver stage to be designed using the theoretical principles outlined in this section.
The value of R2 at the gate of the BS170 could also be reduced to lower the threshold
27
Figure 3.3: Simplified Schematic for a Class A Driver Stage
voltage effectively pushing the amplifier into class-AB operation if increased efficiency
is needed [30].
3.3 Final Stage
For the final RF amplifier stage, exploitation of amplifier efficiency would be desired
to reduce the power dissipated and still be able to achieve a higher output power level.
Another consideration comes from how the transmitting amplifier is switched into the
on state in that the input signal from the LO is switched on or off at the input to the
driver stage. Choice of class B or C would be a likely candidate here since the current
draw would be limited or practically zero if no signal is present at the input [32]. With
the driver configured for class-A operation, some power will be constantly dissipated
regardless of whether or not the system is transmitting. Reducing the conduction angle
will only help keep unnecessary power dissipation to a minimum in the receive state.
The design of the transceiver is intended only for CW, so linearity is less of a concern
over output power [31]. Therefore, an IRF510 power MOSFET was chosen for the final
28
transmitter stage. This transistor has a maximum drain-to-source voltage (Vds) of 100
V and can sustain a continuous drain current of 4 A [33].
Assuming a sinusoidal input to the amplifier, a waveform analysis can be performed
to illustrate how efficiency increases with the reduced conduction angle. Using the
symmetry of the input signal, a half conduction angle (θ) can be taken over the range
where the transistor is conducting. This allows for an expression of the quiescent
current (ICQ) in relation to a maximum current (Imax) and the half conduction angle.
The DC and fundamental current components then can be expressed in the form of
the Fourier series of the waveform and reduced to the equations 3.6, 3.7, and 3.8.
ICQ =Imax cos(θ) (3.6)
IDC =Imax
π[sin(θ)−θcos(θ)] (3.7)
I0=Imax
2π[2θ−sin(2θ)] (3.8)
Referring back to Equation 3.1 in the previous section, a formula for the maxium
efficiency of (ηmax) can then be expressed, as shown in Equation 3.9. A plot of this
expression as a function of θcan be seen in Figure 3.4 [32]. As θthen falls below π
2,
the PA enters class C operation. This increase in efficiency does come at the price of
reduced gain since less and less of the input signal is being represented at the output.
From the figure then, it would seem the best course of action to bias the amplifier in
29
Figure 3.4: Plot of Theoretical Amplifier Efficiency
such a way to keep the conduction angle as close to the class B point without going
into class B operation.
∴ηmax =2θ−sin(2θ)
4[sin(θ)−θcos(θ)] (3.9)
By applying no bias to the gate of the IRF510 from the power supply, the threshold
voltage should be high enough to keep the amplifier well in the class C operation region.
The output from the driver should be able to reach output levels of 5 V or higher to
effectively turn on the transistor. However, a Zener diode connect to a ground resistor
could also be placed at the gate to provide a short time constant that varies as the
voltage changes. A voltage develops as a result of the charge stored in the junction
capacitance. This effect has the ability to alter the quiescent current over the transition
into cutoff reducing amplifier efficiency. A simplified schematic is then shown in Figure
3.5.
30
Figure 3.5: Simplified Schematic of the IRF510 Final Stage Power Amplifier
3.4 Digital Transmit/Receive Switching
For the last section in this chapter, the method of switching still needs to be addressed
for the transceiver system to be functional. In the block diagram introduced in Fig-
ure 1.1, a number of single-pole switches can be seen connected to the MCU. These
switches need to be active RF switches with high isolation that respond to a digital
control signal. A common method of doing this would be a common-gate JFET shar-
ing the same supply bus as the MCU. Due to pricing, availability, and package size,
an Atmel ATTiny85 was chosen for the MCU. This chip can use a 5 V supply and
comes in an eight-pin dual inline package (DIP). The single-pole JFET switches then
can share the supply voltage with MCU and a control signal can effectively switch
the transistor on and off. The drain-to-source resistance of a JFET is generally deter-
mined by the approximation given in Equation 3.10, where gmrepresents the forward
31
Figure 3.6: Schematic for RF Switch Using a Common-gate JFET Amplifier
transconductance of the transistor [17]. A J310 has a typical gmof 14.1 mS even with
a minimal current draw, which translates to an impedance of around 70 Ω [34] and an
operable frequency range well into the UHF region. This makes it a good candidate
for use as an RF switch.
Rs≈1
gm
(3.10)
Figure 3.6 shows the schematic for the RF switch. Two capacitors provide DC blocking
at the input and output of the switch. The +5V supply is connected to the drain
resistor. The CTL port is where the digital control signal connect to the MCU. As the
control signal switches between high and low states, Rgand Cgcreate an analog time
constant that creates a small delay as the signal switches. Component values can be
determined experimentally to minimize pops or clicks that could wind up at the output
of the audio amplifier. Rgalso acts as a pull-up resistor, keeping the gate voltage high
32
Figure 3.7: Pinout for the ATTiny85 8-bit Microcontroller
and keeping the switch ON with a high logic value.
The ATTiny85 AVR microcontroller has an 8-pin package featuring 8 kB of in-system
programmable flash memory and six programmable I/O pins available for use as digital
control lines [35]. This allows for the creation of a transmit (TX), receive (RX),
and frequency adjust (ADJ) bus. The ATTiny85 also includes an 8-bit high speed
timer/counter with separate prescalar, which can be utilized for the sidetone oscillator
(SOSC). The switch control pin is assigned to a 10-bit ADC, which will receive two
separate voltages for the keyer and spot controls. Figure 3.7 shows the pinout and
their various functions.
33
Chapter 4
Receiver Module Characterization
4.1 Local Oscillator
In this chapter, the individual receiver modules highlighted in Figure 2.1 are designed
using the criteria and methods outlined in Chapter 2 and then simulated using a circuit
simulator software known as LTSpice. Once adequate performance was achieved in
the simulator, individual modules were assembled and characterized on a bare piece
of copper-clad FR4 laminate. The results for each module are given in the following
sections.
Being a critical peice of the entire transciever for both transmit and receive, the ma-
jority of the time spent on development was done with the LO. After many variations
of the simplified design given in Figure 2.6, suitable performance was obtained. The
simulated schematic shown in Figure 4.1 produced oscillations in the frequency range
but required some manipulation to produce the expected result of a crystal stabilized
oscaillator. One such idealization includes the current source (I1). This current source
acts as an impulse function and provides a short pulse of current to reduce simulation
time needed to create the oscillations. Using this technique produces a signal at the
output in less than 200 µs and required only about 10 s of processing time during the
simulation.
34
Figure 4.1: LTSpice Schematic for the Local Oscillator
In order to acheive some level of accuracy with the non-linear devices in the circuit, a
model for the 2N3904 transistor was downloaded from ON Semiconductor’s web site.
Three physical transistors were selected and had their DC characteristics compared
with simulator. Three copies of the supplied model were then made with each having
their beta values adjusted to match the measured values of the physical ones. This at
least created similar but not identical transistors for the purposes of simulation. The
simulated fast Fourier-transform (FFT) of the oscillator output is given in Figure 4.2.
The parallel crystal resonators shown in the simplified schematic proved to be some-
what difficult to simulate in LTSpice. Therefore, pulling range and automatic frequency
offset range were determined experimentally. In fact, the value of Lsshould be in the
mH instead of µH as given in Figure 4.1. By reducing the value of Lsand increasing
the value of Cs, this is basically the same tactic employed by placing multiple crystal
resonators in parallel, but the values needed to produce the oscillation in the simulator
are unrealistic and result in overly optimistic performance. In simulation, the focus
35
Figure 4.2: Simulated FFT of Local Oscillator Output
Parameter Simulated Measured
IDC 8.2 mA 10.6 mA
PDC 95 mW 125 mW
VP eak 935 mV 720 mV
PRF 9.71 dBm 7.15 dBm
Table 4.1: Simulated/Measured Comparison Table for Local Oscillator
was then getting the most power output and determining the functionality of the fre-
quency offset. Table 4.1 gives a comparison of measured performance metrics versus
simulated.
Figure 4.3 shows the build of the LO while Figure 4.4 shows the power output of the
fundamental frequency using a 7.055 MHz crystal. One interesting thing regarding the
measured performance of the LO was how the power output changed as the frequency
was pulled. If the series inductor value was too large, the power output would drop
considerably towards the end of the pulling range. Using +4 dBm as the minimum
power output needed to drive the ADE-1 mixer, an FT37-67 toroid was wound with 30
turns and then backed off experimentally until and adequate drive level was achieved
across the tuning range.
36
Figure 4.3: Build of Local Oscillator Module
Figure 4.4: Measured Power Output of Local Oscillator Build
37
Figure 4.5: Measured Harmonic Content of Local Oscillator with Output Filter on
Agilent N9030A
A third-order Butterworth filter was placed at the output of the LO to attenuate the
harmonic content of the ouput signal. This provided a clean input signal to the ADE-1
at the fundamental frequency. Figure 4.5 shows the harmonic content of the LO up to
40 MHz. From the this measurement, the output filter provides 30 dB of attenuation
at the second harmonic and 54 dB at the third harmonic, which makes for adequate
filtering into the product mixer. Harmonics above the third harmonic are attenuated
into power levels at -70 dBm or less, which is far below any useable power level by the
mixer. This made for a fairly clean signal for driving the ADE-1 over the region of
operation.
4.2 Low-Noise Amplifier (LNA)
For the low-noise amplifier, a few different transistor models were used to develop the
design in simulation. Ultimately, the designs using the 2N3904 and BC547C devices
38
Figure 4.6: LTSpice Schematic for the Single-tuned Low-noise Amplifier
were built and characterized since both devices were readily available. The 2N3904
design provided the most gain over the range of operation by more than 10 dB and was
included in the final design for this reason. The schematic capture shown in Figure
4.6 shows the final design used for the transceiver system. The simulated LNA circuit
produced a quiescent current draw of around 7.3 mA for both stages with 11.5 V
applied to VCC . By comparison, the measured current on the module came in sightly
higher than the simulated current at 9.4 mA. A picture of the LNA module is shown
in Figuer 4.7.
Figure 4.8 provides a plot of the simulated S-parameters provided from LTSpice. The
plot of S21 shows gains of more than 40 dB over the range of operation. Attenuation
of the input signal at 1 MHz was less than ideal having a simulated gain of 12.9 dB.
However, the LNA starts to attenuate signals above 14.4 MHz, which contributes to
any filtering done after the antenna. The plot of S11 shows a good 50 Ω match around
7.15 MHz and the best match at 7.82 MHz, but this was less of a concern being that the
LNA doesn’t provide much power to the load. Gain was the key performance metric
39
Figure 4.7: Build of Low-noise Amplifier Module
Figure 4.8: Simulated S-parameters for Single-tuned LNA
utilized for the purpose of the transceiver design.
Comparing measured performance with the simulation, Figure 4.9 shows the measured
S-parameters of the LNA module as measured on a vector network analyzer (VNA).
The inductor labeled L1 in Figure 4.6 was wound manually on a T37-25 toroid and
likely produced a value slightly higher than 1.01 uH given the S21 plot shown. However,
the overall performance was still adequate for the purposes of the design, yielding
40
Figure 4.9: Measured S-parameters for Single-tuned LNA Using Agilent E5071C VNA
more than 38 dB of gain over the band of operation. Additionally, the measured data
shows more attenuation at 1 MHz, which is benficial at keeping strong signals in the
AM broadcast band from overloading the receiver. The plot of S11 didn’t match the
simulation results hardly at all, but performance is still likely adequate for the intended
use of the LNA.
4.3 Audio Amplifier
As mentioned in Chapter 2, the design of the audio output stage for the receiver revolves
around an NE5532 dual op-amp. A schematic of the design simulated in LTSpice is
shown in Figure 4.10. The first op-amp (labeled U2) acts as an active first-order
low-pass filter having a voltage gain of around 50 dB. The input to the second stage
is driven by the other half of the NE5532 (labeled U1), which supplies voltage gain
for the complementary-symmetry output stage created by a pair BC547 and BC557
41
Figure 4.10: LTSpice Schematic for the Receiver Audio Stage
Figure 4.11: Audio Output Capture at 1 kHz into a 32Ω Load Using Agilent DSO-X
3040A
transistors (Q1 and Q3 respectively). Q2 sets the bias point both Q1 and Q3 and
results in a class-AB output stage for delivering audio to the speaker or headphones.
With a 32Ω load, the amplifier provided more than 90 mW at 1 kHz. That’s enough
to exceed the threshold of pain in most earphone applications and enough to drive a
small speaker [36]. A time domain capture of the measured output from the circuit
built on the module can been seen in Figure 4.11.
42
Figure 4.12: Simulated and Measured Amplifier Frequency Response Normalized at 1
kHz
The plot shown in Figure 4.12 gives a comparison of the measured and simulated
frequency response of the amplifier. The output was normalized to 1 dBV at 1 kHz at
the output of the amplifier and then the frequency was swept from 100 Hz to 10 kHz.
Given the filtering on both stages, the frequency response shows a steeper roll off at
high frequencies and a lower cuttoff point in simulation when compared to the measured
response. However, the response of the amplifier provides 25 dB of attenuation at 10
kHz.
The low frequency attenuation shown in Figure 4.12 is largely a result of a DC blocking
capacitors having a lower value in circuit module. Due to the high gain of the amplifier
at low frequencies, large clicks or pops created when keying the amplifier resulted in
low frequency oscillations. These oscillations could be halted pretty easily by turning
down a potentiometer between C6 and R7, but the value of C3 and C6 were reduced
from 10 µF to 1 µF to reduce gain. The values of the RC network in the feedback
path for each stage could also be adjusted to lower the gain while retaining the cutoff
43
frequency in the event that oscillations become a problem in the finished transciever.
44
Chapter 5
Transmitter and Switching Module Characterization
5.1 Power Amplifier Characterization
This section outlines the characterization of the transmitter circuitry to be used in the
transceiver. As discussed in Chapter 3, the target specification for the power amplifier
section swas to be able to deliver a continuous wave (CW) signal with a power level of
30 dBm or more power into a 50 Ω load. The amplifier was designed in such a way to
keep quiescent currents to a minimum so that a single JFET switch could be placed
between the input to the PA and the LO. This would allow the LO to drive the PA
during transmit. The JFET switch had its gate connected to a control bus so that
a microprocessor could then turn the amplifier on and off just by muting the input
signal.
The PA is composed of two sections: the driver and the final amplifier. For the sake of
testing and loading, the PA was assembled originally on a single piece of copper-clad
laminate and then tested again on the final printed circuit board. The test results
presented here are measured on the final circuit board mounted inside the shielded
enclosure, as shown in Figure 6.6. PA measurements varied between shielded and
unshielded tests. Figure 5.1 shows the schematic of the circuit simulated in LTSpice. A
comparison of the simulated and measured output in the time-domain from a Tektronix
45
Figure 5.1: LTSpice Schematic of the Power Amplifier Design
Figure 5.2: Simulated and Measured Comparison of Power Amplifier Output
TDS 360 digital oscilloscope is shown in Figure 5.2. From the plot of the output, the
overall power output tracks fairly well, resulting in a difference of 1.3 dB. With a supply
voltage a 11.5 V, The output power of the PA was measured at 34.7 dBm, which is
in the vicinity of 3 watts. Given a DC current of 550 mA, this gives a power-added
effeciency (PAE) of 46.5%. This varies from simulation by a large margin since the
simulator is able to get more power while consuming only 504 mA of current. This
results in a simulated PAE of 68.9%.
46
Figure 5.3: Spectral Content of the Power Amplifier Output Measured with Agilent
N9030A Spectrum Analyzer
Figure 5.3 displays the measured spectral output of the power amplifier. In this plot,
the overall effectiveness of the output filter in attenuating higher order harmonics can
be seen. The setup for this measurement included a 20 dB attenuator on the input
of the spectrum analyzer. Therefore, measurements in the plot are 20 dB below their
actual value. The second harmonic of the CW output signal is attenuated by 48.1 dB,
resulting in an output power of -13.4 dBm. This is in compliance with the FCC’s Part
97 emission standards for transmissions below 30 MHz [37]. Higher harmonics don’t
see as drastic of a reduction like that between the fundamental and second harmonic,
but power levels fall to or below -30 dBm and are acceptable. Power levels appear to
drop off into the noise floor beyond the seventh harmonic.
47
Figure 5.4: Measured Switching Time of JFET Transistor Switch on Tektronix TDS
360 Oscilloscope
5.2 RF Switch Measurements
The RF switch design using a J310 JFET transistor shown in Figure 3.6 was also
assembled on the printed circuit board and tested by measuring the PA turn-on time.
In order to examine the switching time of the transistor alone, the capacitor, Cg, at
the gate of the transistor was removed. This eliminated the short delay introduced by
the time constant created by Rgand Cg. The LTSpice simulation results measured a
turn on time of 7.5 µs and a current draw of 4 µA. This varied somewhat from the
measurements taken on a Tektronix TDS 360 digital-storage oscilloscope as shown in
Figure 5.4. The measured turn-on time was more than double the simulation results
at 14.8 µs and drawing 10 µA of current. Despite both measurements being off by a
factor of more than double, the differences are still negligible in terms of this design.
48
Figure 5.5: Schematic of MCU Transceiver Application Circuit
5.3 Digital Control
The final section in Chapter 3 gives the specification of a control bus for each function-
ing block of circuitry. The schematic in Figure 5.5 shows the electrical configuration
and pin assignment for the ATTiny85P MCU. Since the JFET switches have been
designed to work with a +5 V control signal, there are three pins dedicated as outputs
to enable and disable various RF switches. These are 5-volt digital logic output sent
from the MCU for manipulating the TX, RX, and SPOT CTL busses. Pin 2 (PB3) is
an input pin on the MCU connected to the 10-bit analog-to-digital converter (ADC).
Using the ADC on PB3 is useful since a number of control input signals could then be
created by using different voltage levels. In the schematic, R10 acts as a pull up resis-
tor until either the SW1 or SPOT switch is connected. Placing R38 in series with the
SPOT switch allows the MCU to see two different voltages, depending on which switch
is pressed. This technique was used to create a spot feature allowing the operator to
zero-beat the incoming signal by listening on the transmit frequency.
49
The application of the spot feature was found to be very useful when operating on the
air. When the SPOT switch is connected to ground, a logic high signal is applied to
the SPOT CTL bus. This bus was connected first to a potentiometer and then to the
frequency control line on the local oscillator. In operation, a signal can be heard on
either the upper or lower side band of the LO frequency. The operator adjusts the
tuning knob until the calling station is on the upper side of the LO frequency. Once
the station’s tone is around 500 to 700 Hz, pressing the SPOT button on the front
of the radio switches the LO from the receive frequency to the transmit frequency.
The transmit frequency will always be above the receive frequency. The potentiometer
connected to the SPOT CTL bus then acts and a transmit incremental tuning (XIT)
control in order to best zero-beat the incoming station. Once the calling station can
no longer be heard, releasing the SPOT switch returns the LO to the receive frequency
where the station can again be heard.
5.4 MCU as a Side-tone Oscillator
In order to have audible feedback when keying the transceiver, pin 6 (PB1) was con-
nected to the MCUs internal Timer1 and configured for PWM mode to act as a side-
tone oscilltor. A 32-byte look-up table was created in the program to contain amplitude
values of a sine wave. The PWM mode of the ATTiny85 produces an output compare
match when the value of the output compare register is reached. By setting the out-
put compare register to the amplitude value of the waveform in the look-up table, the
PWM output of the pin has a varying duty cycle at the clock frequency. A 14-bit
prescalar can by applied to the clock frequency, effectively slowing down the rate of
the PWM signal. With a 32-byte waveform, the PWM frequency could be at least 32
times the audio frequency. Adding a very lossy first order audio filter on the output,
50
the high frequency PWM signal can be removed, leaving an 8-bit audio signal. While
this signal isn’t by any means a pure sine wave, enough filtering makes it sound good
enough for feedback purposes. A clear tone of 600 Hz is heard on the output of the
audio amplifier whenever the transmitter is keyed up.
51
Chapter 6
Results and Discussion
6.1 Schematic and Board Layout
This chapter primarily deals with the construction and board-level testing of the
transceiver system as a whole. A small 3.5 by 4 inch aluminum enclosure houses
the double-sided printed circuit board (PCB), which contains all the transceiver cir-
cuitry. The footprint of the board has the dimensions of 3.5 by 3 inches in order to
make space for the controls and connections needed on the front and back panels. The
schematic capture and PCB layout was drafted in EagleCAD and are shown in Figures
6.1 and 6.2 respectively. PCB manufacturing was done by Osh Park, and assembly
began on arrival. The first fully assembled transceiver unit was actually stolen after
being field tested and left overnight in a vehicle. A second assembly was built, which
provided most of the data presented in this document.
6.2 Board-level Testing
Initial bring-up of the board started by assembling the LO circuitry so that voltage
measurements of its output could be taken and troubleshooted before adding addi-
tional components. The original board layout had only two crystal resonators and was
adapted to include four in a later revision. Due to time constraints, the routing around
52
Figure 6.1: Full Transceiver Schematic
53
Figure 6.2: Full Transceiver Circuit Board Layout
the resonators is rather crowded. From frequency measurements of the LO, there must
be some amount of board capacitance either from the traces or ground relief as the
highest frequency possible from the LO was lower than the markings on the crystal by
4 to 5 kHz. Some care had to be taken in order to achieve a reasonable tuning range
with a constant power output over the band.
Some adjustments also had to be made to the PA in order to reduce LO leakage on
the output of the antenna port. The isolation of the JFET switch was such that a
54
Figure 6.3: Transmitter Signal Received on a Software-Defined Radio in Corinne, Utah
small signal was appearing at the input to the BS170 driver stage. At the antenna,
power levels of around 10 dBm were originally observed. A small reduction in the bias
voltage on the gate reduced LO leakage to a negligible level (around -20 dBm) while
also causing a 1.4 dB drop in overall output power. Ideally, a redesign of the bias
control and an improvement in RF isolation of the JFET switch could aid in reducing
the LO leakage, but the power amplifier did see a small boost in efficiency since the bias
reduction slightly reduced the overall DC current. The power reduction also aided in
some other issues where the high output signal during transmit could damage various
unshielded components on the board.
6.3 On-Air Test Results
Testing the transceiver over the air proved to have its own challenges. Having done
most on-air testing in a major metropolitan area, there are several sources of electro-
magnetic interference (EMI) resulting in heavy noise at times. Additionally, finding
space to deploy an antenna for the 40 m band is also challenging. On-air tests were
performed with either a wire dipole or long wire tuned for an approximate 50 Ω match.
55
Figure 6.4: Stations Reporting Received Transmissions on the Reverse Beacon Network
The Reverse Beacon Network was extremely useful for observing the propagation of
test transmissions, as shown in Figure 6.4. The furthest distance reported from Tucson,
Arizona at a distance of 1103.5 miles from the source of the transmission. Additionally,
SDR receivers in Utah and California provide access via the internet allowing for re-
mote operation. Figure 6.3 shows a capture of the transceiver being received on 7.038
MHz.
Reception tests involved recording the audio output signal with a digital recorder so
that frequency analysis could be performed. In Figure 6.5, two sections of separate
audio recordings can be seen as a logarithmic spectrogram. The spectrograph on the
left side of the figure shows received audio without the various low-pass filters. The
right side of the figure is an audio recording with the filters in place and a clear drop-
off in signal strength around 3.6 kHz. This tracks well with the frequency response of
the amplifier shown previously in 4.12. Some stations can still be seen in the filtered
audio capture, but the increased attenuation at higher frequencies adds to the overall
selectivity of the receiver.
Both spectrographs in Figure 6.5 capture a number of distant stations. The strong
56
Figure 6.5: Logarithmic Audio Spectrograph with and without Multi-stage Filtering
signal around 690 Hz on the left side is station call sign N5AW in Burnet, Texas at a
distance of 1660 miles from Portland, Oregon. On the right, station N7IV in Minot,
North Dakota shows up around 549 Hz coming in from a distance of 1023 miles. When
tested in remote areas, some stations were strong enough that the volume had to
be adjusted to more comfortable levels despite less-than-optimal antenna deployment
during test.
6.4 Future Work
Overall, the final build on PCB, as shown in Figure 6.6, performed very much in line
with individual module tests. However, some minor component changes had to be
made in order to improve general operability of the system. The value of the DC
blocking capacitor at the input to the audio section was adjusted from 10 µF to 0.1
µF to reduce oscillations. Due to leakage of RF back into the mixer during transmit,
a strong impulse results as a loud pop on the audio output. When the system is first
57
Figure 6.6: Assembled PCB Mounted in the Aluminum Enclosure
powered on or has not been keyed up in a while, the pop is still very apparent even with
this modification, and a very low frequency oscillation can result in some situations.
Additional design work could be done here to improve the interaction between the
output of the mixer and input of the amplifier.
Additionally, switching between the two pairs of crystal resonators produced some odd
results with respect to frequency tuning range. When comparing the pulling range of
both sets, the pair of resonators with the lower frequency consistently had more than
double the tuning range of the pair with the higher frequency. The lower frequency
pair also seemed to have more stability issues towards the bottom end of the tuning
range. In order to combat this problem, four crystals of the same frequency were
used and connected in parallel. This provided more frequency stability and consistent
power output from the LO while offering 15 kHz of tuning range (7.026 MHz to 7.041
MHz). While this is acceptable in terms of operation, having frequency agility across
the entire CW portion of the 40m band would be preferable.
58
Figure 6.7: Completed Transceiver and On-air Test Station
6.5 Conclusion
Figure 6.7 shows the transceiver system configured for on-air testing. Many stations
have been received under less-than-optimal conditions given the location in a major
metropolitan area, and the transmitting signal was received by stations more than a
thousand miles away. The addition of the MCU to a predominantly analog environment
within the direct-conversion system did not result in any adverse effects and provided
precision control to the TX, RX, and LO sections of the transceiver. With a 11.5 V
supply to simulate the average voltage of a 12 V battery, the transceiver pulls 45 mA
of current during receive and 520 mA of current during transmit. This level of current
draw makes it ideal for portable use with AA alkaline batteries or rechargable batteries
capable of producing a 12 V supply.
59
Appendix A
AVR Controller Program
A.1 Keying Control Code for AVR Microcontroller
[C++ Code for AVR]
# i n cl u d e < a vr / i o . h >
# i nc lu d e < av r / in t er r up t . h>
# d ef i ne cb i ( sf r , b i t ) ( _ S FR _ B YT E ( s fr ) & = ~ _ BV ( b it ) )
# d ef i ne sb i ( sf r , b i t ) ( _ S FR _ B YT E ( s fr ) | = _ BV ( b i t ))
# d e f i n e T X 0 // T X e n a b l e p i n
# d e f i n e R X 2 // R X e n a b l e p i n
# d ef i ne SO S C 1 // Si de - t on e o s ci l la t o r o ut p ut pi n
# d ef in e S W 3 // in p ut sw i tc h p in
# d ef in e A D J 4
# d ef in e N 10 // N pe r io d s i n m o no p ul s e m od e
long sw = 10 2 4 ;
bool t ri g = L OW ; // m on o p u l se t r i gg e r s t a t us
bool tx = L OW ; // flag fo r T X e n a b l e
bool k ey e r = L O W ; / / flag for start of k ey pre s s
int m o d e = 0;
int d i t = 5 0 ; // delay t i m e f o r d i t i n ms
int dash = 150; / / d e l a y ti m e fo r d a s h in ms
int m u t e = 0 . 1 1 ; // d e l a y ti m e fo r m u t e in ms
unsig n e d l o n g h ol d = 5 e 6 ; // max ho l d va l u e
unsig n e d l o n g p au s e = 1 e 7 ; // p a u s e b e t w ee n I D s
unsig n e d l o n g start = 0; // s t a r t t i m e
unsig n e d l o n g last = 0; // time of last ID ;
long c = 0; // c o u n t vari a b l e f o r m o d e c h a n ge
int i n d e x = 0; // i n d e x f or side tone PWM value
u in t8 _t wa ve Ta ble [] = {
// - -- SI NE WA V E ( 32 Sa m p le s ) - - - //
128,152,176,198,218 ,234 ,245 ,253 ,255 ,253 ,245 ,234 ,218 ,198 ,176 ,152,
1 28 , 1 03 , 79 , 5 7 , 3 7 , 2 1 , 1 0 , 3 , 1 , 3 , 1 0 , 21 , 3 7 , 5 7 , 7 9 , 10 3
};
60
void s et up ( ) {
// C on t r o l P i n s
p in M od e ( TX , O UT P UT ) ;
p in M od e ( RX , O UT P UT ) ;
p in M o de ( SO S C , O U T PU T ) ;
p in M od e ( ADJ , O U TP UT ) ;
// I n p u t Pin s
p in M od e ( SW , I NP U T );
cli();
/*--- TIMER1 CONFIG ---*/
T CC R1 = 0 b 11 1 00 0 01 ;
G TC CR = 0 b 00 0 00 0 00 ;
T IM SK = 0 b 01 0 00 0 00 ;
P LL CS R = 0 b 10 0 00 1 11 ;
/*--- TIMER0 CONFIG ---*/
T CC R0 A = 0 b 00 0 00 0 01 ;
T CC R0 B = 0 b 00 0 00 0 01 ; // l a s t 3 b i t s se t pr e sc a l a r fo r Ti m er 0
OCR1C = 255;
OCR1A = 128;
sei();
// u n mu t e RX
d ig i t al W ri t e ( RX , H IG H ) ;
d ig i ta l Wr it e ( TX , L OW ) ;
d ig i ta l Wr it e ( AD J , L OW ) ;
}
void l oo p () {
// pe rf o r m functio n b a s e d o n m o d e
sw = a n a lo g R e ad ( SW );
switch( m o de ) {
case 0:
if ( s w < 1 0 0) {
// k e y t h e T X
d ig i ta l Wr it e ( RX , L OW ) ; // m u t e R X
delayMicroseconds(mute); // s h o r t de l a y
d ig i ta l Wr it e ( AD J , H IG H ); // s e t A D J t o TX freq
d ig i ta l Wr it e ( TX , H IG H ); // b e g i n T X
}else if ( s w < 9 0 0) {
// mo ni t o r au d i o on T X f r e q
d ig i ta l Wr it e ( AD J , H IG H ); // s e t A D J t o TX freq
}else {
// r e tu r n to RX operat i o n
d ig i ta l Wr it e ( TX , L OW ) ; // s t o p T X
d ig i ta l Wr it e ( AD J , L OW ) ; // retur n A D J t o RX f req
delayMicroseconds(mute); // s h o r t de l a y
d ig i ta l Wr it e ( RX , H IG H ); // u n m u te RX
}
b re ak ;
case 1:
if ( l a st == 0 ) {
61
id ( ) ;
}else if (( m icr os ( ) - l as t ) > p au se ) {
id ( ) ;
}
b re ak ;
case 2:
if ( s w = = L OW ) {
pulse ();
}
b re ak ;
}
t ri g = L OW ; // m on o p u l se t r i gg e r r e s e t
}
ISR(TIMER1_COMPA_vect) {
if ( s w < 1 0 0) { // start up the side tone o s c i l la t o r
if ( i n de x < 3 2) {
O CR 1A = w a ve T a bl e [ i nd ex ];
index ++;
}else {
index = 0;
O CR 1A = w a ve T a bl e [ i nd ex ];
}
}else {
OCR1A = 128; // turn off side tone
}
}
ISR(TIMER0_COMPA_vect) {
sw = a n a lo g R e ad ( SW );
if ( s w < 1 0 0) {
if ( k e ye r = = H IG H ) {
mo de Ch k () ;
}else {
start = m ic ros () ;
k ey e r = H I GH ;
trig = HIGH;
}
}else {
k ey e r = LO W ;
}
}
void m od eC hk ( ) {
if ( ( mi c ro s () - s ta rt ) > h ol d ) {
if ( m o de < 2 ) {
mode ++ ;
}else {
mode = 0;
}
start = m ic ros () ;
stat () ;
delay (10 00 );
}
}
62
void p ul se ( ) {
// pu l s e TX on and o ff N times
d ig i ta l Wr it e ( RX , L OW ) ;
d el a y ( mu te );
for(int n = 0 ; n < N; n + + ) {
d ig i t al W ri t e ( TX , H IG H ) ;
delayMicroseconds(500);
d ig i t al W r it e ( TX , L OW ) ;
delayMicroseconds(500);
}
d el a y ( mu te );
d ig i ta l Wr it e ( RX , H IG H ) ;
}
void s ta t () {
d ig i ta l Wr it e ( RX , L OW ) ;
d el a y ( mu te );
// t a p o u t m o de n u m b e r i n m o r s e c o d e
f or (int n = 0; n < m o d e ; n++) {
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
}
for(int n = 0 ; n < (5 - m o d e ); n ++ ) {
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
}
}
void id ( ) {
// t a p o u t I D for K 2 N X F
// K
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh );
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh );
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( da sh );
// 2
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
63
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh );
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh );
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh );
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( da sh );
// N
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh );
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( da sh );
// X
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh );
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( da sh ) ;
// F
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( da sh ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( di t ) ;
64
d ig i t al W ri t e ( TX , H IG H ) ;
d el a y ( di t ) ;
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( da sh );
// n e w w o r d
d ig i t al W r it e ( TX , L OW ) ;
d el a y ( da sh );
d el a y ( mu te );
d ig i ta l Wr it e ( RX , H IG H ) ;
last = m ic ro s () ; // s t or e c u r re n t t i m e a t e n d of ID
}
65
Appendix B
Bill of Materials
B.1 List of Materials Used in the Final Transceiver
Qty Value Description Price Cost
1 78L05 5V Voltage Regulator $0.67 $0.67
5 100 nF KEMET Ceramic Capacitor $0.26 $1.30
2 100 uF KEMET Ceramic Capacitor $0.26 $0.52
2 10 nF KEMET Ceramic Capacitor $0.26 $0.52
1 10 pF KEMET Ceramic Capacitor $0.26 $0.26
6 10 uF KEMET Ceramic Capacitor $0.26 $1.56
1 150 pF KEMET Ceramic Capacitor $0.26 $0.26
11 1 nF KEMET Ceramic Capacitor $0.26 $2.86
4 22 nF KEMET Ceramic Capacitor $0.26 $1.04
1 330 pF KEMET Ceramic Capacitor $0.26 $0.26
1 33 nF KEMET Ceramic Capacitor $0.26 $0.26
9 470 pF KEMET Ceramic Capacitor $0.26 $2.34
1 680 pF KEMET Ceramic Capacitor $0.26 $0.26
3 1N4148 Fast Switching Diode $0.10 $0.30
1 12 V Zener Diode (12 V, 1 Watt) $0.24 $0.24
1 5.6 V Zener Diode (5.6 V, 1 Watt) $0.24 $0.24
1 11 V Zener Diode (11 V, 1 Watt) $0.26 $0.26
2 2N3904 ON Semiconductor NPN Transistor $0.20 $0.40
3 J310 InterFET N-Channel JFETs $3.27 $9.81
1 ADE-1 Mini Circuits ADE-1+ Level 7 Mixer $5.49 $5.49
1 ATTINY85-20P Atmel ATTiny85-20PU $1.20 $1.20
4 BC547 ON Semiconductor NPN Transistor $0.20 $0.80
1 BC557 ON Semiconductor PNP Transistor $0.21 $0.21
1 BS170 Fairchild N-Channel Enhancement MOSFET $0.45 $0.45
1 30 pF Trimming capacitor $4.54 $4.54
2 7.055MHz Crystal Resonator $1.13 $2.26
1 IRF510 Vishay N-Channel Enhancement MOSFET $0.88 $0.88
1 3mm LED $0.10 $0.10
1 NE5532N Dual Operational Amplifier $0.57 $0.57
2 100kA 100k Logarithmic Potentiometers $1.57 $3.14
1 10 1/8W Leaded Metal Film Resistor $0.01 $0.01
66
5 100k 1/8W Leaded Metal Film Resistor $0.01 $0.05
1 10MEG 1/8W Leaded Metal Film Resistor $0.01 $0.01
6 10k 1/8W Leaded Metal Film Resistor $0.01 $0.06
1 150k 1/8W Leaded Metal Film Resistor $0.01 $0.01
2 1MEG 1/8W Leaded Metal Film Resistor $0.01 $0.02
4 1k 1/8W Leaded Metal Film Resistor $0.01 $0.04
1 2.2 1/8W Leaded Metal Film Resistor $0.01 $0.01
4 2.2k 1/8W Leaded Metal Film Resistor $0.01 $0.04
1 2.7 1/8W Leaded Metal Film Resistor $0.01 $0.01
1 220k 1/8W Leaded Metal Film Resistor $0.01 $0.01
1 22k 1/8W Leaded Metal Film Resistor $0.01 $0.01
1 240k 1/8W Leaded Metal Film Resistor $0.01 $0.01
1 270k 1/8W Leaded Metal Film Resistor $0.01 $0.01
2 33k 1/8W Leaded Metal Film Resistor $0.01 $0.02
1 4.7k 1/8W Leaded Metal Film Resistor $0.01 $0.01
2 470k 1/8W Leaded Metal Film Resistor $0.01 $0.02
2 51 1/8W Leaded Metal Film Resistor $0.01 $0.02
1 680k 1/8W Leaded Metal Film Resistor $0.01 $0.01
1 SMA SMA 50 Ohm End Launch Jack Receptacle $3.74 $3.74
2 SPST Push-button SPST Switch $3.17 $6.34
1 3.5mm Stereo (TRS) 0.25 Inch Phone Jack $1.10 $1.10
2 FT37-23-12T Inductor wound on a T37 Toroid $0.49 $0.98
1 FT37-23-18T Inductor wound on a T37 Toroid $0.49 $0.49
1 FT37-67-12T Inductor wound on a T37 Toroid $0.49 $0.49
1 FT50-J-25T Inductor wound on a T50 Toroid $3.64 $3.64
1 T37-6-19T Inductor wound on a T37 Toroid $0.80 $0.80
1 T37-6-24T Inductor wound on a T37 Toroid $0.80 $0.80
3 T37-6-26T Inductor wound on a T37 Toroid $0.80 $2.40
1 T37-6-27T Inductor wound on a T37 Toroid $0.80 $0.80
1 PCB Printed circuit board $11.44 $11.44
1 Enclosure uxcell Aluminum Project Box 124x88x38mm $13.27 $13.27
Table B.1: Bill of Materials
Total Cost: $89.67
67
Bibliography
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[3] Krauss, Herbert L, et al. “Solid State Radio Engineering.” New York, John
Wiley & Sons, 1980.
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