Formal Verification of ECCs for Memories Using ACL2

Abstract

Due to the ever-increasing toll of soft errors in memories, Error Correction Codes (ECCs) like Hamming and Reed-Solomon Codes have been used to protect data in memories, in applications ranging from space to terresterial work stations. In past seven decades, most of the research has focused on providing better ECC strategies for data integrity in memories, but the same pace research efforts have not been made to develop better verification methodologies for the newer ECCs. As the memory sizes keep increasing, exhaustive simulation-based testing of ECCs is no longer practical. Hence, formal verification, particularly theorem proving, provides an efficient, yet scarcely explored, alternative for ECC verification. We propose a framework, with extensible libraries, for the formal verification of ECCs using the ACL2 theorem prover. The framework is easy to use and particularly targets the needs of formally verified ECCs in memories. We also demonstrate the usefulness of the proposed framework by verifying two of the most commonly used ECCs, i.e., Hamming and Convolutional codes. To illustrate that the ECCs verified using our formal framework are practically reliable, we utilized a formal record-based memory model to formally verify that the inherent properties of the ECCs like hamming distance, codeword decoding, and error detection/correction remain consistent even when the ECC is implemented on the memory.

Full text

https://doi.org/10.1007/s10836-020-05904-2
Formal Verification of ECCs for Memories Using ACL2
Mahum Naseer1·Waqar Ahmad1·Osman Hasan1
Received: 12 April 2020 / Accepted: 2 September 2020
©Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract
Due to the ever-increasing toll of soft errors in memories, Error Correction Codes (ECCs) like Hamming and Reed-Solomon
Codes have been used to protect data in memories, in applications ranging from space to terresterial work stations. In
past seven decades, most of the research has focused on providing better ECC strategies for data integrity in memories,
but the same pace research efforts have not been made to develop better verification methodologies for the newer ECCs.
As the memory sizes keep increasing, exhaustive simulation-based testing of ECCs is no longer practical. Hence, formal
verification, particularly theorem proving, provides an efficient, yet scarcely explored, alternative for ECC verification. We
propose a framework, with extensible libraries, for the formal verification of ECCs using the ACL2 theorem prover. The
framework is easy to use and particularly targets the needs of formally verified ECCs in memories. We also demonstrate the
usefulness of the proposed framework by verifying two of the most commonly used ECCs, i.e., Hamming and Convolutional
codes. To illustrate that the ECCs verified using our formal framework are practically reliable, we utilized a formal record-
based memory model to formally verify that the inherent properties of the ECCs like hamming distance, codeword decoding,
and error detection/correction remain consistent even when the ECC is implemented on the memory.
Keywords Error Correction Codes (ECCs) ·Memory soft errors ·Hamming codes ·Convolutional codes ·Formal
verification ·Theorem proving ·ACL2
1 Introduction
Soft errors are type of errors that do not cause permanent
damage to the semi-conductor devices [56], yet leading to
temporary faults in them. In particular, radiation induced
soft errors have been a major concern in semi-conductor
devices since 1970s [12,60]. In a long chain of events,
both the high speed protons in cosmic rays and the alpha
particles emitted during the decay of radioactive impurities
Responsible Editor: V. D. Agrawal
Mahum Naseer
mnaseer.msee16seecs@seecs.edu.pk
Waqar Ahmad
waqar.ahmad@seecs.edu.pk
Osman Hasan
osman.hasan@seecs.nust.edu.pk
1School of Electrical Engineering and Computer Science
(SEECS), National University of Sciences and Technology
(NUST), Islamabad, Pakistan
in IC packaging material, induce the silicon based semi-
conductor memories to change their logic states, hence
resulting in soft errors [10,47].
Recent advancements in technology, including circuit
miniaturization, voltage reduction, and increased circuit
clock frequencies, have augmented the problem of soft
errors in memories [10,48]. The most obvious drawbacks of
memory errors include the loss of correct data and the addi-
tion of faulty data into the memory. However, depending
on the application/system using the memory, the severity
of these memory errors could vary. This is summarized in
Fig. 1. In a LEON3 processor, a memory error may simply
cause a result error, i.e., an erroneous output from an algo-
rithm running on the system, or a system timeout, i.e., the
termination of an application without any result [39]. Sim-
ilarly, in a Xilinx FPGA, such errors may cause the system
to halt [33].
Error Correction Codes (ECCs) [44], are used to cater
for memory errors by adding extra bits, often called parity
or check bits, to the data bits in the memory. The parity bits
are calculated using the available data bits, and in case of an
error, the lost data is retrieved using these parity bits. Hence,
ECCs are considered to be the most effective solution for
memory errors [10], and since the introduction of Hamming
/ Published online: 26 September 2020
Journal of Electronic Testing (2020) 36:643–663
Content courtesy of Springer Nature, terms of use apply. Rights reserved.