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2.5D and 3D Packaging Failure Analysis Techniques
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An electrically open defect on a laminate may not always be found timely or successfully due to the lack of fault isolation techniques for this type of defect. This is partly due to needing high frequency techniques to isolate the location of the open. Magnetic field imaging (MFI) using a Superconducting Quantum Interference Device (SQUID) is a technique that maps, in this case, an RF signal through a trace, up until the open defect boundary. Several obstacles are introduced when using an RF signal, one of which is the shielding of the signal from the external world. Despite this obstacle, analysis of an open in an arbitrary location along a laminate under a copper plane is proven successful using this technique.
Magnetic Field Imaging (MFI) and Thermal Laser Stimulation (TLS) failure analysis (FA) techniques (e.g. OBIRCH, XIVA, ect.) both have advantages and disadvantages. The obstacles encountered from these techniques may hinder further fault isolation (FI), lengthen turn-around-time and/or detract from actionable results. MFI using a Giant Magneto Resistance (GMR) sensor is compared to TLS techniques to understand the capability of the MFI technique at finding shorting defects. A short within a capacitor bank is successfully isolated using both techniques.
While transistor gate lengths may continue to shrink for some time, the semiconductor industry faces increasing difficulties to satisfy Moore's Law. One solution to satisfying Moore's Law in the future is to stack transistors in a 3-dimensional (3D) formation. In addition, the need for expanding functionality, real-estate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques. We describe in this paper innovations in Magnetic Field Imaging for FI which have the potential to allow 3D characterization of currents for non-destructive fault isolation at every chip level in a 3D stack.
This paper proposes and validates a novel simulation ,for thermal non-destructive characterization. An electro-thermal modelling ,of the ,sample ,is adapted ,for MATLAB - SIMULINK simulation. Though the technique is capable of considering ,any heat stimuli on an arbitrary sample, the special case of lock-in thermography (LT) with periodic heating is taken up for illustration. A mild-steel sample having defects at different depths is taken as a test sample. Phase of the reflected thermal wave having great importance in LT, is obtained by measuring time delay of the reflected thermal wave. Predictions from the proposed simulation technique are shown to match well withexperimental,results. Introduction:Presently two different types of active thermography,[1] are mainly in use: Pulse and Lock-in thermography. In pulse thermography, the examined material is warmed up with a short energy pulse (light, eddy current, or ultrasonic pulse) and the thermal response recorded with time. The resultant infrared image sequence indicates material defects at different depths, but it is also affected by local ,in-homogeneities of the material surface as well ,as non-uniform heating. Lock-in thermography,uses sinusoidal intensity modulated,thermal excitation in order to derive information from the observed phase and magnitude of reflected thermal wave. The phase angle has the advantage ,that it is independent ,of local variations of illumination ,or of ,surface emissivity. The present ,work ,describes ,a MATLAB-SIMULINK [2] simulation ,for lock-in thermography. The defect depth is estimated ,by measuring ,the phase of the ,reflected thermal wave. Simulated results show good match with experimental results. The basic concept of Lock-in thermography,is the periodic heating of the sample surface by a sinusoidal intensity modulated,heat source as shown in Fig.1. This causes a heat distribution topropagate into the material. Reflection of the thermal wave is caused, if it finds a different thermal impedance medium. For the purpose of analysis, the sample is considered as semi- infinite, on to which a uniform heat source periodically deposits heat at a modulating angular frequency ω. Then, neglecting convection losses, the temperature T, as a function of depth z and time t is given by [3], T( z, t) = T0 e ,z/µ) cos(2πz/λ– ωt) (1) where T0 is amplitude of the oscillating temperature, z the depth below the surface, λ is the wavelength of thermal wave, ω the angular frequency and µ is the thermal diffusion length [3], defined as follows
Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel nondestructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper, we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.
In this paper, we demonstrate cases for actual short and open failures in FCB (Flip Chip Bonding) substrates by using novel non-destructive techniques, known as SSM (Scanning Super-conducting Quantum Interference Device Microscopy) and Terahertz TDR (Time Domain Reflectometry) which is able to pinpoint failure locations. In addition, the defect location and accuracy is verified by a NIR (Near Infra-red) imaging system which is also one of the commonly used non-destructive failure analysis tools, and good agreement was made.
Industry and market requirements keep imposing demands in terms of tighter transistor packing, die and component real estate management on the package, faster connections and expanding functionality. This has forced the semiconductor industry to look for novel packaging approaches to allow for 3D stacking of transistors (the so called “More than Moore”). This complex 3D geometry, with an abundance of opaque layers and interconnects, presents a great challenge for failure analysis (FA). Three-dimensional (3D) magnetic field imaging (MFI) has proven to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allows for submicron vertical resolution. 3D X-ray microscopy (XRM) enables 3D tomographic imaging of advanced IC packages without the need to destroy the device. This is because it employs both geometric and optical image magnifications to achieve high spatial resolution. In this paper, we propose a fully nondestructive, 3D-capable workflow for FA comprising 3D MFI and 3D XRM. We present an application of this novel workflow to 3D defect localization in a complex 2.5D device combining high bandwidth memory (HBM) devices and an application specific integrated circuit (ASIC) unit on a Si interposer with a signal pin electrical short failure.
The present paper introduced a non-destructive TDR (Time Domain Reflectomerty Analysis) methodology, an essential E-FA (Electrical Failure Analysis) technique for separating the fault isolation and identifying failure mode of advanced 2.5D IC package. The package consists of TSV and u-bump staked packaging structure. This methodology has been shown to be applicable for allocating the defect within a package. The I/V curve tracing, TDR (Time Domain Reflectometry) and the LIT (Lock-in thermography) as the useful package level and die level non-destructive techniques on fault isolation have been performed to overcome some of the difficulties. In this paper, the methodology and application of TDR and LIT on open and short/leakage failure isolations in 2.5D IC packages have been presented. The analysis procedure and results on both of fault isolations as well physical analyses to further inspection the root cause have also been discussed in detail from some case studies and the conclusion are presented at the end.
The Technical University of Dresden, Sonoscan has introduced a simulation technique that makes imaging easier and faster for stacked die and other multi-layered structures. The simulator tool uses construction information from the sample to predict the echo patterns that will result from using a pre characterized transducer in the C SAM acoustic microscope. The construction data includes thicknesses and properties of each layer. The two functions of the simulation module include it allows the engineer to create a simulated die stack that is as similar as possible to the physical die stack that he needs to image and it allows the engineer to acoustically image the simulated die stack that he has created. The C-scan imaging mode is moved using the simulated data, which results in the production of a visible acoustic image of the simulated defect.
Principle, parameters and selected applications of the optical profilometer MicroProf FRT (Fries Research & Technology GmbH) in determining surface quality are presented in this contribution.
Infrared microscopy is an important tool to the failure analyst, and its uses in failure mode identification are becoming more varied and numerous. Recent advances in equipment have enabled high magnification examination with very good resolution when analyzing plastic encapsulated devices from the backside of the die. This paper will discuss various anomalies observable with this technique as well as sample preparation techniques and a description of the IR equipment used.
Scanning SQUID microscopy (SSM) is used to visualize current paths on package and die level. In case studies it is shown, how the integration of SSM into the failure analysis flow and its combination with lock-in-IR thermography (LIT) makes it faster and allows more reliable interpretation of results
TSV interposer has emerged as a good solution to provide high wiring density interconnections, improved electrical performance due to shorter interconnection from the die to substrate, and minimized CTE mismatch between the chip and copper filled TSV interposer, resulting in high reliability micro bumps and more reliable low-k chip. Furthermore, for an interposer that does not contain any active device, already established process technology could be applied, TSV pitch could be coarser and a thicker interposer could be used. This paper presents the development of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated. The silicon interposer is 100um thick, and is mounted on a 42.5mm×42.5mm substrate through 180um pitch C4 bumps. TSV fabrication process steps and assembly process of the large logic die mounted on the TSV interposer with lead-free micro-bumps have been optimized as well as assembly of the component on the organic substrate. 3D thermal-mechanical modeling and simulation for the packaged device with TSV interposer have been performed. The samples have been subjected to thermal cycling, electro-migration and moisture sensitivity tests. Effect of TSV interposer on the stress of the die, low-k layers and fatigue life of micro bumps and C4 bumps have been investigated. Several DOEs have been performed to optimize design and material selection in order to maximize yield and reliability. Finally, Si interposer seemed to be a low-risk 3D path to have a reliable package with acceptable warpage/coplanarity, passing 1000TCB without any crack, delamination or void being detected in low-k, TSV, micro bumps and C4 bumps.
Photothermal radiometry allows for remote measurement of local harmonic heat transport where the phase angle (between remote optical energy deposition and resulting temperature modulation) is sensitive to subsurface features or defects. Phase sensitive modulation thermography (or 'lock-in thermography') combines the advantages of photothermal radiometry with the fast technique of infrared imaging thereby revealing hidden defects in a short time. In this paper the principle and various applications are described and analyzed. While this lock-in thermography is based on remote optical heating of the whole area of interest, one can heat defects selectively with modulated ultrasound which is converted into heat by the mechanical loss angle effect which is enhanced in defect regions. This 'ultrasonic lock-in thermography' provides images showing defects in a way that is similar to dark field imaging in optical microscopy.
IC packages become increasingly complex, which make failure analysis (FA) very challenging. This paper presents advanced packaging failure isolation with time-domain reflectometrv (TDR). where the efforts are put on comparative method investigation. Flip-chip ball grid array (fcBGA) and stacked-die low-profile fine-pitch BGA (stacked-die LFBGA) packages are used to demonstrate advanced packaging FA isolation with TDR and good practices in analysis are highlighted, including signature quality improvement and ground selection. The paper also uses software to mimic and observe TDR signature under various failure modes in order to study TDR behavior with different failure modes. The acquired observations are helpful in packaging FA isolation with TDR.
A reiview of ULSI failure analysis techniques for DRAMs 1. Defect localization and verification
- Guenther
Electronic Package Fault Isolation using TDR
- Smolyansky
ZEISS Xradia 510 Versa - Your 3D Submicron Imaging System with Breakthrough Flexibility
- Carl Zeiss