Conference PaperPDF Available

Design and computational modeling of fault current limiter topologies


Abstract and Figures

The increase in demand for electric power and the insertion of a distributed generation led to the rise of the short-circuit current in substations. Most of these Brazilian substations were designed decades ago, because of that their equipment may not support the new short-circuit current levels. To protect the installed equipment and avoid excessive costs replacing old devices, it is possible to install Fault Current Limiters (FCLs). This document is a report from an R&D project that evaluated FCL topologies considering real parameters in simulation from used equipment, concluding that the selected FCL topologies accomplished their technical objective. However, before implementing these topologies in the distribution system, one should consider the technical and economic feasibility of using semiconductor switching devices.
Content may be subject to copyright.
Design and computational modeling of fault current limiter topologies
Alexandre Bitencourt, Daniel H. N. Dias, Bruno W. França, Felipe Sass, Guilherme G. Sotelo
Departamento de Engenharia Elétrica - Universidade Federal Fluminense - Niterói, Brazil,,,,
Abstract: The increase in demand for electric power and the insertion of a distributed generation led to the
rise of the short-circuit current in substations. Most of these Brazilian substations were designed decades
ago, because of that their equipment may not support the new short-circuit current levels. To protect the
installed equipment and avoid excessive costs replacing old devices, it is possible to install Fault Current
Limiters (FCLs). This document is a report from an R&D project that evaluated FCL topologies
considering real parameters in simulation from used equipment, concluding that the selected FCL
topologies accomplished their technical objective. However, before implementing these topologies in the
distribution system, one should consider the technical and economic feasibility of using semiconductor
switching devices.
Keywords: Short Circuit Current Limiter, Resonant Circuit, Series Switched Inductor Circuit, Fault
In recent years, world energy consumption has grown fast and
is projected to increase by 28% until 2040 (EIA, 2017). In
Brazil, the energy consumption in 2017 was 1.2% higher than
in the previous year (EPE, 2018). As power generation does
not grow at the same rate as demand, the system is forced to
operate close to its maximum capability, leading to highly
active and reactive power flows. This operational condition
implies higher transient currents in the distribution system
lines during a short circuit. Since many Brazilian substations
were built a few decades ago, the new levels of short circuit
current have already overcome the maximum capability of
protection devices (Prigmore and Schaffer, 2017).
To mitigate this problem, a Fault Current Limiters (FCLs) can
be inserted between the transformers and the distribution lines
(Castro et al., 2018; Kozak et al., 2017; Sahebi et al., 2017).
This solution is less costly than replacing the protection
In many situations, short circuits can cause more problems to
the electrical network than just the discontinuation of the
power supply. For example, it can damage several equipments
in the substations. To avoid such damages, FCLs can be
installed in distribution system substations, where high rates
of equipment burn are detected due to the occurrence of faults
(Badakhshan and Mousavi G., 2018).
FCLs are usually placed in series with the power grid,
preventing the electric current from exceeding system limits
during the occurrence of faults. The literature presents several
FCL topologies and the choice of the best type to be installed
in a given system must be based on technical and economic
criteria (Castro et al., 2018).
This document is a report from an R&D project entitled
Hybrid Short Circuit Current Limiter for Distribution
Systems executed by Federal Fluminense University (UFF in
Portuguese) in partnership with the local distributor Light
S/A. This manuscript presents the basic design and
computational modelling of two different fault current limiter
topologies. Simulations were performed using the software
ATPDraw, which is the graphical interface of the
Electromagnetic Transients Program (EMTP).
The two FCL studied in this work were named Series
Switched Inductor (SSI) and Resonant. This section presents
its basic principles.
This type of FCL was also studied in (Abramovitz and Ma
Smedley, 2012; Ahmed et al., 2006; Chen et al., 2006; Genji
et al., 1994; Meyer et al., 2004). It is composed of an inductor
in parallel with a switch, as presented in Fig. 1. The switch is
closed in the normal operation of the system and should be
opened during the fault. At this moment, the current will be
limited by the inductor’s impedance. The component values
used in simulation were L = 0.314 mH and RJ = 0.02 Ω.
Fig. 1. Series Switched Inductor topology.
This type of FCL has a switched capacitor in series with an
inductor. The circuit resonates when the switch is opened like
presented in (Karady, 1992; Martins Lanes et al., 2007;
Sarmiento, 2007; Sugimoto et al., 1996) and illustrated in Fig.
2. During the occurrence of a short circuit, the capacitor is
removed from the system, and the inductor limits the current.
The component values used in simulation were L = 0.314 mH,
C = 22.408 mF, RC = 10 kΩ and RJ = 0.01 Ω. The RC and RJ
elements represent the capacitor discharge and Joule effect
resistances, respectively.
Fig. 2. Resonant topology.
The model of semiconductor devices in ATPDraw is a
challenge since this software has only ideal devices in its
library. This section describes how these devices were
modeled in order to present a behavior closer to real. Two
kinds of semiconductor devices were considered: Thyristors
and IGBTs.
A bi-directional switch based on thyristors can be built in
ATPDraw by connecting two of those elements in antiparallel,
as can be observed in Fig. 3. The pulses generated by the
"Command" enter the gate of the thyristors (highlighted in
blue) and determine its state of conduction, where the opening
will only occur when the current passes through zero, a typical
characteristic of this type of switch. The elements RSW and
LSW represent the resistance and inductance of a real model
switch, respectively, to simulate their effects. Points 1 and 2
correspond to the terminals where the switches will be
connected to the FCL circuit.
Fig. 3. ATPDraw Thyristor model.
Fig. 4 shows the modelling of the IGBT switch, also with RSW
and LSW presented in its equivalent circuit, connected between
terminals 1 and 2. A TACS switch was used in ATPDraw to
simulate the commutation of the IGBT accordingly to the
command signal on the gate. It is worth mentioning that this
modelling is equivalent to two IGBTs in anti-series. The
current passing through this switch represents both positive
and negative half-cycles.
Fig. 4. ATPDraw IGBT modeling.
The modeled system consists of a 10 VRMS AC voltage source
at a frequency of 60 Hz which supplies a nominal ZLOAD
impedance (composed of a 1.25 Ω resistor and an inductor of
1.83 mH), the nominal current (INOM) being 7 ARMS. To
analyze the limiter's performance during a short circuit event
the FCLs are connected to the voltage source through a small
resistance (RSOURCE = 1 μΩ) and in series with ZLOAD, shown
in Fig. 5. The short-circuit impedance ZSC in parallel with
ZLOAD is composed of a resistor of 4.9 mΩ and an inductor of
0.19 mH.
Fig. 5. ATPDraw system modeling.
The occurrences of the short-circuit events are generated by
closing the switch 1, 2 and 3 (Sw1, Sw2 and Sw3) without de
FCL at different times, where the voltage angle (θ) is equal to
0°, 45° and 90° respectively. After 100 ms of the duration of
each short circuit, these are ended by the opening of Sw1, Sw2
and Sw3 also for θ equal to 0 °, 45 ° and 90 ° respectively. The
results of these events are called the prospective current,
which is the short-circuit current of the system that would be
obtained when there is no actuation of the limiting equipment.
The purpose of this sequence of events will be to evaluate the
minimum, average and maximum values of currents and
transient voltages that may occur during the fault. Also, these
operations will be used for validation of the control system
(proposed in the following section) in correctly
identifying/distinguishing normal and short-circuit
For the elaboration of the control algorithm of the FCLs, the
following initial information must be entered by the user
(input data): the maximum value of the current module
(limax1) from which the FCL will act in [A]; the value of the
nominal system voltage (VN) in [VRMS]; the equivalent
impedance of the FCL (ZLIM), in steady state [Ω]; the initial
state of the switch (State) for normal operating condition of
the system (0 open, 1 closed); the number of samples (ST)
measured per cycle by the control system; the minimum time
(time) of sample verification, after system normalization [ms].
For the simulation performed in this report, based on the
system circuits and the modelled FCLs described in the
previous sections, the input data is shown in TABLE I for each
proposed FCL.
TABLE I. Control Parameters
The flowchart of Fig. 6 shows the logic and dynamics of the
control system, described through an algorithm in MODELS.
The control logic implemented for fault detection takes into
account the value of the current of the network and its
derivative so that the fault must be detected before the current
of the system reaches high values. The control system operates
the switch contained in the FCL circuit as a function of the
total current of the line measured at the input of the limiter (I),
as shown in the equivalent circuit of Fig. 5.
Fig. 6. Control flowchart.
In the beginning, step 01 of Fig. 6, the FCL is considered to
be under normal operating condition, and the input data were
entered into the control system. The current value measured is
acquired at each iteration performed by the control system at
step 02, based on the ST informed by the user. This ST
represents the time between one iteration and another of a
microcontroller, to reproduce its effect in the simulations. In
conditional 03, if I is higher than limax1 (minimum threshold
for the FCL to act, prior to the ZLIM insertion), step 04 is
initialized by changing the command from the switch to "state
in short circuit ", causing the FCL to act (step 05), finishing
the iteration of the algorithm (step 06).
If the measured current is less than or equal to limax1
(conditional 03), in conditional 07, it is checked if the system
was short-circuited (command in a short-circuit state) in the
previous ST. If it was not, the system then indicates that there
is no fault and sends the command to finalize the algorithm
through steps 08 and 06. On the other hand, if it was short-
circuited, then it is analyzed in conditional 09 if I is less or
equal to limax2 (the minimum limit for the FCL to continue
acting, due to the ZLIM insertion). This limit is calculated by
the algorithm, based on ZLIM, limax1 and VN. If conditional 9
is true, the counter of consecutive samples of currents less
than or equal to limax2 (Count) is initialized, in step 10, adding
another to its sum obtained in the previous step. If not, Count
is reset in step 11, because the system is still short-circuited
(I> limax2).
This counter is used to verify if the system is still short-
circuited, until a minimum number of consecutive samples
less based on the time of verification (time). If this occurs
(conditional 12), the system is no longer in the short-circuit
state (I limax2), Count is reset (step 13) and the switch
command is changed to "normal state" (step 14), causing the
FCL to stop acting (step 08), terminating the algorithm (step
06). This counter is also used to identify if the system is in a
fault condition through the numerical derivative of the current,
allowing faster detection without necessarily obtaining a very
high current.
The results were obtained through simulation of the
EMTP/ATP program, through the ATPDraw interface. The
main parameters analyzed were: short-circuit current (or
prospective); limited current; and the transient effects on the
switch (𝑑𝑖/𝑑𝑡).
Fig. 7 shows the results for the FCL SSI topology. It can be
noted that using thyristor for this type of FCL the first peak of
the limited current coincides with the prospective. This is
because the thyristor performs the opening (0 state) only when
the short-circuit current goes through zero, and so without
limiting the first peak. After its actuation, the series inductor
starts to limit the subsequent peaks. It also shows the results
of the limiter if the thyristor is replaced by an IGBT switch,
giving a reduction already at the initial peak of the first short
circuit. This is due to the difference in the performance of the
IGBT when compared to the thyristor, since there is no need
to wait for the current to go through zero to change the state
of the switch (aperture). The remaining peaks in the steady
state had very close results for both switches. Small
differences are justified by the reduction of the homogeneous
portion caused by the limitation already in the first half cycle
with the IGBT switch. It is possible to verify that the
application of IGBT switch would be more appropriate for this
topology, since it limits the short-circuit current already at the
first peak of the short-circuit current, due to its shorter
response time to act.
Fig. 7. Prospective and SSI current system with thyristor and IGBT.
Fig. 8 shows the current passing through the thyristor and
IGBT during short-circuit. For the thyristor the current would
reach 362.52 A and a di/dt of 0.052 A/μs. Using the model
TT120N16SOF as a parameter it can be seen that this event
would not damage the switch, since it can handle a current up
to 2250 A for 10 ms and 140 A/μs. As for the IGBT, current
goes up to 50 A and a di/dt of 0.006 A/μs. Using model
BSM150GB60DLC as a parameter, it can be seen that this
event also would not damage the switch since it can handle a
current up to 300 A for 1 ms and 5600 A/μs.
Fig. 8. Current through thyristor and IGBT in an FCL SSI topology.
Fig. 9 shows the result of Resonant FCL operation. In this
topology, both thyristor and IGBT limited the current in the
first peak. This effect is because that thyristor can change from
open to close as fast as the IGBT. This demonstrates that for
this FCL model, the type of applied switch does not influence
in limiting the current since the operation is based on the
closing of the switch, not on opening.
Fig. 10 shows the current passing through the thyristor and the
IGBT. It can be seen that in this FCL the limited current goes
through the switch, even for a short period. Using the
parameters of the thyristor TT120N16SOF and the IGBT
BSM150GB60DLC can be verified that both switches would
not be damaged since it can handle a current of 120 ARMS and
150 ARMS respectively. For the di/dt simulation results in a 1.1
A/μs, a value that is below the maximum rating in both
Fig. 9. Prospective and Resonant current system with thyristor and IGBT.
Fig. 10. Current through thyristor and IGBT in an FCL Resonant topology.
TABLE II summarizes the average percentual current
reduction in all three fault angles considering the first and
second peak. It is worth notice that the SSI with thyristor did
not limit the current in the first peak and for Resonant
topology both switches limited in the same level.
Percentual Current Reduction
According to the results obtained so far, it was verified that
the SSI FCL with thyristor was not able to limit the short-
circuit current in the first peak. Concerning to the SSI FCL
with IGBT, it was found that the short-circuit current was
limited already in the first peak, since this switch does not
require that the current pass through zero to open, thus
enabling its future application in the next stages of the project.
It was also observed that the Resonant FCL, regardless of the
type of switch used, presented closer values in the short-circuit
current limitation, both for the first peak and for the
subsequent peaks, being considered promising for the
execution of prototypes in the following steps. Another
advantage of this topology is the possibility of being used as
a correction of power factor, with the proper switching of the
The simulations showed that the stipulated switch models are
suitable for future prototype tests. In this way, the selection of
the FCL topology to be applied in the future should take into
account, in principle, the technical characteristics and costs
between the thyristor and IGBT.
The authors would like to thank Light Serviços de Eletricidade
S/A for the concession of the ANEEL R&D project 108
entitled Hybrid Short Circuit Current Limiter for Distribution
Abramovitz, A., Ma Smedley, K., 2012. Survey of Solid-State Fault Current
Limiters. IEEE Transactions on Power Electronics 27, 2770
Ahmed, M.M.R., Putrus, G.A., Ran, L., Penlington, R., 2006. Development
of a Prototype Solid-State Fault-Current Limiting and Interrupting
Device for Low-Voltage Distribution Networks. IEEE
Transactions on Power Delivery 21, 19972005.
Badakhshan, M., Mousavi G., S.M., 2018. Flux-lock type of superconducting
fault current limiters: A comprehensive review. Physica C:
Superconductivity and its Applications 547, 5154.
Castro, L.M., Guillen, D., Trillaud, F., 2018. On Short-Circuit Current
Calculations Including Superconducting Fault Current Limiters
(ScFCLs). IEEE Transactions on Power Delivery 33, 25132523.
Chen, B., Huang, A.Q., Baran, M., Han, C., Song, W., 2006. Operation
Characteristics of Emitter Turn-Off Thyristor (ETO) for Solid-
State Circuit Breaker and Fault Current Limiter, in: Twenty-First
Annual IEEE Applied Power Electronics Conference and
Exposition, 2006. APEC ’06. Presented at the Twenty-First
Annual IEEE Applied Power Electronics Conference and
Exposition, 2006. APEC ’06., IEEE, USA, pp. 174–178.
EIA, 2017. EIA projects 28% increase in world energy use by 2040 [WWW
Document]. U. S. Energy Information Administration. URL
(accessed 2.11.19).
EPE, 2018. Anuário Estatístico de Energia Elétrica [WWW Document].
Empresa de Pesquisa Energética. URL
168/Anuario2018vf.pdf (accessed 2.11.19).
Genji, T., Nakamura, O., Isozaki, M., Yamada, M., Morita, T., Kaneda, M.,
1994. 400 V class high-speed current limiting circuit breaker for
electric power system. IEEE Transactions on Power Delivery 9,
Karady, G.G., 1992. Principles of fault current limitation by a resonant LC
circuit. IEE Proceedings C Generation, Transmission and
Distribution 139, 1.
Kozak, J., Majka, M., Kozak, S., 2017. Experimental Results of a 15 kV, 140
A Superconducting Fault Current Limiter. IEEE Transactions on
Applied Superconductivity 27, 14.
Martins Lanes, M., Carvalho Braga, H.A., Gomes Barbosa, P., 2007. Fault
Current Limiter Based on Resonant Circuit Controlled by Power
Semiconductor Devices. IEEE Latin America Transactions 5,
Meyer, C., Kollensperger, P., De Doncker, R.W., 2004. Design of a novel low
loss fault current limiter for medium-voltage systems, in:
Nineteenth Annual IEEE Applied Power Electronics Conference
and Exposition, 2004. APEC ’04. Presented at the Nineteenth
Annual IEEE Applied Power Electronics Conference and
Exposition, 2004. APEC ’04., IEEE, Anaheim, CA, USA, pp.
Prigmore, J., Schaffer, J.S., 2017. Triggered Current LimitersTheir Arc
Flash Mitigation and Damage Limitation Capabilities. IEEE
Transactions on Power Delivery 32, 11141122.
Sahebi, A., Samet, H., Ghanbari, T., 2017. Evaluation of power transformer
inrush currents and internal faults discrimination methods in
presence of fault current limiter. Renewable and Sustainable
Energy Reviews 68, 102112.
Sarmiento, H.G., 2007. A fault current limiter based on an LC resonant
circuit: Design, scale model and prototype field tests, in: 2007
IREP Symposium - Bulk Power System Dynamics and Control -
VII. Revitalizing Operational Reliability. Presented at the 2007
iREP Symposium - Bulk Power System Dynamics and Control -
VII. Revitalizing Operational Reliability, IEEE, Charleston, SC,
USA, pp. 15.
Sugimoto, S., Kida, J., Arita, H., Fukui, C., Yamagiwa, T., 1996. Principle
and characteristics of a fault current limiter with series
compensation. IEEE Transactions on Power Delivery 11, 842
ResearchGate has not been able to resolve any citations for this publication.
Full-text available
This paper presents a comparative survey of research activities and emerging technologies of solid-state fault current limiters for power distribution systems.
Power systems must be developed and extended to supply the continuous enhancement of demands for electrical energy. This development of systems in addition to the integration of distributed generation (DG) units to the power systems results higher capacity of system. Hence, short circuit current of network is confronted with persistent increasing. Since exploration of high temperature superconducting (HTS) materials, superconducting fault current limiters (SFCLs) have attracted a lot of attention all over the world. There are different types of SFCLs. Flux-lock type of SFCL because of its characteristics in fault current limitation is an important category of SFCLs. This paper aims to present a comprehensive review of research activities and applications of Flux-lock type of SFCLs in power systems.
This paper introduces a novel modelling approach for short-circuit studies incorporating Superconducting Fault Current Limiters (ScFCL). The conventional formulation for short-circuit studies, based on symmetrical components, has been extended to include the nonlinear limiting features of the ScFCL. Indeed, this is a novel iterative modelling method which has been derived from the classical calculations of short-circuits. The operating point of the ScFCL is computed in the abc reference frame, whilst the solution of the whole network, including all its components, is achieved using symmetrical components. The ScFCL model, which includes various parallel-connected superconducting tapes, is derived for the positive, negative and zero sequences. Given that the resistance of the ScFCL is nonlinear and depends on the current flow, an iterative process is used to carry out short-circuit calculations. To validate the proposed method, a radial and a meshed distribution networks, both including a ScFCL, were studied and the solutions derived from the proposed approach and the ones obtained from the software ATP-EMTP were compared with both solutions agreeing very well with each other. The standard IEEE 14-bus test system, modified to include two ScFCL, was simulated to demonstrate the practicality of the new approach in larger networks
This paper presents the design and experimental results of a coreless superconducting fault current limiter. The limiter has a rating of 15 kV and 140 A and was tested with a 2.5 GVA short-circuit generator. During the occurrence of a short-circuit, the elements of the system are less exposed to electrodynamic and thermal overloads. The application of a SFCL leads to an increase of the capability of the power network for connecting distributed generation energy sources. Compact design of the coreless superconducting fault current limiter consists of three magnetically coupled windings cooled in liquid nitrogen. A high magnetic coupling between the superconducting windings gives a very low voltage on the limiter at a nominal current. The presented solution reduces size and weight of the device. The paper summarizes the design of the coreless limiter and presents in detail the results of tests performed at a high power test facility.
Triggered Current Limiters (TCL) have traditionally been applied to protect overdutied switchgear in medium voltage substations but increasing trends include the applications of damage limitation and Arc Flash mitigation. TCLs are effective at minimizing damage from short-circuits due to their speed, which results in their peak current limitation capabilities. Their sub-cycle response time (extinction in 1/4 to 1/2 cycle) can often reduce the I2t available in the system to less than 1% of its potential value, as compared to a 5 cycle breaker. TCLs are therefore capable of reducing the incident energy which can reduce the Arc Flash hazard category and required PPE for onsite personnel. A TCL can commonly reduce the Arc Flash hazard category from category 4 to category 2 in medium voltage. For low voltage, most applications should be reduced to category 0 or 1. This paper aims to address the applications of Arc Flash reduction and damage limitation for substation design, generating stations and highlight the benefits a TCL can provide.
Conference Paper
This paper presents relevant aspects of a project to design and install a FCL of the resonant link type. This device consists of a series reactor and capacitor, tuned to 60 Hz. The series capacitor is shunted by a saturable reactor when a fault occurs.
Conference Paper
Solid-state circuit breakers and current limiter can provide significant advantages in speed, lifetime and functionality compared to electromechanical switchgear used in distribution systems. The paper presents the operation characteristics of emerging ETO semiconductor power switch during turn-off transient. The gate commutating rate at turn-off, dI<sub>G</sub>/dt, is improved to as higher as 12kA/mus. Experimental results demonstrates that a 75 mm ETO can safety interrupt 8kA current instead of 3 kA in GTO mode. Moreover, thanks to the built-in current sensor and the self-power generation for the gate driver, ETO will largely lower the cost of whole system. This device is suitable for solid-state circuit breaker and fault current limiter with its very fast switching speed, high current interruption capability, low conduction loss and compact structure
Conference Paper
It has been proven that fault current limiters (FCL) based on power semiconductors offer many advantages compared to mechanical circuit breakers, e.g. improved voltage quality during short circuit and reduced short circuit current. However, all presented solutions have major drawbacks concerning material costs and on-state losses, which prevent a realization of these systems. In this paper a different solid-state circuit breaker concept will be presented, which uses thyristors for an active current interruption. Thyristors offer a significant reduction in both on-state losses and material costs. Consequently, these topologies could lead to a wider integration of solid-state circuit breakers in present grids due to an increased economical performance compared to solid-state concepts with turn-off semiconductors. After a brief introduction to the topic and a presentation of the fundamentals, four different topologies will be described. Whereas two of these solutions are known in literature the others are newly developed. Afterwards, simulation results will be presented and the topologies will be compared under technical and economical aspects.
This work presents a resonant fault current limiter (FCL) controlled by power semiconductor devices. Initially the operation of two ideal resonant circuit topologies as fault current limiter are discussed. The analysis of these circuits is used to derive an alternative topology to the fault current limiter based on the connection of a series and a parallel resonant circuit. Digital models are implemented in the SimPowerSystem/Matlab simulation package to investigate the performance of the proposed FCL to protect transmission and distribution electric networks against short circuit currents. Transfer functions of the linear limiter models are used to identify the effect of each element of the FCL over its stability and its transient response. The developed analysis will be used to derive modifications in the FCL topology in such a way to improve their dynamic response.