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Considerations for Through-Substrate-Via Placement in
InGaAs mHEMT THz Circuits using Thin-Film Wiring
Laurenz John#, Philipp Neininger#, Axel Tessmann#, Arnulf Leuther#, Thomas Zwick‡
#Fraunhofer Institute for Applied Solid State Physics IAF, 79108 Freiburg, Germany
‡Institute of Radio Frequency Engineering and Electronics, Karlsruhe Institute of Technology,
76131 Karlsruhe, Germany
Abstract — This paper discusses the necessity of
through-substrate vias for compact integrated circuits (ICs)
at frequencies around 300 GHz, which are implemented
using backside-process-free thin-film microstrip line (TFMSL)
matching networks. The technology used is a 35-nm InGaAs
mHEMT technology, which is processed on a GaAs substrate.
The measured S-parameters of 300-GHz common-source (CS)
and cascode power amplifier ICs with different via-placement
scenarios are presented, which indicate a topology-dependent
necessity of through-substrate-via implementation in order to
suppress the excitation of substrate resonances and inter-device
coupling. Different scenarios for via placement are investigated
experimentally and evaluated in simulation, in order to define
requirements for via-placement considerations in compact
TFMSL circuits in this InGaAs mHEMT technology.
Keywords — solid-state power amplifier, InGaAs mHEMT,
sub-mm-wave operation.
I. INT ROD UC TI ON
Due to their low losses, substrate-based microstrip and
grounded coplanar interconnects are used in most III-V
HEMT technologies, which require a backside process
including wafer thinning and through-substrate vias in
order to suppress unwanted substrate modes. In order
to permit the implementation of THz ICs without this
dependency on the height and material of the semiconductor
substrate, miniaturized thin-film microstrip lines (TFMSLs)
on thin BCB dielectrics have been implemented in HBT
and HEMT technologies at InP and GaAs substrates [1],
[2]. While through-wafer connections are not required for
the functionality of these backside-free TFMSL matching
networks, through-substrate vias are typically nonetheless
required for most MMIC to waveguide transitions and
the suppression of in-package resonances when considering
MMIC packaging.
Since the dimensions of through-substrate vias are typically
in the same order of magnitude as the substrate height,
which is usually 50 µm for usage around 300 GHz, the via
dimensions, in relative terms, increase in size in comparison
to the shrinking device and matching network dimensions at
frequencies around 300 GHz. The via placement, therefore,
needs to be considered as a part of the design process when
developing compact ICs with high device density at THz
frequencies, even though the vias might not be required for
the TFMSL matching networks to be functional. In this paper,
we evaluate the necessity of via placement for compact power
amplifier MMICs around 300 GHz, which are designed in a
35-nm InGaAs mHEMT technology.
MET3
BCB2
TFMSL
MIM Cap
NiCr MESA
Gate
MET1
MET2 SiN
BCB1
GaAs substrate
VIA
Backside Metallization
OHM
50 µm
30 µm
Fig. 1. Layer stack of Fraunhofer IAF’s 35-nm InGaAs mHEMT technology
with three metal layers and air-bridge technology.
II. TE CH NO LO GY
The technology used is Fraunhofer IAF’s
In0.52Al0.48 As/In0.8Ga0.2As mHEMT technology with
35-nm gate length. This 35-nm mHEMT technology features
an fTabove 500 GHz and an fmax exceeding 1 THz. A
detailed description of the front-end-of-line (FEOL) process
is given in [3].
The cross-section and available layers of the frontside
process which is used in this work is shown in Fig. 1. The
back-end-of-line (BEOL) process includes 50-Ω/NiCr thin
film resistors and an 80-nm-thick CVD deposited SiN layer
used for on-wafer metal–insulator–metal (MIM) capacitors.
Three metal layers (MET1-MET3) are available for the design
of compact matching networks with thin-film microstrip line
(TFMSL) interconnects on the wafer frontside. The electron
beam evaporated Au-based first and second metal layers are
defined in a lift-off process. MET3 is a 2.7-µm-thick plated
Au layer in air bridge technology.
III. DES IG N OF CO MPACT POWE R-AM PL IFI ER CE LL S
The layout and design considerations which are discussed
here are based on the layer stack shown in Fig.1. MET1 is
implemented as substrate-shielding RF and DC ground, and
the second-BCB layer BCB2 is used as dielectric substrate for
the routing of MET2 TFMSL interconnections. The TFMSL
matching network design is, therefore, independent of the
semiconductor substrate and the MET1 ground plane only
needs to be opened for frontside-via connections to the active
mHEMT devices (MESA) as well as the NiCr layer which is
routed below MET1.
The chip area which is required for the through-substrate
connection is in the range of 30 x 30 µm2and must not
overlap with the MESA or any NiCr thin-film resistors, which
30 µm
30 µm through-substrate via
8-finger CS
8-finger cascode
TFMSL
gate biasing
MET1 ground
plane
TFMSL and MIM-Cap
matching elements
bias insertion
network
NiCr resistor
Fig. 2. Layout of an 8-finger cascode stage and two CS stages.
limits the via-implementation possibilities for compact circuit
topologies with high device density. The design rule for
minimum spacing of vias to active devices is negligible small,
the via-to-via spacing, however, is limited to around 30 µm for
this technology.
Compact power amplifier MMICs have been reported
recently in [4], achieving state-of-the art output power levels
for solid-state PA MMICs around 300 GHz. Fig. 2 shows the
close-up view of a three-stage TFMSL 300-GHz PA circuit
which was implemented in the reported PA MMICs of [4],
including an 8-finger cascode stage and two common-source
(CS) stages. NiCr thin-film resistors, which are implemented
in the bias-insertion network and for stability reasons, are
depicted in black color and matching elements like TFMSL
interconnections and MIM capacitors, which are relevant for
the RF signal, are shown in blue color. The chip area which
would be required for a through-substrate connection is shown
for scale below the layout.
The depicted PA core is optimized for a compact chip size
in order to maximize the total gate width on the smallest chip
width possible. The interstage matching networks depicted in
blue are designed for a minimized chip width, which must
not exceed the width of the parallelized active devices. This
permits the parallelization of the compact PA cell at the
smallest chip area possible. Due to the limited space for the
matching networks, the gate bias is applied using the NiCr
layer, which is routed below the MET1 ground plane and is
directly connected to the gate feeders of the single devices.
Since the bias needs to be applied symmetrically, the NiCr
layer needs to be routed in the depicted tree structure, which
consumes much of the chip area between the cascaded devices.
The space for the implementation of through-substrate vias
within the active circuit area is very limited for these kind
of compact PA circuits, due to the shrinking dimensions of
the interstage matching networks at THz frequencies, as can
be seen from the layout depicted in Fig. 2. Whether vias
are required underneath a TFMSL circuit, however, strongly
depends on the devices and circuit topology used, and hence,
needs to be known during the design process.
8-finger cascode 8-finger CS
via cage
750 x 170 µm²
PA core
(a) Via placement scenario1.
(b) Via placement scenario2 (red) and scenario 3 (red + yellow).
Fig. 3. Chip photographs of the compact 4-stage PA MMICs: (a) no vias
within the active circuit area, (b) including vias of scenario 2 (vias highlighted
in red) and scenario 3 (vias highlighted in red and yellow)
In order to define the requirements for via placement
within the IC design process of compact TFMSL PA cells,
the necessity of trough-substrate connections is evaluated in
the following sections.
IV. IMPAC T OF THROUGH-SUBSTRATE-VIA PLAC EM EN T
Fig. 3 shows compact 4-stage PA cells which were reported
in [5], consisting of the 8-finger CS and cascode devices
depicted in Fig. 2. In order to experimentally investigate
the impact of inter-device coupling and resonances in the
GaAs substrate, three different via-placement scenarios are
considered: (1) there are no vias at all underneath the PA
core, as depicted in Fig. 3 (a), (2) vias are placed as close
as possible to the active devices but not within the interstage
matching networks, as depicted with the vias highlighted in red
in Fig. 3 (b), and (3) the vias highlighted in yellow in Fig. 3(b)
are added between the active devices, in addition to the vias of
scenario 2. The whole MMICs as well as the RF pads within
the MMICs are surrounded by a via cage, with the result that
RF power is only coupled into the GaAs substrate at the MET1
opening around the active devices.
The on-wafer measured S-parameters of the 4-stage PA
MMIC before backside processing (thick wafer), as well as
for the three via-placement scenarios described above, are
shown in Fig. 4. In case of the unthinned-wafer measurement,
the small-signal gain is around 20 dB over the 280–350-GHz
frequency range, showing a flat gain response. The ripple at the
upper H-band frequencies around 320 GHz is mainly caused
by the poor isolation of the on-wafer measurement setup.
On-wafer measurements of TFMSL circuits on unthinned
wafers without any vias typically show the ideal circuit
behavior with good accuracy, since any RF-power which is
coupled into the substrate, is dissipated in the ”infinitely” wide
substrate.
When comparing the on-wafer measurement results of the
three different via-placement scenarios, a strong dependency
of the gain flatness on the via placement is observed, indicating
(a) Thick wafer (b) Scenario 1
(c) Scenario 2 (d) Scenario 3
Fig. 4. Measured S-parameters of the 4-stage PA MMICs depicted in Fig. 3:
(a) measured before backside processing, (b) scenario 1, (c) scenario 2 and
(d) scenario 3.
resonant inter-device coupling through the GaAs substrate for
scenario 1 and scenario 2. While the via cage highlighted in red
in Fig. 3 (b) (scenario 2, 30-µm via-to-via spacing) suppresses
the resonances observed in Fig. 4 (b) up to 320 GHz, the
additional through-substrate vias between the active devices
(highlighted in yellow) are still required to avoid resonance at
higher frequencies.
As depicted in Fig. 4 (c), the measured S21 of scenario 2
decreases at frequencies around 320 GHz, showing resonances
above 340 GHz. The scenario-3 measurements, on the other
hand, show the same flat gain response as the unthinned
measured S-parameters, providing a flat 20-dB small-signal
gain over the 280–350-GHz frequency range.
The resonant behavior observed in Fig. 4 (b) is from our
experience strongly dependent on the implemented device
layouts and circuit topology used. H-band TFMSL amplifier
circuits using only CS devices, for example, typically do
not require through-substrate connections within the active
circuit area, as can be seen from the measured S-parameters
shown in Fig. 5. The measurement results of the 300-GHz CS
amplifier MMIC depicted in Fig. 5(a) before and after backside
processing are shown in Fig. 5(b) and Fig. 5(c), respectively.
This three-stage amplifier MMIC was designed implementing
three cascaded CS stages without any through-substrate vias
within the active circuit area (comparable to scenario 1 in
Fig. 4 (b)) and, nevertheless, no resonances can be observed
after wafer thinning.
The results discussed above show that the implementation
of vias is necessary in order to avoid substrate resonances
and inter-device coupling, at least in TFMSL circuits using
cascode devices. The resonances observed in the cascode
circuits are believed to be due to the larger MET1
ground-plane opening, which is required for common-gate
devices, in comparison to common-source transistors. The
spacing between the scenario-2 vias (red vias in Fig. 3 (b)) is
limited to 120–130 µm by the width of the 8-finger cascode
devices. The cut-off frequency of a 130-µm-wide GaAs
loaded rectangular waveguide is around 320 GHz. This cut-off
8-finger CS
4-finger CS
(a) Chip photograph
(b) Thick wafer (c) After backside processing
Fig. 5. Chip photograph (a) and measured S-parameters of a three-stage
300-GHz CS amplifier MMIC, without through-substrate vias within the active
circuit area. The S-parameters were measured on an unthinned wafer (b), as
well as after backside processing (c).
Port 1
Port 2
MESA
4-finger CS 4-finger CG
4-finger cascode layout simplified CST model
drain finger
gate
feeder source
finger
Fig. 6. Screenshot of the simplified CST simulation model of the 4-stage PA
MMIC depicted in Fig. 3.
frequency corresponds to the resonances observed for the
cascode PA MMIC without through-substrate vias between the
active devices (scenario 2) at frequencies above 330 GHz, and
stresses the necessity of the scenario-3 vias.
V. SIM UL ATIO N OF TH ROUGH-SUBSTRATE INTER-DEVICE
COU PL IN G
As shown above, the requirements for via placement
in TFMSL circuits strongly differ between cascode and
CS topologies. In order to simulate different via-placement
scenarios for the four-stage cascode MMIC depicted in Fig. 3
and reproduce the measurement results shown in Fig. 4, a
simplified model of the cascode MMIC has been implemented
in CST Microwave Studio.
To evaluate the via-placement requirements for different
device and circuit topologies, the whole MMIC, including
the matching networks as well as the GaAs substrate,
through-substrate vias and backside metalization, is simulated
using a simplified finger model for the active devices, as
depicted in Fig. 6. The MESA as well as the gate fingers are
not considered in this CST model. Only the MET1 source and
drain fingers and feeding structures are included, which are
the main source of the excited substrate modes.
For both the CS and CG devices in Fig. 6, the drain fingers
are extended and connected to the gate feeders in the case of
(a) Thick wafer (b) Scenario 1
(c) Scenario 2 (d) Scenario 3
Fig. 7. 3D-EM simulated S-parameters of the 4-stage PA MMIC CST model
depicted in Fig. 6: (a) simulated without backside process, and (b) scenario 1,
(c) scenario 2 and (d) scenario 3 via placement.
the CS devices, and to the source feeders for the CG devices.
This prevents the excitation of spurious resonances between
the transistor fingers in the simulation, so that the resonances
caused by substrate modes can be isolated.
In order to reduce the simulation time and effort, the
whole DC-bias insertion network, which is not relevant for the
propagation of the RF signal, is omitted. The two waveguide
ports at the input and output are defined at the port extension of
the RF pads, in order to prevent faux artifacts in the simulation,
caused by the RF-pad simulation.
Fig. 7 shows the simulated S-parameters of the 4-stage
MMIC CST model depicted in Fig. 6. As for the measurements
results depicted in Fig.4, the same four via-placement scenarios
(thick wafer, scenario 1–3) are investigated in simulation, in
order to evaluate the simulation approach described above.
In comparison to the measurement results depicted in
Fig. 4, the simulated S-parameters (Fig. 7) show the same
resonant behavior for the four different scenarios, at least from
a quantitative point of view. The thick-wafer simulation shows
the expected ideal behavior of the purely passive four-stage
MMIC, as the simulated S21 and S12 indicate the passband of
the matching networks, shifted in frequency due to the missing
active-device parasitics.
The scenario-1 simulation shows heavy resonances over
the full frequency band from 200–500 GHz, similar to the
measurement results. These resonances are suppressed up
to 350 GHz, implementing the scenario-2 via placement
(Fig. 7 (c)). By using the additional vias within the matching
networks, the simulated S-parameters show the ideal
thick-wafer behavior, up to frequencies above 400 GHz.
VI. CO NC LU SI ON
This paper discusses the necessity of through-substrate
vias in compact 300-GHz PA circuits, which are implemented
with backside-free TFMSL interconnections. The limited
via-implementation possibilities in chip-size-optimized PA
cores is described and different via-placement scenarios are
investigated experimentally.
The comparison of two MMICs implemented in
CS and cascode topology indicate that the necessity
of through-substrate vias is dependent on the devices
and topology used. At least for cascode devices, the
implementation of vias needs to be considered in order to
avoid substrate resonances and inter-device coupling. The
resonances observed in the cascode circuits are believed
to be caused by the finger structure of the common-gate
devices, which require a larger MET1 ground-plane opening,
in comparison to common-source transistors.
In order to avoid inter-device coupling in TFMSL circuits
in this technology, a via cage in close proximity around the
active circuit area is sufficient up to the cutoff frequency of
the loaded waveguide formed by this via cage. At frequencies
above this cutoff frequency, additional vias between the active
devices might be required. The minimum via spacing (30 µm
for the 50-µm-thick substrate) is sufficient for the 300-GHz
cascode circuits investigated in this work. At frequencies above
500 GHz, however, the substrate is typically thinned down
to sub-30-µm dimensions, which permits a smaller via-to-via
spacing.
General design rules to prevent substrate resonances
are hard to define, due to their device-layout and
topology dependency. However, to evaluate the via-placement
requirements in simulation, the usage of a simplified finger
layout for the active devices is proposed. This permits
the modeling and simulation of the full MMIC in a
3D-EM simulation software, including different via-placement
scenarios. Using this approach, the via placement can be
considered in the design process of compact THz MMICS with
high device density and limited via-placement possibilities, in
order to avoid substrate resonances after backside processing.
ACK NOW LE DG ME NT
This work was funded by the German Federal Ministry of
Defence (BMVg) and the WTD81 in the framework of the
MIKOSENS 3 program. This work has also received funding
from Horizon 2020 under grant agreement No. 814523 within
the Project ThoR.
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