No full-text available
To read the full-text of this research,
you can request a copy directly from the authors.
Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro-core architectures using ePython
... However, to date, these technologies have tended to result in significant performance overheads, required the programmer to ensure their code fits within the limited on-chip memory, provided limited choices around data location and size, and provided little, if any, portability across architectures. As evidenced by ePython [12], a Python interpreter for the Epiphany-III, dynamic programming languages can significantly reduce the programming effort required to overcome these complexities in comparison to the provided, low-level C software development kits (SDKs) [22]. ...
... vPython can either be run standalone on the device or as a Domain-Specific Language (DSL) within Python running on the host, offloading kernels for execution to the device. More information on the parallel programming, offloading and dynamic code loading capabilities of the language can be found in [22] and [21]. ...
Vipera provides a compiler and runtime framework for implementing dynamic Domain-Specific Languages on micro-core architectures. The performance and code size of the generated code is critical on these architectures. In this paper we present the results of our investigations into the efficiency of Vipera in terms of code performance and size.
Vipera provides a compiler and runtime framework for implementing dynamic Domain-Specific Languages on micro-core architectures. The performance and code size of the generated code is critical on these architectures. In this paper we present the results of our investigations into the efficiency of Vipera in terms of code performance and size.KeywordsDomain-specific languagesPythonnative code generationRISC-Vmicro-core architectures
In this paper we introduce Epiphany as a high-performance energy-efficient
manycore architecture suitable for real-time embedded systems. This scalable
architecture supports floating point operations in hardware and achieves 50
GFLOPS/W in 28 nm technology, making it suitable for high performance streaming
applications like radio base stations and radar signal processing. Through an
efficient 2D mesh Network-on-Chip and a distributed shared memory model, the
architecture is scalable to thousands of cores on a single chip. An
Epiphany-based open source computer named Parallella was launched in 2012
through Kickstarter crowd funding and has now shipped to thousands of customers
around the world.
We provide an overview of the key architectural features of recent microprocessor designs and describe the programming model and abstractions provided by OpenCL, a new parallel programming standard targeting these architectures.
Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor Hot Chips 27 Symposium (HCS)
- B De Dinechin
- Mppa Kalray
B.D de Dinechin. Kalray MPPA: Massively parallel
processor array: Revisiting DSP acceleration with
the Kalray MPPA Manycore processor Hot Chips
27 Symposium (HCS), 2015 IEEE, pages 1--27
- S Davidson
S. Davidson et al. Celerity: An Open-Source RISC-V Tiered Accelerator Fabric IEEE Micro, Volume:
38, Issue: 2, March/April 2018, Pages 30 -41
Processor Reference Guide
- Xilinx
- Microblaze
Xilinx. MicroBlaze Processor Reference Guide
https://www.xilinx.com/support/documentation/
sw_manuals/xilinx2018_2/ug984-vivadomicroblaze-ref.pdf, 2018
[epiphany-specifications] Adapteva. Epiphany Architecture Reference http:
//www.adapteva.com/docs/epiphany_arch_ref.pdf,
Rev 14, 2013
The MicroPython language
- D P George
D. P. George. The MicroPython language
http://docs.micropython.org/en/latest/pyboard/
reference/index.html, Last accessed June 2020
[micropython-website]
MicroPython community. MicroPython https://
micropython.org/, Last accessed June 2020