Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation

Intel Corp., Folsom
IEEE Transactions on Device and Materials Reliability (Impact Factor: 1.89). 04/2008; 8(1):98 - 121. DOI: 10.1109/TDMR.2008.915629
Source: IEEE Xplore


The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.

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Available from: Xiaojun Li, Nov 23, 2014
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    • "Different types of aging mechanisms have been reported for the current generation of CMOS designs, e.g. Negative/positive biased temperature instability (NBTI/PBTI), time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI) or electromigration (EM) [4]. The main causes of these effects are environmental and electrical stress. "
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