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On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup
We present the SEU laser testing of different SRAM resources of a 7nm FinFET programmable SoC. The results provide original insights on the physical organization of the device and testing challenges are discussed. Multiple-cell upsets are discussed together with Monte-Carlo simulation results. Correlation with heavy ion data is presented and discussed.
The pulsed-laser-induced Single Event Effect (SEE) technique has been developed for decades to provide an alternative method for testing the radiation durability of circuits under radiation environment. In recent years, more works have been done to introduce simulation into this research field to assist the test as an analyzing tool. In this paper, pulsed laser is used to scan over a self-designed dynamic comparator to perform pulsed-laser-induced Single Event Upset (SEU) experiments. And the simulation built based on the chip’s element are also done to find out the dynamic comparator’s SEU sensitive position. Related parameters of the experiment and information about the dynamic comparator are given for constructing the simulation. It is found that the peak value of transient current induced by pulsed laser on different sensitive positions are varied from 550 to 900 μA, while the current peak threshold for our self-designed dynamic comparator to generate SEU signal is around 817 μA. Thus, it turns out the result that sensitive position found by simulation is in good agreement with the experiment results. This work shows the feasibility for conducting simulation into SEE research field. Furthermore, Linear Energy Transfer (LET) is also calculated, which is helpful for equivalent pulsed-laser-induced and ion-induced SEE test to improve circuit’s radiation hardening design for actual application. This work performs a series of demonstrations showing that the simulation, with sufficient information, can assist the SEE experiment and provide important information for analysis of the sensitive area of DUT, and make a demonstration for the feasibility of simulation to be combined into SEE testing which could improve circuit’s radiation hardening technology.
The single-event latch-up (SEL) cross section of a 16nm bulk finFET programmable system-on-chip (SoC) is investigated by combining single photon absorption (SPA) laser testing, emission microscopy and embedded instrumentation. The contributions of different SEL-sensitive areas identified by their current increase, light emission and functional signatures are measured. The effect of temperature and IO bias is evaluated. The laser results show an excellent correlation with heavy ion data, and delimit the origin of SEL in this device by excluding the occurrence of SEL in the core-logic for this technology.
This work explores a combination of techniques using pulsed and continuous lasers to investigate and quantify the suit-ability of state-of-the-art logic technology for radiation hardened applications. We find that using a laser allows the sensitivity of underlying circuitry to be evaluated providing insights into the underlying failure mechanisms and enabling further hardening by design opportunities. Lastly, we show a non-invasive pump-probe laser voltage probe technique that allows us to evaluate logic circuitry response of various design topologies to ionizing radiation events.
A series of distance metrics to quantitatively assess the level agreement between laser- and ion-induced single-event effects is presented. Historically, this agreement has been assessed by visual inspection. While traditionally effective, this approach can lead to misleading comparisons and erroneous conclusions. To enable quantitative comparisons for response agreement, a more objective approach is required. The present work defines and demonstrates the use of five distinct distance metrics to quantitatively assess the level of SEE response agreement. These metrics correspond to each of the five categories in which most of the published SEE work can be sorted. Various applications of these metrics are shown, including the objective correlation of laser pulse energy and ion linear energy transfer. While demonstrated with laser and ion data, this approach can be applied to other surrogates for heavy ion testing, and may be used to validate results obtained from potential predictive surrogate testing techniques.
Pulsed-laser testing is used to accurately determine single-event latchup (SEL) thresholds for static random-access memories (SRAMs) with different body-tie-to-drain spacings on a mixed-signal application-specific integrated circuit (ASIC), a study that could not be completed using only broad-beam heavy-ion testing. Two distinct approaches were employed with the first approach, an empirical correlation method, exploiting the complementary nature of broad-beam heavy-ion and laser testing. Various single- and dual-port SRAMs exhibited SEL thresholds ranging from 1 MeV-cm
2
/mg to over 100 MeV-cm
2
/mg, with a dual-port device possessing the smallest body-tie-to-drain spacing being latchup immune at the highest available test conditions (>300 MeV-cm
2
/mg). These results have been used to inform a follow-on ASIC design resulting in a significant improvement in chip-level SEL sensitivity. The second approach, a calculational method, uses pulsed-laser measurements and charge-deposition modeling to predict linear energy transfer (LET) thresholds without heavy-ion data. This calculational approach agrees with the empirical approach and therefore shows promise as a predictive tool for SEL threshold estimation, but further validation is required. Overall, these approaches can be effective tools for evaluating SEL susceptibilities and mitigation strategies.
We show that the thresholds for picosecond (psec) laser
pulse-induced latchup and energetic particle-induced latchup are well
correlated over a range of bulk CMOS test structures designed to be
susceptible to latchup. The spatial length of the latchup-sensitive node
of the test structures covers a range of values that commonly occur in
bulk CMOS devices. The accuracy of this correlation implies that
laser-induced latchup can be used for hardness assurance and, under the
proper conditions, can be an accurate predictor of latchup threshold
linear energy transfer (LET) for most bulk CMOS devices
A chip-level single event latchup (SEL) estimation methodology is introduced and its accuracy demonstrated on test vehicles manufactured in a state-of-the-art technology for various process options. Novel test structures have been designed and built to make them accessible to accelerated beam testing for the purpose of calibrating the SEL rate as a function of layout design style and use condition. The calibrated model and SEL assessment strategy is capable of accurately accounting for variations in circuitry and layouts across complex products. 64 MeV mono-energetic proton and broad spectrum neutron beam testing results establish that the novel compact model accurately projects full chip SEL rates and hence it can be used to guide layout optimizations and mitigate (or eliminate) component-level SEL rates.
In this work we investigate single event latchup (SEL) in CMOS-based flip-flop structures combining heavy ions, laser pulses and simulation. In the framework of exploring the use of lasers for single event sensitivity studies, we have compared SEL cross-sections obtained with these techniques. The spatial resolution of the laser provided the sensitivity map of a flip-flop cell using various laser energies, highlighting the origin of SEL occurrence in link with topology. Latchup current distributions were then deeply analyzed over the cell and the whole ASIC to understand their sources, supported by simulation. A cross-correlation was performed with heavy ion test data to show the potential and the limits of laser techniques both for global and detailed SEL analysis.
This paper reviews techniques for physics-based device-level simulation of single-event effects (SEEs) in Si microelectronic devices and integrated circuits. Issues for device modeling of SEE are discussed in the context of providing physical insight into mechanisms contributing to SEE as well as providing predictive capabilities for calculation of SEE rates. Recent advances in device simulation methodology are detailed, including full-cell simulations and cross-section calculations from first principles. Examples of the application of physics-based SEE simulations are presented, including scaling trends in soft error sensitivity as predicted by device simulation, single-event latchup (SEL) simulations in CMOS structures, and recent simulations of single-event transient (SET) production and propagation in digital logic circuits.
Changes in technology and device scaling have generally increased
the sensitivity of VLSI devices to latchup from single interactions of
heavy particles in space. This paper discusses latchup mechanisms,
comparing latchup from heavy particles in space with electrically
induced latchup, which has been more widely studied. The effects of
technology changes and device scaling on latchup susceptibility are
discussed as well. Test methods and the interpretation of latchup
results are also included, along with predictions of the effects of
device evolution and scaling on latchup susceptibility in space
Laser System for Single Event Effects Testing and Radiation Sensitivity Mapping of ICs
- M Petasecca
IEEE Trans. Nucl. Sci. (TNS)
- A H Johnston
Correlation of picosecond laser-induced latchup and energetic particle-induced latchup in CMOS test structures
- S C Moss
- S D Lalumondiere
- J R Scarpulla
- K P Macwilliams
- W R Grain
- R Koga
IEEE Trans..on Device and Materials Reliability (TDMR)
- P Dodd