Conference Paper

A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver

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... In [16] a 55 nm SiGe BiCMOS 2-to-1 AMUX with a sampling rate of 120 GS/s is reported with a large power consumption of 2.2 W. The 2-to-1 AMUX from [15] achieved >110 GHz analog bandwidth at 180 GS/s using a 0.25 µm InP HBT process, however, requiring digital pre-processing to compensate the limited switching speed [17]- [19]. In [20] we reported a 4-to-1 interleaver with an analog bandwidth beyond Nyquist at sampling rates up to 100 GS/s using a 55 nm SiGe BiCMOS. The interleaver is based on the generation and summation of return-to-zero (RZ) signals from analog inputs. ...
... This paper is an extension of our work demonstrated in [20]. In this work we provide an explicit explanation on the architecture and its implementation. ...
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We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver's ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.
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