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Novel high functionality fault tolerant ALU
... However, the final hardware overhead decreases, but still it is high for embedded systems. In [23], to make the ALU fault-tolerant, parity gates are employed which have limited capability in fault tolerance and are suitable to detect single-bit faults. Hardware redundancy-based methods enforce extra hardware to the embedded systems that are not acceptable in many applications where the area and performance of these systems are critical. ...
This paper presents a fault-tolerant ALU (“FT-EALU”) based on time redundancy and reward/punishment-based learning approaches for real-time embedded systems that face limitations in hardware and power consumption budgets. In this method, operations are diversified to three versions in order to correct permanent faults along with the transient ones. The diversities of versions considered in FT-EALU are provided by lightweight modifications to differentiate them and clear the effect of permanent faults. Selecting lightweight modifications such as shift and swap would avoid high timing overhead in computation while providing significant differences which are necessary for fault detection. Next, the replicated versions are executed serially in time, and their corresponding results are voted based on the derived learned weights. The proposed weighted voting module generates the final output based on the results and their weights. In the proposed weighted voting module, a reward/punishment strategy is employed to provide the weight of each version of execution indicating its effectiveness in the final output. To this aim, in the method defined for each version of execution, a weight is defined according to its correction capability confronting several faulty scenarios. Thus, this weight defines the reliability of the temporal results as well as their effect on the final result. The final result is generated bit by bit based on the weight of each version of execution and its computed result. Based on the proposed learning scheme, positive or negative weights are assigned to execution versions. These weights are derived in bit level based on the capability of execution versions in mitigating permanent faults in several fault injection scenarios. Thus, our proposed method is low cost and more efficient compared to related research which are mainly based on information and hardware redundancy due to employing time redundancy and static learning approach in correcting permanent faults. Several experiments are performed to reveal the efficiency of our proposed approach based on which FT-EALU is capable of correcting about 84.93% and 69.71% of permanent injected faults on single and double bits of input data.
... However, the final hardware overhead decreases but still it is high for embedded systems. In [21], to make the ALU fault-tolerant, parity gates are employed which have limited capability in fault tolerance and are suitable to detect single-bit faults. ...
In this paper, a fault-tolerant approach to mitigate transient and permanent faults of arithmetic and logic operations of embedded processors called FT-EALU is proposed. In this method, each operation is replicated in time and the derived final results are voted to generate the final output. To consider the effect of permanent faults, replicating identical operations in time is not sufficient, and diversifying the operands is required. To this aim in FT-EALU, we consider three distinct versions of input data and apply the target operation to them serially in time. To avoid high time overhead, we employ simple operators such as shift and swap to make an appropriate diversion in input data. Our proposed fault tolerance approach passes the replicated and diverse results to a novel weighted voter that is designed based on the reward/punishment strategy. For each version of execution, based on the proposed weighting approach a corresponding weight according to its correction capability confronting several faulty scenarios is defined. This weight defines the reliability of the result of each version of execution and determines its effect on the final result. The final result is generated bit by bit based on the weight of each execution and its computed result. These weights are determined statically through a design-time learning scheme according to applying several types of faults on various data bits. Based on the capability of execution versions on mitigating the permanent faults, positive or negative scores are assigned to them. These scores are integrated for several cases and normalized to derive the appropriate weight of each execution at bit level. Several experiments are performed to show the efficiency of our proposed approach and based on them, FT-EALU is capable of correcting about 84.93% and 69.71% of permanent injected faults on single and double bits of input data.
... It concludes that SET technology has adopted for low-power digital applications. Thakral and Dipali [11] presented a fault-tolerant ALU based on high functionality. The proposed design compared with existing designs resulted in improvement of functionality by 25% and a quantum cost reduction of 40%. ...
The concept of IOT (Internet of Things) prevalent in the era, an enormous increase in the implementation of low resource devices with limited resources to implement various arithmetic primitives for cryptographic applications. Most of the National Institute of Standards and Technology NIST approved conventional security algorithms like the IDEA, RSA etc. involve simple operations like addition, multiplication and complex operations like addition-modulo, multiplication-modulo etc. such algorithms may not be routed to the low resource devices. Even though the NIST approved algorithms may be fitted into the low resource devices their erformance may be a concern. An extensive research has been carried out on designing the cryptographic arithmetic structures over the years, the arithmetic modules have been implemented using different design styles, logic, algorithms and aspects. In this paper the reversible logic and Vedic mathematics have been combined to implement efficient cryptographic arithmetic primitives. A considerable amount of improvement in the performance parameters like Area, power dissipation and delay have been analyzed by the implementation and synthesis
The birth to IC technology by Moore became driving force behind civilization and it spent almost 45 years successfully without any scruple in mind. It affected life of a mankind and brought pivotal moment in civilization. Now technology is hitting atomic levels and soon limits will be touched. Therefore time has come to rethink for an alternative solution that may slow down exponential rate demonstrated by Moore. Reversible computing is emerging as a superior technology and soon will be future of all smart computing applications. Although renowned physicists and computer scientists have investigated remarkable results in reversible logic based arithmetic logic unit (ALU) designing still research in the field of reversible ALU with add on fault tolerance is under progress and there is scope of further optimization. This paper aims in investigation of improved fault tolerant ALU architecture using parity preserving fault tolerant reversible adder (FTRA), double Feynman and conservative Fredkin gates. Performance evaluation of proposed architecture is done in respect of functionality, garbage lines, ancillary lines, quantum cost and number of gates. The quantum cost of all gates is verified using RCViewer+ tool. The proposed architecture is coded in Verilog HDL, Synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2.
Quantum-dot cellular automata (QCA) as a technology in the nanoscale is used for designing the future circuits. It has high density, speed, and low power dissipation. Besides, arithmetic and logic unit (ALU) is one of the main bases to define the system performance. Its plan depends on combinational circuits that decrease complexity and it has reasonable simulation times. Cell misalignment, cell displacement, cell omission (missing cell), and the extra (additional) cell are considered as the weaknesses of these circuits. Designing Fault tolerance of ALU in QCA is very important but there is no survey about the details. A three-level fault-tolerant ALU based on QCA is discussed in this paper, which performs “AND”, “OR”, “XOR” and “Full adder”. Also, the used rotated majority gate in the proposed ALU is fault tolerance. This structure tolerances a single stuck-at 0 and 1 and related faults are covered using test patterns {11100, 11101, 11010, 11001}. Furthermore, the presented ALU, under omission errors of cells in layers 2 and 3 is tolerated using the test patterns. The presented method has high fault tolerance compared to the similar methods according to the simulation results using QCAdesigner. It also has 0.78 µm² of circuit area and the outputs are delivered after three clock cycles. Also, it has lower area consumption and delay compared to other schemes.
There is a tremendous growth in fabrication from small scale integration (SSI) to giant scaleintegration (GSI). It however raises a question of sustainability of Moore's law due to almost intolerablelevels of power consumption. Researchers have invented a lot of methods to reduce power consumptionand recent technologies are switching to reversible logic. Reversible logic has various applications in fieldsof computer graphics, optical information processing, quantum computing, DNA computing, ultra lowpower CMOS design and communication. ALU is considered to be the basic building block of a CPU in thecomputing environment and portability in computing system highly demands reversible logic based ALU. Modern processors usually have a word length of 32 or 64 bits. Divide and conquer approach principlecascades n number of 1 bit ALU to implement n bit ALU. Several researchers have proposed 1-bit ALUdesign using various reversible logic gates. This paper aims at categorizing various ways ofimplementation in VHDL using Xilinx ISE design suit 14.2 tool and comparative analysis of existing 1 bitALU designs in terms of optimization metrics like power consumption, number of gates, number ofconstant inputs, number of garbage outputs and quantum cost.ALU realized using carry save adder blockis found to be most optimum design in terms of gate count and quantum cost.
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the
simulation result obtained ensures the correctness of the design.
Reversible logic is becoming an important research area which aims mainly to reduce power dissipation during computing. In this paper we introduce a new parity preserving reversible gate PPPG (a 5x5 gate). This gate is universal in the sense it can synthesize any arbitrary Boolean function. It is also a parity preserving gate in which the parity of input matches the parity of the output. This parity preserving gate allows any single fault to be detected at the circuit’s primary outputs. By using one PPPG a fault tolerant reversible full adder circuit can be realized. The proposed fault tolerant full adder (PFTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. The PFTFA gate is also used to implement high speed adders which are efficient basic building blocks of logic circuits. It has also been demonstrated that the proposed high speed adders are efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
Arithmetic Logic Unit (ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4 (Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated. © 2014, Science Press, Institute of Electronics, CAS and Springer-Verlag Berlin Heidelberg.
Now days most of the circuits which are going to be designed to perform any specific or safety critical operations are mainly based upon the digital domain, where microprocessors and microcontrollers plays an important role to design these digital circuits. ALU is the heart of these processors. By optimizing this co-processor a highly efficient digital processor can be obtained. So this paper is totally devoted to design speed, energy and power efficient Arithmetic Logic Unit. Speed of ALU is greatly depends upon the speed of multiplication unit. There are so many multiplication techniques have been devised at algorithmic and structural level. After a thorough study and deep analysis we have found that Vedic Urdhva Triyambakam multiplication algorithm is the best algorithm as it generates partial products in the parallel manner. In this paper we have proposed a new tree multiplication structure based architecture to design this Vedic multiplier. To generate partially generated products divide and conquer approach has been used. For the addition of partially generated products a new addition tree structure has been proposed. It provides better speed in comparison Array, Booth, Wallace, Modified Booth Wallace, Karatsuba and Vedic Karatsuba Multiplier as well as it is faster than Vedic multiplier which has been proposed by L. Shriraman [2], and Devika Jaina [3]. To make ALU energy and power efficient, a new reversible logic gate has been proposed which is similar to Fredkin Gate [18]. After integrating these modules we have obtained the speed, energy and power efficient ALU. The proposed Arithmetic Logic Unit is coded in Verilog HDL, synthesized and simulated using Xilinx ISE 9.2i software.
Parity-preserving reversible circuits are gaining
importance for the development of fault-tolerant systems in
nanotechnology. On the other hand, Quantum-dot Cellular Automata
(QCA), a potential alternative to CMOS, promises efficient digital
design at nanoscale. This work targets design of reversible ALU
(arithmetic logic unit) in QCA (Quantum-dot Cellular Automata)
framework. The design is based on the fault tolerant reversible
adders (FTRA) introduced in this paper. The proposed fault
tolerant adder is a parity-preserving gate, and QCA implementation
of FTRA achieved 47.38% fault-free output in the presence of all
possible single missing/additional cell defects. The proposed
designs are verified and evaluated over the existing ALU designs
and found to be more efficient in terms of design complexity and
quantum cost.
Reversible Logic is gaining significant consideration as the potential logic
design style for implementation in modern nanotechnology and quantum computing
with minimal impact on physical entropy .Fault Tolerant reversible logic is one
class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the
design of fault tolerant reversible logic gate structures and arithmetic units,
however, there are not many efforts directed towards the design of fault
tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing
unit in any computing device and it has to be made fault tolerant. In this
paper we aim to design one such fault tolerant reversible ALU that is
constructed using parity preserving reversible logic gates. The designed ALU
can generate up to seven Arithmetic operations and four logical operations.
This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic–logical operations on two n-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible ALU for a programmable computing device is possible and that the V-shape design is a very versatile approach to the design of quantum networks.
Since the Arithmetic Logic Unit (ALU) is one of the essential components of the Central Processing Unit (CPU), its well performance is the most important factor in obtaining the high reliability. The reversible logic has also found emerging attention in nanotechnology, optical computing, quantum computing and low power CMOS design. In this paper we are going to propose and analyze a basic model of fault tolerant reversible ALU and show that the realization of an efficient fault tolerant reversible ALU is possible with both minimum constant inputs and garbage outputs. The proposed fault tolerant reversible ALU is a versatile approach to the implementation of quantum computing with having both a remarkable low power consumption and nano scaling. [Parisa Safari, Majid Haghparast, Asgar Azari. A Design of Fault Tolerant Reversible Arithmetic Logic Unit. Life Sci J 2012;9(3):
Quantum-dot cellular automata (QCA) is a promising emerging nanotechnology that has been attracting considerable attention due to its small feature size, ultra-low power consuming, and high clock frequency. Therefore, there have been many efforts to design computational units based on this technology. Despite these advantages of the QCA-based nanotechnologies, their implementation is susceptible to a high error rate. On the other hand, using the reversible computing leads to zero bit erasures and no energy dissipation. As the reversible computation does not lose information, the fault detection happens with a high probability. In this paper, first we propose a fault-tolerant control unit using reversible gates which improves on the previous design. The proposed design is then synthesized to the QCA technology and is simulated by the QCADesigner tool. Evaluation results indicate the performance of the proposed approach.
Quantum dot-cellular automata (QCA) based reversible logic is the foundations of emerging nanotechnological computing systems. It promises extremely low power consumption with high density and operating frequency. This work focuses on design of an efficient reversible ALU (Arithmetic Logic Unit) and its realization in QCA. We have considered existing 3 × 3 RUG (Reversible Universal Gate) as the basic building block, and also present a HDLQ model of RUG having 52.2% fault tolerance capability. Further, the reversible ALU has synthesized with reversible logic unit (RLU) and reversible arithmetic unit (RAU). We also present QCA implementation of RLU and RAU with minimum complexity and cell count. The proposed ALU requires only 68 MVs (Majority Voter), which is 35% more area efficient than the existing work. It is simulated using QCADesigner to verify the proposed designs which can be also embedded with ultra low power complex digital system.
It is argued that computing machines inevitably involve devices which perform logical functions that do not have a single-valued inverse. This logical irreversibility is associated with physical irreversibility and requires a minimal heat generation, per machine cycle, typically of the order of kT for each irreversible function. This dissipation serves the purpose of standardizing signals and making them independent of their exact logical history. Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
A function is reversible if each input vector produces a unique output vector. Reversible logic is of growing importance to many future computer technologies. In this paper, the design of a reversible Arithmetic Logic Unit (ALU) is presented making use of multiplexer unit as well as control signals. ALU is one of the most important components of CPU that can be part of a programmable reversible computing device such as a quantum computer. In multiplexer based ALU the operations are performed depending on the selection line. The control unit based ALU is developed with 9n elementary reversible gates for four basic arithmetic logical operations on two n-bit operands. The series of operations are performed on the same line depending on control signals, instead of selecting the desired result by a multiplexer. The later design is found to be advantageous over the former in terms of number of garbage outputs and constant inputs produced.
In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.
Power dissipation is an important design criterion during the VLSI process flow. Reversible logic is one of the promising fields having a wide range of applications starting from low power VLSI design, fault tolerant circuits, quantum computing to fields such as bio informatics. An ALU may be regarded as the processor's numerical calculator and logical operation evaluator. In this paper a fault tolerant reversible ALU design is proposed. Parity preserving logic gates are the main component in this design. A parity preserving gate is the one in which the parity of the input and the output vectors is the same. The proposed ALU can produce up to 16 logical and 16 arithmetic operations.
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