Conference PaperPDF Available

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

Authors:
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power
and High Performance Applications
J. Zhang, J. Frougier, A. Greene, X. Miao, L. Yu, R. Vega, P. Montanini, C. Durfee, A. Gaul, S. Pancharatnam, C. Adams, H. Wu,
H. Zhou, T. Shen, R. Xie, M. Sankarapandian, J. Wang, K. Watanabe, R. Bao, X. Liu, C. Park, H. Shobha, P. Joseph, D. Kong,
A. Arceo De La Pena, J. Li, R. Conti, D. Dechene, N. Loubet, R. Chao, T. Yamashita, R. Robison,
V. Basker, K. Zhao, D. Guo, B. Haran, R. Divakaruni, H. Bu
IBM, 257 Fuller Rd, Albany, NY 12203
Email: zhangji@us.ibm.com
Abstract
In this paper, full bottom dielectric isolation (BDI) is first
demonstrated on horizontally stacked Nanosheet device
structures with Lmetal 12 nm. The comparison of full BDI
scheme vs punch through stopper (PTS) scheme has been
systematically studied. By comparing off-state leakage current,
short channel behavior and effective capacitance (Ceff) for both
schemes, we show that BDI could potentially provide: 1) good
immunity of sub-channel leakage due to process variation (from
parasitic “fat-Fin” which is unique in Nanosheet structure);
2) power-performance co-optimization.
Introduction
Horizontally Stacked Gate-All-Around Nanosheet
architecture has been identified as a promising candidate to
replace FinFET for 5 nm node and beyond with further
aggressive scaling requirement because of its superior
electrostatics [1-3]. We have demonstrated the short channel
behavior for extremely scaled Nanosheet device, studied
transport behavior with varying sheet width (Wsheet) [4],
validated feasibility of multi-threshold-voltage (multi-Vt)
scheme on Nanosheet structure [3].
In addition to the elements mentioned above, sub-fin leakage
is an important topic that has been studied for FinFET
technology. SOI substrates and PTS implant on bulk substrate
[5-8] have been identified as solutions to address this issue.
However, it still remains unclear on how to effectively transfer
those elements to Nanosheet device structures. There are
multiple approaches being discussed on Nanosheet structure
including PTS implant and S/D isolation (partial dielectric
isolation) schemes [2].
In this paper, we propose a full BDI scheme which
introduces a dielectric layer underneath both the S/D and gate
regions. The benefits of implementing a full BDI scheme is to
reduce sub-channel leakage, immunity to process variation and
power-performance improvement. Details will be discussed in
following sections.
Motivation
In a stacked nanosheet structure, Lmetal and Weff have been
considered as key tuning parameters to enable high performance
application [2][4]. Lmetal scaling is known to be critical as a
Ceff reduction knob to improve AC performance. Fig. 1 shows
simulated total Ceff of FO3 inverters with Lmetal 12 nm and
Lmetal 15 nm devices respectively. As can be seen, reducing
Lmetal from 15 nm to 12 nm (with the same junction design),
can lead to a 4% to 6% Ceff reduction depending on Wsheet.
The power-performance can be improved accordingly by
reducing Ceff. Nanosheet device structure shows its unique
advantage to meet the electrostatic requirements for Lmetal 12
nm device. Fig. 2 and Fig. 3 show sub-threshold slope (SS) and
drain-induced-barrier-lowering (DIBL) vs Lmetal from
simulation for both Nanosheet and FinFET devices. These
figures highlight that Lmetal 12 nm Nanosheet structures have
comparable SS and DIBL values as Lmetal 15 nm on FinFET
structures.
Fig. 4 shows the dependence of Wsheet vs performance with
various back end of line (BEOL) load assumptions (considering
different resistance and capacitance). When considering a
smaller BEOL load, wide Wsheet devices show a performance
benefit of 5% to 7%. When considering a larger BEOL load,
wide sheet devices show a more significant (~14%)
performance benefit over narrow sheet device. The ratio of
front-end capacitance (C
FE
) vs back-end capacitance (C
BE
)
explains performance sensitivity over various Wsheet.
Device Design and Fabrication
When migrating from a Fin to Nanosheet structure, the sub-
channel for Nanosheet is much wider in comparison with
FinFET (Wsheet vs Dfin). The sub-channel (“fat-Fin”) in
Nanosheet has weaker gate control in the center region due to a
wide Wsheet. Therefore, the center of “fat-Fin” region is more
vulnerable to source to drain leakage through the substrate.
While comparing BDI and PTS schemes, the two elements
which have been mainly evaluated include process variation and
power-performance of FO3 inverter ring oscillators. This
section focuses on the process variations’ impact on devices.
Fig. 5(a) shows an ideal Nanosheet device structure with PTS
scheme where the S/D recess is at a target depth. Fig. 5 (b) and
(c) show Nanosheet device structures with 5 nm and 10 nm
deeper S/D recess respectively, considering process non-
uniformity and variation. The S/D recess depth (T
1
) and PTS
depth (T
2
) are labeled accordingly. Fig. 6 shows a schematic of
a cross-Fin direction view with Fin reveal depth T
3
as labeled.
When T
1
increased, the sub-channel will introduce more off-
state leakage current as shown in Fig. 7. I-V characteristics of
all three S/D recess conditions show that both Ioff and SS are
degraded when T
1
increases. In addition to higher leakage
current, this sub-channel will contribute to an increased Ceff
which will degrade device performance. Due to a large Vt and
poor carrier mobility, the sub-channel will not contribute to any
on-state current. The alternative solution to suppress the
parasitic leakage is to increase T
3
which will cause a Ceff and
performance penalty.
On the contrary, the BDI integration scheme will not be
susceptible to these issues. In addition to the situation described
above, BDI has a stronger immunity to other non-ideal process
variations, such as PTS dopant loss, S/D dopant diffusion into
sub-channel at extremely scaled Lmetal design and shallow-
trench-isolation (STI) liner charge effect. As a result, BDI is
expected to have better extendibility for more aggressive scaling
as compared to PTS. As previous published, Fig. 8 shows the
structure of a nanosheet device structure with a partial bottom
dielectric isolation layer under the S/D region only. Although
the partial bottom dielectric isolation layer can turn off the sub-
channel leakage, the parasitic inversion gate capacitance (Cginv)
still exists under the gate region. Fig. 9 shows the ideal
Nanosheet device structure with a full BDI layer.
Nanosheet devices are fabricated on bulk Si substrate. To
implement the BDI module, a high Ge% SiGe layer is grown as
the first layer on the substrate followed by low Ge% SiGe/Si
stacked layers. To improve selectivity between bottom SiGe and
regular sacrificial SiGe layers, the Ge% of regular sacrificial
SiGe layers in the alternating stack needs to be lowered. As a
result of lowering Ge% in sacrificial SiGe layers, the inner
spacer indentation and channel release processes will be more
challenging due to reduced selectivity between the sacrificial
SiGe and Si channel layers. This requires a novel process with
“ultra-high selectivity” to prevent Si sheet erosion during
channel release and S/D EPI etch-out through the inner spacer
region due to non-ideal inner spacer profile.
Fig. 10 shows a cross-gate view TEM image after low Ge%
sacrificial SiGe layer indentation and inner spacer formation.
The robustness of the BDI layer under the S/D regions is the key
because this region will be exposed to multiple etch processes.
Fig. 11 shows a cross-gate view TEM image post S/D CMOS
EPI growth.
Results and Discussions
1) BDI vs PTS -- Sub-Channel Leakage Control
Fig.12 shows I-V characteristics for both NFET and PFET of
44CPP Lmetal 12 nm devices with the BDI scheme at Vds = 0.7
V. Both NFET and PFET show good electro-static behavior
with SSsat of ~74mV/dec and low Ioff. Fig. 13 shows I-V
characteristics of NFET with BDI vs PTS splits of 44CPP
Lmetal 12 nm device at Vds = 0.7 V. I-V characteristics show
that SSsat is improved from PTS split #1 to PTS split #2 due to
increased PTS dopant level of split #2. However, the BDI split
demonstrates a further improved SSsat compared with PTS split
#2. Meanwhile the Ioff is improved together with SSsat. The
same behavior is observed from PFET I-V characteristics as
well, as shown in Fig. 14. The Ioff and SSsat improvement with
PTS dopant level suggests that the source of this effect is from a
bottom parasitic channel which degrades electro-static (“fat-
Fin” effect). The BDI scheme shows further improvement in
measured hardware data which indicates that the dopant amount
in PTS split #2 is not enough to fully turn off the parasitic “fat-
Fin”.
Fig. 15 shows Isoff extracted from the Lmetal 12 nm NFET
devices on BDI and PTS splits. BDI demonstrates the smallest
Isoff as compared to other PTS splits. PTS split #2 shows much
lower Isoff than PTS split #1 which confirms that the leakage
current is coming from bottom parasitic channel. Fig. 16 shows
SSsat extracted from Lmetal 12 nm NFET devices on BDI and
PTS splits. Fig. 17 shows SSsat extracted from Lmetal 30 nm
NFET devices on the same splits. BDI shows a better SSsat
control compared to PTS splits when reducing the Lmetal from
30 nm to 12 nm which suggests BDI has better immunity to
short-channel-effect from the sub-channel. Fig. 18 shows DIBL
extracted from Lmetal 12 nm devices on BDI and PTS splits.
The BDI split shows a smaller DIBL as compared to PTS splits
which is consistent with SSsat data.
Overall, the BDI data shows better immunity for process
variations such as S/D recess depth, fin reveal depth, PTS
doping profile, etc. In other words, BDI could provide more
robust device performance with less variability, good leakage
and short-channel control. The lower leakage level (as
demonstrated with the BDI scheme) is preferred for extending
the design viability for low power circuits.
2) BDI vs PTS -- Power-Performance Evaluation
Wide sheet devices could provide higher frequency and better
performance for HPC applications. To understand how BDI can
impact power-performance for HPC applications, devices with
BDI and PTS structure at different Vdd have been studied and
compared. Fig. 19 shows a normalized active power vs
normalized performance correlation chart for wide sheet devices
with BDI and PTS schemes (evaluation via FO3 inverter ring
oscillators). It shows that a wide sheet with BDI has ~4% higher
performance at the same power consumption. While at the same
performance, the power consumption for the BDI scheme is
~18% lower than the PTS scheme. Fig. 20 shows a schematic of
capacitance components that will be affected by introducing
BDI structure: Cov (overlap capacitance) and Cginv. Fig. 21
shows the performance evaluation on wide sheet devices for
BDI and PTS schemes. Nanosheet structures with wide sheets
show a 4.4% Ceff reduction using BDI which translates to a
4.6% performance boost. Out of this 4.4% Ceff reduction, 2%
comes from Cov reduction and the remaining part comes from
Cginv reduction. The critical advantage of BDI is minimizing
parasitic capacitance components by eliminating the need for
the T
1
, T
2
or T
3
control which is required for PTS integration as
shown in Fig. 5 and 6.
Full BDI integration on Nanosheet transistors can provide
improved power-performance optimization which is applicable
for both low-power and high-performance applications.
Conclusion
Full BDI scheme on stacked Nanosheet transistors can
potentially provide significant benefit over the conventional PTS
integration scheme. BDI shows better immunity to process
variation in terms of sub-channel leakage control and can
provide performance enhancement depending on the circuit
design requirement of Wsheet, BEOL load and Vdd. BDI
integration on stacked nanosheet transistors also provides
additional opportunities for power-performance co-optimization
for both low-power and high-performance applications.
Acknowledgments
This work was performed by the IBM research and
development teams at various IBM Research and Development
Facilities.
References
[1]
S.D. Kim et al., S3S, p.1-3, 2015
. [2] N. Loubet et al., Symp. VLSI
Tech., T230, 2017. [3] J. Zhang et al.,
IEDM
, p22-1, 2017. [4] C.
Yeung et al., IEDM, p28-6, 2018. [5] J. Kedzierski, et al., IEDM, p247-
250, 2002. [6] C.H. Lin, et al., IEDM, p3-8, 2014. [7] C. Auth et al.,
IEDM, p29-1, 2017. [8] D. Ha et al., Symp. VLSI Tech, T68-T69, 2017.
Gate metal
Fig. 6 Schematic of cross-Fin view with
Fin reveal depth T
3
labeled.
Fig. 7 Is-Vg characteristics for
diff erent S/D recess depth, corresponding
to Fig.5 structures.
Fig. 8 Nanosheet device structure
with partial bottom dielectric isolation
laye r under S/D regiononly.
Gate Metal
Fig. 4 Wsheet vs performance chart with multiple
BEOL load assumptions.
Fig. 5 5(a) shows an ideal Nanosheet device str ucture ; (b) and (c) show deeper S/D
recess device structure associated with PTS scheme.
(a) (b) (c)
Fig. 1 Normalized Ce f f for Lmetal 12 nm and
Lmet al 15 nm devices with different Wsheet.
(c)
Fig . 2 Sub-threshold slope (SS) vs Lmetal
on both Nano sheet and FinFET devices.
Fig. 3 DIBL vs Lmetal on bot h
Nanosheet and FinFET devices.
Fig. 10 TEM image of cross-gate view pos t
inner spacer formation.
Fig. 9 Ideal Nanosheet device structure wit h
full BDI layer under gate and S/D regions.
Fig . 11 TEM image of cross-gate view
post S/D EPI formation.
BDI layer
Fig. 21 Pe rfo rmance evaluati on on wide shee t device s @Vdd 0.9 V. For wide s heet , Ceff wi th BDI structure is 4.4% smaller than PTS
structure which translates to a 4.6% performance improvement.
Vdd=0.9V Scheme Normalized Ceff Normalized Reff Normalized Fmax
wide sheet
PTS 1.0X 1.0X 1.0X
BDI 0.956X 1.0X 1.046X
Fig. 13 I-V characteristics of NFET with
BDI vs PTS splits on 44CPP Lmetal 12 nm
devic es at Vds = 0.7 V.
Fig. 12 I- V characteristics for both NFET and
PFET with 44CPP Lmet al 12 nm device with BDI
scheme at Vds = 0.7 V.
Fig. 14 I-V charact eristics of PFET
with BDI vs PTS splits on 44CPP
Lmetal 12 nm devices at Vds =0.7V.
Fig. 15 Iso ff extracted from Lmetal 1 2
nm devic es on BDI and P TS spl its.
Fig. 16 SSsat extracted from Lmeta l 12
nm devices on BDI and PTS splits.
Fig. 17 SSsat extracted from Lmetal
30 nm device s o n BDI and PTS splits.
Fig. 18 DIBL extracted from Lmetal 12 nm
devic es o n BDI and PTS splits.
Fig. 19 Power vs performance correlation
chart of wide sheet devices for both w/ and
w/ o BDI layer.
Fig. 20 Schematic of Nanosheet device
st ruct ure wit h key capac itanc e co mpone nts
that will be affec ted by introduc ing BDI
layer.
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Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total ionizing dose (TID) tolerance due to the ultra-scaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes.
  • S D Kim
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