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# SiQAD: A Design and Simulation Tool for Atomic Silicon Quantum Dot Circuits

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## Abstract

This paper introduces SiQAD, a computer-aided design tool enabling the rapid design and simulation of computational assemblies of atomic silicon quantum dots. SiQAD consists of several simulation tools: a ground-state electron configuration finder, a non-equilibrium electron dynamics simulator, and an electric potential landscape solver for the exploration of field-driven modulation with electrodes. Simulations have been compared against past experimental results to inform the electron population estimation and dynamic behavior. Fundamental logic building blocks and circuits suitable for this platform have been designed and simulated, and a clocked wire has been demonstrated. This work paves the way and provides the first set of open design tools for the exploration of the emerging design space of atomic silicon quantum dot circuits.
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Transactions on Nanotechnology
1
SiQAD: A Design and Simulation Tool for
Atomic Silicon Quantum Dot Circuits
Samuel S. H. Ng, Jacob Retallick, Hsi Nien Chiu, Robert Lupoiu, Lucian Livadaru, Taleana Huff,
Mohammad Rashidi, Wyatt Vine, Thomas Dienel, Robert A. Wolkow, Member, IEEE,
Abstract—This paper introduces SiQAD, a computer-aided
design tool enabling the rapid design and simulation of com-
putational assemblies of atomic silicon quantum dots. SiQAD
consists of several simulation tools: a ground state electron con-
ﬁguration ﬁnder, a non-equilibrium electron dynamics simulator,
and an electric potential landscape solver for the exploration of
ﬁeld-driven modulation with electrodes. Simulations have been
compared against past experimental results to inform the electron
population estimation and dynamic behavior. Fundamental logic
building blocks and circuits suitable for this platform have
been designed and simulated, and a clocked wire has been
demonstrated. This work paves the way and provides the ﬁrst set
of open design tools for the exploration of the emerging design
space of atomic silicon quantum dot circuits.
Index Terms—Computer aided design, quantum dots, silicon
I. INT ROD UC TI ON
RECENT advancements in scanning probe microscopy
have enabled the precise creation and erasure of silicon
dangling bonds (DBs) on the hydrogen passivated silicon
100 2×1 (H-Si(100)-2×1) surface [1]–[3]. These DBs have
tightly conﬁned orbital wavefunctions with energies that fall
within the silicon substrate’s bulk band gap [4], [5], and
can be considered as zero dimensional quantum dots with at
most two occupying electrons [6]–[8]. The total number of
electrons within ensembles of DBs, as well as their spatial
arrangement, are governed by electrostatic interactions [9],
[10]. The preferred charge conﬁgurations of speciﬁc patterns
of DBs enable the creation of logic gates [9], [11], introducing
a fundamentally new computational platform technology and
unique design space at the atomic scale. Exploration of this
prospective technology requires new tools for simulating the
behavior of DB patterns.
This work was supported by a research grant from the Natural Sciences and
Engineering Research Council of Canada (NSERC), with funding reference
number STPGP 478838-15. A version of this manuscript was uploaded to a
preprint server (arXiv:1808.04916).
S. S. H. Ng, J. Retallick, H. N. Chiu, R. Lupoiu, and K. Walus were with
the Department of Electrical and Computer Engineering, University of British
Columbia, Vancouver, BC, Canada V6T 1Z4 (e-mail: samueln@ece.ubc.ca;
jret@ece.ubc.ca; nathanchiu@ece.ubc.ca; robert.lupoiu@alumni.ubc.ca;
L. Livadaru, T. Huff, and R. A. Wolkow were with Quantum Silicon Inc.,
taleana@ualberta.ca; rwolkow@ualberta.ca).
T. Huff, M. Rashidi, W. Vine, T. Dienel, and R. A. Wolkow were
with the Department of Physics, University of Alberta, Edmonton, AB,
Canada T6G 2J1 (e-mail: taleana@ualberta.ca; rashidi.moe@gmail.com;
wyattvine@gmail.com; td342@cornell.edu; rwolkow@ualberta.ca).
2020 IEEE.
Here we present SiQAD (Silicon Quantum Atomic
Designer), a computer-aided design (CAD) tool that provides
an environment for the design and simulation of DB circuits,
thus enabling rapid prototyping of DB designs before they are
physically fabricated. This paper is organized as follows: Sec-
tion II provides the technical background on DB quantum dot
circuits; Section III introduces SiQAD’s capability for circuit
design and simulation, and describes the software architecture
of the CAD tool; Section IV provides detailed explanations
and simulation results of the three included simulation tools;
Section V presents new DB logic gates and circuits created
using SiQAD, as well as design rules gathered in the process.
II. BACKGROU ND
Silicon DBs are fabricated by desorption of individual
hydrogen atoms from a hydrogen-terminated silicon surface
using the probe of a scanning tunneling microscope (STM);
H-Si bonds are broken by applying a voltage pulse at a
hydrogen site, leaving behind a valence orbital as depicted in
Fig. 1a [3], [12]–[14]. Hydrogen sites are located atop silicon
atoms with locations discretely deﬁned by the lattice structure,
allowing the creation of DBs at atomically precise locations
as illustrated in Fig. 1b. There are three charge states that
a DB can host: the unoccupied positive state (DB+), singly
occupied neutral state (DB0), and doubly occupied negative
state (DB-). Since the charge transition levels between these
states exist within the band gap as illustrated in Fig. 1c, they
are considered electrically isolated from the bulk [8], [15]
and allow for discrete electron population by manipulating
the relative energetic positions between the bulk Fermi energy
and the charge transition levels [6], [7], [16], [17]. A number
of factors contribute to band bending, including inter-DB
Coulombic interactions [6], [9], external ﬁelds such as the
contact potential of the tip of a nearby STM or atomic force
microscope (AFM) [16], [18], and charged subsurface dopants
[19]. This band bending shifts the charge transition levels with
respect to the bulk Fermi level. The charge occupation of a DB
changes when its charge transition level crosses the Fermi level
due to changes in the energy landscape; local charge defects or
dopants can affect the energies at which this happens through
proximity based gating effects [19]. The charge states can be
measured via AFM with examples included in Fig. 1d.
The potential of DBs as building blocks for computational
logic circuits has previously been demonstrated [9], where a
binary OR gate that consists of 3 radially placed DB pairs as
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Transactions on Nanotechnology
2
HDB
Si dimers
Si
(a) Surface of H-Si(100)-2×1 with DB.
2.34 7.68
3.84
(b) DB layout.
CB
VB
Si
Vacuum
Charge transition levels
w/o BB
Upward BB
Downward BB
DB(0/-)
DB(+/0)
Energy
Depth
(c) Schematic of DB energy level diagram.
DB0
DB-
Hz
-24.7
-54.0
(d) DB AFM.
Fig. 1. (a) Desorbed hydrogen leaves a valence orbital, shown in blue, in
H-Si(100)-2×1 with mid-gap charge states. (b) Schematic top view of the
surface where the highlighted area represents the region in (a). The blue
dot represents a DB and the smaller gray dots represent hydrogen locations
where DBs can be created. (c) Schematic of the DB energy level diagram
illustrating the mid-gap DB positive to neutral (+/0) and neutral to negative
(0/-) charge transition levels. The red, blue, and black states represent upward
band bending, downward band bending, and no band bending respectively.
VB and CB represent the valence and conduction bands, and ESi
Fdenotes
the bulk Fermi energy. (d) AFM images of a DB in DB0 (singly occupied)
and DB- (doubly occupied) states. Contrast can be used to directly imply the
charge state of DB ensembles.
shown in Fig. 2a was proposed. Each DB pair conveys a single
bit of information via the location of one negative charge
within. The input logic states are actuated by the presence
of perturbers, which are peripheral DBs energetically favored
to remain in the DB- state regardless of the state of other DBs
in the circuit. The output is given by the charge state of a
particular DB. The charge states were measured via AFM in
[9] exhibiting a tendency to relax to the system’s ground state,
as shown in Fig. 2b. A simulated version of the OR gate is
also shown in Fig. 2c, with details to follow in Section IV-A.
Additionally, non-equilibrium charge dynamics were inves-
tigated in [10] via AFM experiments on a six DB structure
shown in Fig. 3a, which was designed to be energetically
frustrated such that an electron has the tendency to localize
on either of the innermost DBs. A “hopping” of the electron
among those sites was observed as the structure was scanned,
with each localization persisting over multiple line scans as
shown in Fig. 3b. In [10], the persistence is attributed to a
stabilization of the charge states by lattice relaxation [20],
[21], presenting an additional energetic barrier between the
degenerate states that prevents elastic tunneling. The tip inﬂu-
ence and thermal ﬂuctuations likely contribute to overcoming
this barrier. We were able to simulate the ground state and the
hopping phenomena of the frustrated ground states as shown
in Fig. 3c-3d, which will be discussed in Section IV-B.
The potential to construct nanometer-scale logic circuits
from atomic DBs makes this technology a promising candidate
for advancing the work in circuit miniaturization and power
pm 440 pm 420 pm 460 pm 470
0 0 0 0
(a) STM images of the OR gate [9].
Hz
-49.9 -30.0 Hz
-34.9 -23.5 Hz
-40.9 -26.5 Hz
-40.9 -26.3
(b) AFM images of the OR gate [9].
1 nm
0 0
Out 0 1 1 1
1 0 0 1 1 1
DB pairs
Lattice sites
DB0
DB-
Degenerate DB-
(c) SimAnneal simulations of the OR gate.
Fig. 2. A DB OR gate made of 3 pairs of binary dots studied in [9] toggled
through all necessary truth states with perturbers. The logical output of the
gate is determined by the charge state of the DB labeled ‘Out’: 0 and 1
for DB0 and DB- respectively. (a) STM images of the OR gate revealing
all DB locations in white. The presence of perturbers at the top of the
device (indicated by blue arrows) change the input state. The output perturber
(indicated by orange arrows) acts to prevent a charge from occupying the
lower output dot unless sufﬁciently repelled by charges in the upper half of
the device. (b) Constant height AFM images revealing charge localization in
the structure as the darker DB sites. (c) Simulated annealing results of the OR
gate with the output perturber moved one lattice site lower for more reliable
simulated performance. These charge conﬁgurations can be reached by a range
of simulation parameters (ref. Fig. 5). Unﬁlled and fully-ﬁlled DBs are singly
and doubly occupied respectively, while partially-ﬁlled DBs indicate shared
charges in degenerate states. The radially placed DB pairs are also labeled.
(a) and (b) adapted by permission from Springer Nature Customer Service
Centre GmbH: Springer Nature, Nature Electronics, [9] (Huff et al., Binary
atomic silicon logic), c
2018.
reduction. Further, the use of silicon substrate opens up possi-
bilities to integrate DB circuits with existing infrastructures for
silicon complementary metal-oxide-semiconductors (CMOS)
devices. This is a new design space with largely unknown
design rules and constraints; many more logic gates and circuit
components still await investigation. The SiQAD project aims
to reduce the barrier for the research community to explore
this platform technology, as well as to develop design rules
that will allow for effective design of complex circuits and
systems at the atomic scale.
of DB circuits through an intuitive graphical user interface
(GUI) and a modular simulation back-end. The GUI is written
in C++ with the Qt cross-platform application framework
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Transactions on Nanotechnology
3
(a) AFM scan. (c) Average occupation.
(b) AFM line scans.
0
9
18
0 1 2
Time (min)
Charges
(d) Simulated line scans.
Fig. 3. Six DB symmetric structure studied in [10]. (a) AFM image of the
structure, with two DB pairs in the middle and one perturber on each side.
(b) Sequence of AFM line scans performed at 4.5 K, repeatedly scanning
back and forth along the center-line of the structure with a high tip-sample
separation to reduce the tip inﬂuence. One charge is shared approximately
evenly between the two inner DBs (ref. Fig. S3 in [10]) and is observed
to maintain its occupancy over multiple line scans. (c) Simulated average
occupation with SimAnneal with parameters µ=0.08 eV,r= 5.6,
and λTF = 5 nm (ref. Section IV-A). (d) Dynamic simulation of the structure
using HoppingDynamics with the Mott Variable Range hopping model with
800 line scans over 18 minutes showing similar results to (b). Reprinted Fig. 3a
and 3b with permission from M. Rashidi et al., Phys. Rev. Lett., 121, 166801,
2018 [10]. Copyright 2018 by the American Physical Society.
[22] and provides tools for DB layout design, simulation
management, as well as multi-layer electrode placement.
The SiQAD GUI communicates with simulation engines
through a custom simulation application programming inter-
face (API). Simulation engines may utilize this API via a pro-
vided class structure which supports engines developed in C++
or Python. The general procedure of a simulation upon user
invocation is as follows: 1) SiQAD exports a ﬁle containing the
simulation parameters as well as the DB and electrode designs;
2) the desired simulator is invoked with user-conﬁgurable
command line arguments; and 3), result ﬁles generated by
result types displayed in the GUI. Currently supported result
visualization types include DB charge state conﬁgurations
and electrostatic landscape results. Simulation engines may
also instruct SiQAD to perform design actions such as the
creation, movement, and removal of design objects through an
instructions API. Three simulation tools are included with the
initial release of SiQAD, with their features and functionalities
detailed in the proceeding section. Additional engines can be
implemented and incorporated through the provided APIs.
The source code and binaries of SiQAD and associated
simulation tools are publicly available at [23]. The open-source
tools allow the research community to modify or contribute
additional functionalities, supporting the future growth of
SiQAD as a DB circuit design platform.
IV. SIM UL ATION ENGINES
Three simulation engines are ofﬁcially included in the
initial release of SiQAD, each with different purposes and
capabilities as detailed below:
SimAnneal: simulated annealing algorithm for ﬁnding
metastable low energy charge conﬁgurations.
HoppingDynamics: non-equilibrium electron hopping dy-
namics simulation intended for capturing the experimentally
observed hopping behavior in [10].
PoisSolver: electrostatics solver which solves the general-
ized Poisson’s equation to ﬁnd the electric potential land-
scape arising from clocking electrodes in the system.
In SiQAD’s simulation setup interface, multiple simulations
can be chained in sequence and inter-engine data ﬂow can be
facilitated. This is particularly useful for directing electrostatic
landscape results generated by PoisSolver to SimAnneal or
HoppingDynamics.
A. SimAnneal: Low Energy Charge Conﬁguration Simulator
1) Working Principle: SimAnneal is a heuristic algorithm
for simulated annealing which attempts to ﬁnd the ground
state metastable charge conﬁguration for given DB layouts.
The energy of a charge conﬁguration, ~n, is given by
E(~n) = X
i
Vext
ini+X
i<j
Vij ninj(1)
where Vext
iis the total contribution of external potential
sources at the ith DB with the exception of inﬂuences from
other DBs, niis the charge state at each DB with possible
values ni∈ {−1,0,+1} 7→ {DB-, DB0, DB+}, and Vij
is the strength of the Coulombic interaction between DB
sites. SimAnneal consists of two major components, surface
hopping and population control, that contribute to ﬁnding low
energy stable charge conﬁgurations.
During the surface hopping phase, attempts are made to
hop electrons or holes to neutral sites, with these hops being
accepted via an acceptance function. Past analyses of exper-
imental results have ﬁtted the inter-DB charge interaction to
the screened Coulomb potential [9], [18], of the form
Vij =q0
4π
1
rij
erij TF (2)
with rij the distance between the DBs, λTF the Thomas-
Fermi screening length, and =0rwhere 0is the vacuum
permittivity and ris the effective dielectric constant at the
surface. The dielectric constant affects the strength of electric
ﬁelds, while the screening damps charge interactions at a
distance exponentially.
The population control phase assesses the effect of band
bending on the charge transition levels (Fig. 1c) and updates
the electron population in an attempt to produce electron
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Surface
Reservoir
Fig. 4. Population update probabilities for electrons to hop on or off DB
sites as a function of the local potential. Vfintroduces an artiﬁcial barrier
between the surface and the reservoir, which increases over the course of the
annealing schedule to restrict hopping and ﬁx the surface charge population.
A similar mechanism is used for holes.
conﬁgurations that satisfy the following conditions: DB sites
should be doubly occupied when the DB(0/-) charge transition
level is below the Fermi level, vacant when the DB(+/0)
charge transition level is above the Fermi level, and singly
occupied otherwise. Band bending effects that contribute to
all DBs approximately equally, such as those due to spatially
broad inhomogeneity, are captured in a chemical potential,
µ=EsESi
F, where Esis the DB(0/-) charge transition
level of a single isolated DB and ESi
Fis the bulk Fermi
level; µ+is the DB(+/0) charge transition level equivalent,
which can be expressed as µ+=µ− E where Eis the
potential between the charge transition levels taken to be
0.59 eV [19]. Other environmental band bending effects, such
as those due to modulation ﬁelds and stray charged dopants,
can be encapsulated in Vext. Local band bending effects for
individual DB sites are expressed as
Vi=Vext
iX
j
Vij nj.(3)
For each SimAnneal iteration, electrons hop between DB sites
and an imaginary reservoir that can provide or contain any
number of electrons according to a heuristic method inspired
by Fermi-Dirac distribution:
P0ni(Vi) = Pt(ni(Vi+µni))
Pni0(Vi) = Pt(ni(Vi+µni))
where Pt(Voffset) = 1
1 + e(Voffset+Vf)/(kBT).
(4)
Here, Pfromto indicate the transition probabilities between
charge states for the ith DB; Vfis the freeze out potential,
an artiﬁcial energy barrier between the reservoir and DB
sites which is increased in each iteration to gradually inhibit
hopping and tends to ﬁx the number of electrons at the surface;
and kBTis an artiﬁcial thermal energy that decreases over the
course of the simulation according to the annealing schedule.
Direct transitions between DB- and DB+ are not allowed in
this model. Fig. 4 illustrates the role of Vfin the population
update mechanism.
At the end of the annealing schedule, the metastability of
generated results are evaluated based on the following criteria:
population stability, where the charge state of each DB must be
consistent with the energetic position of the charge transition
levels relative to the Fermi energy after accounting for band
TABLE I
LOC AL POTE NT IAL S OF BIASED DB PAIR
Setup Method Viat each site
V1V2V3
1
Measured (eV)0.0– –
SimAnneal (eV)0.0– –
Diff (%) 0.0– –
1 2
Measured (eV)0.0 0.280
SimAnneal (eV)0.0 0.287
Diff (%) 0.0 2.50
1 2 3
Measured (eV)0.055 0.407 0.054
SimAnneal (eV)0.056 0.378 0.056
Diff (%) 1.82 7.13 3.70
bending; and conﬁguration stability, where no lower energy
charge conﬁgurations exist that can be reached within a single
hop event. The lowest energy metastable state observed is
presented to the user in SiQAD.
Note that this heuristic method assumes that the charge
system is given sufﬁcient time to relax to the ground state;
actual tunneling rates between the DB and external charge
sources are not considered. This makes SimAnneal well-
suited for fast prototyping of DB layout designs, but not for
real-time dynamic ﬁeld-modulated simulations. The inclusion
of physical intuition in this ground state ﬁnder through the
hopping and population update mechanisms allows SimAnneal
to be much more efﬁcient in exploring the problem space than
random bit-ﬂip methods found in generic simulated annealing
algorithms. For comparison, alternative ground state ﬁnders
using quadratic unconstrained binary optimization (QUBO)
have also been explored via a two-state approximation (DB0
and DB-). SimAnneal consistently outperformed all tested
QUBO solvers under the two-state approximation, includ-
ing Isakov et al.’s SimAn [24], D-Wave’s Qbsolv [25], and
D-Wave’s quantum processing unit [26].
With DB conﬁgurations designed with extreme compact-
ness, or fabricated on surfaces with very strong Coulombic
interactions (very low r), ground states given by Eq. (1) may
contain DB- and DB+ sites at close proximity and still sat-
isfy metastability conditions. However, no such experimental
results have been observed. The lack of such observation may
be due to the inﬂuence exerted by the AFM or STM scanning
probes, or it may be an indication of missing metastability
conditions in the ground state model. This will be further
considered in future work, but does not affect the intended
purposes of the simulation tool at the DB densities and
2) Simulation Results: Physical parameters across sepa-
rately prepared silicon surfaces may differ for many reasons
[9], with examples including differences in doping level, slight
deviations from preparation procedure, and bulk or surface
defects. In the context of the ground state simulation model,
variations in r,λTF,µ, and µ+may result in different
ground state charge conﬁgurations for the same DB layout.
We ﬁrst verify SimAnneal’s simulation results using a
set of experimental results with known physical parameters.
On a surface found to have r= 5.6,λTF = 5 nm, and
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Transactions on Nanotechnology
5
101
100
100101
( )
(a) All inputs combined. (b) ORMod 00 input.
(c) ORMod 01/10 input. (d) ORMod 11 input.
Fig. 5. Operational ranges of ORMod acquired by sweeping the physical
parameter set {r, λTF, µ}. Shaded regions indicate parameter sets which
lead to the operational ground state shown at the top left of each sweep plot.
Changes in µleads to a horizontal translation of the plots in log-log scale.
µ=0.231 eV, the DB(0/-) transition levels in a biased
DB pair depicted in Table I were measured and analyzed
in [9] (ref. Fig. 2 in [9] for experimental results). The raw
experimental data was reanalyzed in this work using the same
analysis procedures in [9] and compared against simulation
results as shown in Table I. SimAnneal produced identical
ground state charge conﬁgurations, and returned Vivalues
(ref. Eq. (3)) that matched closely with those extracted from
experimental data. Note that the Vivalues given for the
unbiased DB pair is for the left-occupied degenerate state.
Proceeding to the OR gate structure from [9], the experi-
ments were conducted on a separate surface from that of the
biased DB pair from Table I. As mentioned at the beginning of
this Simulation Results section, there exists physical property
variations despite the employment of similar surface prepa-
ration procedures. Without making physical alterations to the
OR gate, SimAnneal is only able to reproduce the experi-
mental charge conﬁgurations across all input combinations at
λTF >9 nm and r>10 with very narrow ranges of rvalues
for each λTF value. While we do not completely preclude
the possibility of the silicon surface coincidentally satisfying
those parameters, the experimental charge conﬁguration could
also have been inﬂuenced by the AFM tip or nearby non-
uniformities such as the bright spots near the output perturber
seen in the AFM images.
Although we have reservations over the operational parame-
ter range for an exact replication of the OR gate, we were able
to achieve a much larger operational range simply by moving
the output perturber down by one lattice site (2.34 ˚
A). The
much increased operational range is a highly desirable feature,
(a) All inputs combined. (b) OR gates 00 input.
(c) OR gates 01/10 input. (d) OR gates 11 input.
Fig. 6. Operational ranges at µ=0.23 eV for ORMod and an alternative
design, ORCmpt, which is shown at the top left of each sweep plot. The
compactness of the alternative design allows ORCmpt to function in surfaces
with weaker Coulombic interactions due to higher dielectric constant.
ensuring gate robustness across a broader range of surface
physical parameters. To avoid confusion, we denote the OR
gate from [9] as “ORHuff” and the modiﬁed version “ORMod”.
Fig. 2c shows the simulated ground state charge conﬁgurations
for ORMod which are achievable with a wide range of rand
λTF values at various µvalues. This is shown in Fig. 5,
which sweeps across the parameter set {r, λTF, µ}to ﬁnd
the operational range for each input combination as well as the
operational intersection. The sweep bounds of {r, λTF}were
chosen to encompass their values ﬁtted in past experimental
results [9], [18], [27]. For each input combination, we observe
a contiguous operational window of rand λTF combinations
at each µvalue where the desired charge conﬁguration is
achieved; changes in µtranslates the boundaries of these
operational windows along the raxis in log-log scale.
Different implementations of the same gate may operate
over different ranges of parameters. Physical parameter sweeps
of an alternative OR gate design (ORCmpt) with more compact
DB placements than ORHuff have been performed as shown
in Fig. 6. At the same µvalue, the operational range of
ORCmpt encompasses rvalues that are greater than those of
ORMod. This shift in operational range, which corresponds to
a reduction in Coulombic repulsion, agrees with the intuition
that a more compact version of ORMod would prefer to operate
under conditions with weaker inter-DB interaction.
Distinctive features can be observed at the boundaries of
the operational ranges in Fig. 5-6. To aid the interpretation
of these boundaries, maps delimiting changes in ground state
charge counts for each input combination of ORMod have been
included in Fig. 7. The ground state charge population tends
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Transactions on Nanotechnology
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100101
r
100
101
TF
1
3
5
7
O4
Charge count
(a) ORMod 00 ground states map.
100101
r
100
101
TF
2
4
6
8
O5
O5
N5
(b) ORMod 01/10 ground states map.
100101
r
100
101
TF
7
9
5
3
O6
O5
N5
(c) ORMod 11 ground states map.
Fig. 7. Map of ground state charge populations of ORMod acquired by sweeping the physical parameter set {r, λTF }at µ=0.23 eV. Notable charge
conﬁgurations are depicted next to each map with their frame colors matching the corresponding region on the map. They are labeled Onor Nnindicating
whether the state is Operational or Non-operational and its charge count n. Regions colored white have no metastable ground state unless coexistence of DB-
and DB+ states at close proximity are allowed; they are denoted “null regions” in this work. (a) ORMod 00 sweep map showing an operational region, O4,
that stretches through the entire λTF sweep range; the bordering regions to the left and right have a respective decrease and increase in charge count. We
denote these borders “population boundaries”. A null region also borders the lower left side of O4, indicating signiﬁcant upward band bending exerted by
charged DBs. (b) ORMod 01/10 sweep map showing an operating region similarly sandwiched by population boundaries, with an extra horizontal boundary
at the bottom not seen in ORMod 00. The neighboring state below the horizontal boundary, N5, has the same charge count but a different ground state charge
conﬁguration due to changes in DB interaction distance. These horizontal borders are denoted as “interaction boundaries”. (c) ORMod 11 sweep map showing
an interaction boundary between O5and N5, as well as a slight protrusion of N5into O6. This indicates that different ground states sharing the same charge
count (in this case, O5and N5) do not necessarily share the same population boundaries.
to decrease in the direction of rising λTF and falling r, and
tends to increase in the opposite direction. This agrees with the
intuition that stronger inter-DB repulsion makes it unfavorable
for neutral DBs to acquire new charges of the same sign.
Two types of boundaries have been identiﬁed from these
maps: population and interaction boundaries. The former is
dependent on both rand µand involve a change in preferred
population, causing the operational ground state to cease
functioning; the latter is only dependent on λTF and involve a
change in preferred ground state with the same population.
A detailed analytical model of these boundaries is under
development and will be presented in a future publication.
Lastly, Fig. 3c shows the simulated ground states of the
six DB symmetric structure from [10]. The perturbers on both
sides are always doubly occupied, exerting an inward bias on
the electron occupying the sites in-between. One electron is
equally shared between the two inner DBs. This is in agree-
ment with the experimental results of [10] shown in Fig. 3b,
where the middle electron hops between the inner DBs. Like
ORMod, the same ground state can be achieved for the six DB
symmetric structure under a variety of {r, λTF, µ}param-
eters. Although Vivalues for the structure were presented in
[10] (ref. Fig. 2d in [10]), the estimated physical parameters
used in that model predated the ﬁtting done in [9] and [18],
making it not a deﬁnitive benchmark to reproduce.
B. HoppingDynamics: Non-equilibrium Dynamics Simulator
1) Working Principle: HoppingDynamics is a non-
equilibrium electron dynamics simulator that treats electron
transitions via hopping rates. The simulator is generalized to
allow for various forms of hopping rates depending on the
choice of hopping model. Two hopping models have been
implemented: Mott Variable Range hopping [28] and Marcus
hopping [29]. HoppingDynamics only accounts for the DB0
and DB- states since they are presented as the predominant
charge states used for logic in [9] with the electrostatic energy
of charge conﬁgurations taken to be of the form in Eq. (1).
The rate of hopping for a charge from the ith (DB-) to jth
(DB0) site is taken to be of the form
νij e2αrij η(∆Gij )(5)
with rij the distance between the DBs, Gij the change in
Gibbs free energy associated with the hop, αthe spatial decay
of the hopping rate, and ηsome function of Gij . The change
in Gibbs free-energy is taken to be
Gij = ∆Eij +ρi(6)
with Eij the change in Eq. (1) associated with the change in
to capture the DB- level deepening due to lattice relaxation and
taken to be equal for all occupied sites.
If the average hopping rate, ν0, between two degenerate
DBs at some distance r0is known, the hopping rates can be
expressed as
Mott :νij =ν0e2α(rij r0)eEij /kBT(7a)
Marcus :νij =ν0e2α(rij r0)eEij [∆Eij +2(ρi+λ0)]/4λ0kBT
(7b)
where λ0is a reorganization energy. At each instant in time,
a hop from ito joccurs with probability Pij=νij dt.
A spatial decay of α= 1 nm1is assumed, with ν0and
r0taken from the combined AFM line scans in [10]. Future
experimentation will be used to reﬁne the calibration of the
hopping rates.
Charge population can be modeled by including additional
channels for hopping to and from the surface DBs. As an
example, charges hop from DB- sites to the bulk and from the
bulk to DB0 sites with respective rates νi,B and νB,i:
νi,B =νBf((Vi+µ) + ρi)(8a)
νB,i =νBf(Vi+µ).(8b)
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Transactions on Nanotechnology
7
Here, νBis an attempt frequency and fsome function of the
energy difference between the Fermi level and the DB(0/-)
charge transition level. In these results, fis taken to be a
logistic function and νBis sufﬁciently high such that surface-
bulk transitions are, from the computational standpoint, imme-
diately allowed once the DB(0/-) charge transition level passes
the Fermi level.
2) Simulation Results: The six DB symmetric structure
from [10] has been simulated with HoppingDynamics. DB
charge states were measured according to a tip scanning at
8.9 nm/sfor 800 line scans to match the experimental time
scales with the tip inﬂuence ignored. An example result is
shown in Fig. 3. Like the experimental results from [10],
the structure always contains 3 doubly charged sites with
similar hopping between the two innermost DBs. The OR gate
results were also simulated. Identical results to SimAnneal
were achieved for OR 00,01, and 10. For OR 11, hopping
between the two half ﬁlled DBs in Fig. 2c was observed.
C. PoisSolver: Electrostatics Solver
1) Working Principle: Electron occupation on the surface
may be controlled by shifting the DB charge transition levels
with respect to the bulk Fermi level. The control of Fermi
levels demonstrated so far involves either doping [19], which
cannot be changed after fabrication, or AFM tip-induced band
bending [10], [16], which is not scalable to device-wide
modulation. We envision that future DB circuits will rely on
buried or suspended electrodes with controllable potentials to
adjust the surface electron population, allowing ﬁne control
of information ﬂow. Sections of the circuit may be switched
‘off’ by applying a voltage that induces upward band bending
on the surface until the desired DBs reach the DB0 state; they
may be switched ‘on’ by inducing downward band bending
until the necessary electron population has been reached. In
order to better understand the behavior of the DBs under the
inﬂuence of electrodes, the effect of the electrodes on the
surface potential must be quantiﬁed.
PoisSolver, a ﬁnite element method solver supporting mul-
tiple electrostatics approximation models was implemented in
Python using the FEniCS software package [30]–[36]. The
simulation engine is able to account for user-deﬁned design
parameters, most notably the geometrical dimensions of the
sample and the electrodes, and the resolution of the ﬁnite
element mesh. The physical scope of the simulation includes
the silicon substrate and its doping proﬁle, the silicon surface,
the dielectric above the surface, and the electrodes. The ground
plane is set to be at the bottom of the simulated bulk.
Upon invocation of the simulator, a mesh is deﬁned and
generated according to the provided geometry and resolution,
and the generalized Poisson’s equation is solved over the mesh.
Variable mesh generation is implemented such that the mesh
contains ﬁner detail at material boundaries (e.g. electrodes and
silicon surface), while other areas will have a coarser mesh.
The mesh deﬁnition is then passed to Gmsh to generate the
appropriately formatted mesh for simulation [37]. When the
computations are complete, the potentials are written to a ﬁle
which can be used in other engines. A two-dimensional slice
Vacuum
Silicon
Direction of
information ow
50
0.0
50
100
150
0 50 100 150 200 250 300 0.64
0.48
0.32
0.16
0.00
0.16
0.32
0.48
0.64
Position (nm)
Depth (nm)
Potential (V)
Fig. 8. A schematic of a buried electrode system with dimensions that
are realistic for fabrication. The mesh was generated by PoisSolver, which
was then used to solve for the potential landscape of the cross-section.
The electrodes (white squares) have time-varying potentials in the form of
sinusoidal functions, each with a π
2phase offset from the nearest one to the
left. These phases are indicated by the phasor inside each electrode.
of the potential is extracted and displayed to the user in a color
map. For time-varying clocking ﬁelds, the electrode potentials
are adjusted with each simulation time step, and PoisSolver is
used to recompute the potential landscape.
PoisSolver offers four physical models, the nonlinear
Poisson-Boltzmann Equation (NPBE) [38], the linearized
Poisson-Boltzmann Equation (LPBE) [38], the Poisson’s equa-
tion (PE), and Laplace’s Equation (LE). Using the NPBE, the
movement and effect of mobile charges in the bulk can be
accounted for in electric potential simulations. Linearizing the
NPBE about 0V reference results in the LPBE, also commonly
known as the Debye-H¨
uckel approximation used for electric
ﬁeld screening analysis. At the silicon surface, the potentials
for a clocked system solved by the linear models each have
a different offset from those solved by the NPBE. The offset
in the LPBE is due to the model being valid only for small
values of electric potential, speciﬁcally when sinh( qu
kT )qu
kT .
The difference between the PE model and the NPBE can be
attributed to the PE neglecting charge migration. For the LE
model, the constant offset is attributed to both the internal
potential of the semiconductor due to graded doping and
charge migration. The LE model can be made to match the
PE model closely by considering the built-in potential of
a non-uniformly n-doped semiconductor, something that the
PE model inherently accounts for. The inclusion of multiple
models allows for rough estimates using the linear models,
saving the costly non-linear model for veriﬁcation. Detailed
description of the PoisSolver electrostatic models and a variety
of simulation results will be presented in a future publication.
2) Simulation Results: In order to investigate ﬁeld-
modulated information ﬂow via buried electrodes, an inverting
DB wire structure was implemented in SiQAD with sinu-
soidally clocked 4-phase electrodes located 100 nm below
the surface, as illustrated in Fig. 8. The mesh generated by
PoisSolver and the electric potential of the cross-section are
shown. An electrode clocking amplitude of 0.6 V was chosen
to produce a ±100 meV potential waveform at the surface in
order to provide the appropriate amount of band bending to
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Transactions on Nanotechnology
8
... toward output
Logic
state
Input
perturber
Field
amplitude
Fig. 9. Signal packet propagation using population clocking in an inverting
wire. Shaded ﬁeld amplitudes indicates the ±100 meV surface potential
waveform achieved using 4-phase electrodes 100nm below the surface. The
arrows indicate the logical state of the inverting wire. Note that by changing
the input perturber during the depopulated phase between t1and t2, two
signal packets of opposite polarization are generated. To visualize the dots
and packets for illustration, it was necessary to use electrodes 4 nm wide and
separated by 8 nm. Similar results are achieved for larger electrodes. Lattice
sites are omitted from the time-stepped visualization, but the spacing between
DB pairs remain consistent with that shown in the magniﬁed panel.
control DB states between DB0 and DB-. Simulation results
of the clocked inverting wire using HoppingDynamics can be
seen in Fig. 9.
V. DB LOG IC GATE DESI GN S
Using SiQAD, DB implementations of common logic gates
including the AND, XOR, NAND, and XNOR gates have been
designed and simulated as shown in Fig. 10. Like the wire and
OR gate from [9], these logic gates represent bit information
through the locations of charges in DB pairs. The charges at
the inputs default to the logic 0 position, and tend to take the
logic 1 position in the presence of input perturbers. In these
designs, the input combinations 01 and 10 are equivalent due
to symmetry; the output logic states of the proposed gates
are thus controlled by the count of logic 1 inputs. A change
in the output state as a result of incrementing the count of
input 1s is viewed as crossing a threshold. Two types of
thresholds have been identiﬁed, each exploiting a different
physical phenomenon: the push threshold, where Coulombic
repulsion leads to a reconﬁguration of charges in the gate; and
the pop threshold, where a shift in charge population occurs in
the gate due to local potential changes inﬂuenced by the inputs.
In the proposed logic gate designs, these thresholds are altered
by varying the distances between the radially placed DB pairs
that construct the gate. The push threshold is employed in the
AND, XOR, and XNOR gates where Coulombic repulsion
from inputs push the output to logic 1; the pop threshold
is employed in the XOR, NAND, and XNOR gates where
a charge is ejected from the gate output, leaving subsequent
DB pairs to logic 0. When integrating these gates into circuit
0 0
Out 0 0 0 1
Push
1 0 0 1 1 1
1 nm
(a) AND gate.
0 0
Out 0 1 1 0
1 0 0 1 1 1
1 nm
Push Pop
(b) XOR gate.
Pop
1 nm
0 0
Out 1 1 1 0
1 0 0 1 1 1
(c) NAND gate.
1 nm
0 0
Out 1 0 0 1
1 0 0 1 1 1
Push
Pop
(d) XNOR gate.
Fig. 10. DB logic gate implementations designed in SiQAD with differ-
ent logic behaviors achieved by tweaking the distances between the input
and output DB pairs. Simulation results are produced by SimAnneal with
µ=0.28 eV,r= 5.6, and λTF = 5 nm. The inputs are at logic 0 by
default; the addition of perturbers force those inputs to logic 1. Push and pop
thresholds, where changes in the input states lead to changes in output states,
are indicated. The orange arrows indicate locations where a charge has been
ejected as a result of crossing the pop threshold.
designs, modiﬁcations are often required to account for the
local upward band bending arising from additional negative
charges in the vicinity. The sensitivity of these logic gates
to changes in surface parameters will be further investigated
using an analytical operational boundary model in future work.
Using a combination of gates, a 2-input multiplexer has
been designed in SiQAD as shown in Fig. 11; also included
in the multiplexer is a fan-out design with one output inverted.
Going further, the largest DB binary logic circuit designed thus
far is a half-adder consisting of 72 DBs shown in Fig. 12.
A crossover circuit has also been designed and simulated as
shown in Fig. 13. These circuits were simulated with a higher
empirical chemical potential in order to achieve more compact
designs; in practicality, electrode-based ﬁeld-modulation is
expected to be used to control the surface electron population
through local band bending. It is important to note that the
Y-shaped layout for logic gates employed here is only one of
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Transactions on Nanotechnology
9
ASB
O
A=0
S=1
B=1
Out 1
5 nm
Fig. 11. A 2-input multiplexer designed with SiQAD and simulated using
SimAnneal with µ=0.32 eV,r= 5.6, and λTF = 5 nm. The multi-
plexer consists of 2 AND gates, 1 OR gate, and a fan-out which has one
inverted output as indicated.
C=1
S=0
A=1
B=1
A
BS
C
5 nm
Fig. 12. Ground state simulation of a half-adder using SimAnneal with
µ=0.32 eV,r= 5.6, and λTF = 5 nm.Aand Bare the inputs to
be summed; Sand Care the sum and carry respectively. All possible
combinations in the truth table are satisﬁed.
many possible ways to implement logic on the Si-DB physical
platform; alternatives, such as quantum-dot cellular automata
(QCA) [6], [39], are also worth further exploration.
VI. CO NC LU SI ON
Motivated by recent developments in DB quantum dots,
which have shown their potential to serve as emerging build-
ing blocks for atomic-scale logic circuits [9]–[11], we have
developed SiQAD to enable the exploration of this new
computational paradigm via the design and simulation of
DB circuits. DB layouts from previous works have been
recreated in SiQAD, with simulation results showing similar
ground state charge conﬁgurations. By sweeping through key
physical parameters in the ground state model, DB logic gates
have been found to be operational under a range of physical
parameters. The insights gained from SiQAD’s ground state
simulation capabilities have been used to propose additional
5 nm
Out
In
0 0 1 0 1 1
0 0 0 1 1 1
Fig. 13. Crossover circuit allowing two binary dot logic wires to cross.
Simulated using SimAnneal at µ=0.31 eV,r= 5.6, and λTF = 5 nm.
DB logic gates and circuits, laying the groundwork for future
logic designs on this platform. Furthermore, capabilities to
perform charge dynamic simulations in DB systems as well
as electrostatic landscape simulations with clocking electrodes
enable the exploration of prospective clocked DB systems.
With an intuitive interface and integrated simulation tools,
SiQAD is positioned to facilitate future investigations into
this novel computational platform technology at a time when
limitations to CMOS scaling have become evident. SiQAD’s
design and simulation functionalities will continue to be
project’s development at [23].
VII. CON TR IBUTIONS
K.W. initiated and guided the development of SiQAD. S.N.,
J.R., and H.N.C. developed SiQAD’s GUI and simulation
engines, as well as prepared the manuscript. R.L. contributed
to SimAnneal and circuit designs. L.L., T.H., M.R., W.V.,
T.D., R.W., and K.W. contributed towards the interpretation
of experimental results as well as the development of physics
models. Additionally, T.H. provided Fig. 1d and conducted the
reanalysis of experimental data shown in Table I. All authors
reviewed and commented on the manuscript. We would like
to thank the peer reviewers for their constructive feedback.
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... The geometrical disposition of wires in a two-dimensional electric field establishes the logical gates and other cells. Figure 7(a-b) presents the 2-input OR gate in a Y-shaped [15] format. ...
... In this work, the designs have been validated before the physical implementation using Silicon Quantum Atomic Designer (SiQAD) simulator. Furthermore, prior works present several other simulated designs for SiDB, such as Y-shaped [15] and T-shaped [17] 2-input gates, wire crossing [15,17], 3-input gates for all NPN classes [14]. In addition, there are more complex circuits such as half-adder [15] and full-adder [17]. ...
... In this work, the designs have been validated before the physical implementation using Silicon Quantum Atomic Designer (SiQAD) simulator. Furthermore, prior works present several other simulated designs for SiDB, such as Y-shaped [15] and T-shaped [17] 2-input gates, wire crossing [15,17], 3-input gates for all NPN classes [14]. In addition, there are more complex circuits such as half-adder [15] and full-adder [17]. ...
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After the continuous development of CMOS technology driven by transistor miniaturization and Moore’s law, the scientific community is witnessing the exploration of emerging paradigms to find new ways to develop computational systems. This paper presents critical concepts for understanding some of these new nanocomputing technologies, specifically field-coupled, quantum-dot cellular automata, nanomagnetic logic, silicon dangling bounds, photonic crystal logic, and DNA computing. Next, it shows emerging design automation tools for each of these areas and how they can be applied to support the development of new computing systems. The level of maturity and production speed of solutions achieved by conventional silicon technology thanks to very efficient electronic design automation (EDA) is remarkable. However, here we are dealing with technologies still in their infancy. Therefore, improvements in design automation tools are undoubtedly a way to accelerate the growth of new substrate alternatives and modern applications.
... One such implementation comes in the form of quantum dots made of silicon dangling bonds (SiDBs) on the hydrogen passivated silicon 100 2×1 surface (H-Si(100)-2×1), with the experimentally demonstrated capability to implement an OR gate that spans the length of < 10 nm [5]. This groundbreaking experimental demonstration, combined with latest developments in computer-aided design (CAD) capabilities offered by SiQAD [6], has spurred wide ranging research interests in the technology including the proposal of gate designs [6]- [10], support from an electronic design automation framework [11], an automated quantum dot gate design tool based on reinforcement learning [12], and evaluation of future applications [7], [13]. However, current simulation capabilities assume an ideal physical environment consisting of a perfect, i.e., defect-free, silicon monocrystal substrate. ...
... One such implementation comes in the form of quantum dots made of silicon dangling bonds (SiDBs) on the hydrogen passivated silicon 100 2×1 surface (H-Si(100)-2×1), with the experimentally demonstrated capability to implement an OR gate that spans the length of < 10 nm [5]. This groundbreaking experimental demonstration, combined with latest developments in computer-aided design (CAD) capabilities offered by SiQAD [6], has spurred wide ranging research interests in the technology including the proposal of gate designs [6]- [10], support from an electronic design automation framework [11], an automated quantum dot gate design tool based on reinforcement learning [12], and evaluation of future applications [7], [13]. However, current simulation capabilities assume an ideal physical environment consisting of a perfect, i.e., defect-free, silicon monocrystal substrate. ...
... Further exploration into SiDB logic implementations came in the form of computer-aided studies with the use of SiQAD [6]. Y-shaped BDL gates that implement various truth tables were proposed [6], [11], as were T/+-shaped BDL gates [8]- [10] and gates that employ alternative logic representations [13], exemplifying the flexibility of the SiDB logic platform. ...
Preprint
Experimental demonstration of nanometer-scale logic devices composed of atomically sized quantum dots, combined with the availability of SiQAD, a computer-aided design (CAD) tool designed for this technology, have sparked research interest in future atomic-scale logic systems based on these quantum dots. These studies range from gate designs all the way to new electronic design automation frameworks, resulting in synthesized circuits reaching the size of $32\times10^3\,$nm$^{2}$, which is orders of magnitude more complex than their hand-designed counterparts. However, current simulation capabilities offered by SiQAD do not include defect simulations, meaning that near-surface imperfections are not taken into account when designing these large SiDB layouts. This work introduces fixed-charge simulation into SimAnneal, the main SiDB charge configuration simulator of SiQAD, to cover an important class of defects that has a non-negligible effect on the behavior of nearby SiDB charge states at non-negligible distances -- up to 10 nm and beyond. We compared the simulation results with past experimental fittings and found the results to match fairly accurately. For the three types of defects tested, T1 arsenic, T2 silicon vacancy, and a stray SiDB, the root mean square percentage errors between experimental and simulated results are 3%, 17%, and 4% respectively. The availability of this new simulation capability will provide researchers with more tools to recreate experimental environments and perform sensitivity analyses on logic designs.
... This novel technology takes advantage of the SiQAD simulator [6], a state-of-art tool that allows prototyping and verification before the physical production of SiDB circuits. However, it is still a challenge to design logic gates and interconnections. ...
... However, it is still a challenge to design logic gates and interconnections. The current design method is either a formal analysis or manual development of each circuit by hand in the SiQAD, using the SimAnneal [6] engine. All those methods are expensive and time-consuming options, especially when working with large designs. ...
... The DB pair could modify its neighbors to allow for computational operation at high speeds and low energy usage, while maintaining the stability and predictability of the system. So far, the literature reports the implementation of 2-input [6], [7] and 3-input [7], [8] gates. The main design rules for the 2-input gates are Y-shape [6] and T-shape [7]. Figure 2 presents a Y-shape AND gate. ...
Conference Paper
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The novel Silicon Dangling Bond (SiDB) has become a prominent alternative to the current Complementary Metal Oxide Semiconductor (CMOS) transistor due to the low energy consumption and high integration potential. This article reports the classification of 2-input Y-shape SiDB designs using a Convolutional Neural Network and the development of a suit of 120 handmade SiDB designs. We use our suite of handmade gates to extract features to train and test the models. The results show our accuracy and the potential fundamental features for classifying 2-input SiDB gates, overcoming the need for a time-consuming circuit simulation. This novelty may mitigate the time complexity for simulations of larger SiDB circuits composed of 2-input gates in the future. We use the state-of-art CAD tool for SiDB technologies, named SiQAD, for simulation and verification. We achieve an average accuracy of 70% for the complete CNN implementation and 90% for the better internal network, with a speedup of at least 18x for 120 designs.
... Motivated by the promise of these experimental demonstrations, the research community has started to show great interest in the SiDB platform; with multiple computational explorations leading to various manually designed gates and circuits [3,10,11,29,30,45] along with promises of low-power and high frequency operation in a post-CMOS realm [10,11,29]. However, scaling up would greatly benefit from the contributions of the design automation community towards corresponding design frameworks, which do not currently exist for the SiDB platform. ...
... In the demonstrated system setup, SiDBs may possess 0, 1, or 2 electrons, corresponding to positive, neutral, and negative charge states respectively. In simulations throughout this work, SiDBs with cyan fill represent negatively charged sites and hollow SiDBs represent neutral sites; positive charge states are not relevant to the configuration of interest [18,30]. The charge states can be influenced by environmental factors such as the bulk dopant concentration [34] and the presence of electric fields [32]. ...
... A simulated reproduction of the OR gate is shown in Figure 1c. Here, the input bit state is set by the existence of a peripheral SiDB, dubbed a perturber [18,30], which exerts Coulombic pressure on the input SiDB-pair to emulate the presence of an input BDL wire at logic 1 state. An output perturber is present to emulate the presence of an output BDL wire. ...
... The flexibility offered by the new platform also bears unique new challenges, warranting further exploration, which was made possible by SiQAD [5], a CAD tool for the design and simulation of SiDB logic layouts calibrated to experimental results. The tool has fueled multiple recent works to introduce BDL logic gates with a variety of layout topologies and implemented components: wire crossings [5], [6], Y-shaped [5] and T-shaped [6] 2-input gates, as well as some 3-input gates (Xor3 [6], Majority [6], AndOr [7], OrAnd [7]). ...
... The flexibility offered by the new platform also bears unique new challenges, warranting further exploration, which was made possible by SiQAD [5], a CAD tool for the design and simulation of SiDB logic layouts calibrated to experimental results. The tool has fueled multiple recent works to introduce BDL logic gates with a variety of layout topologies and implemented components: wire crossings [5], [6], Y-shaped [5] and T-shaped [6] 2-input gates, as well as some 3-input gates (Xor3 [6], Majority [6], AndOr [7], OrAnd [7]). Although SiDB logic development is still in early stages, opportunities to offer forward-looking design methodologies that optimize the area footprint of future SiDB circuit implementations have already been identified. ...
... The flexibility offered by the new platform also bears unique new challenges, warranting further exploration, which was made possible by SiQAD [5], a CAD tool for the design and simulation of SiDB logic layouts calibrated to experimental results. The tool has fueled multiple recent works to introduce BDL logic gates with a variety of layout topologies and implemented components: wire crossings [5], [6], Y-shaped [5] and T-shaped [6] 2-input gates, as well as some 3-input gates (Xor3 [6], Majority [6], AndOr [7], OrAnd [7]). Although SiDB logic development is still in early stages, opportunities to offer forward-looking design methodologies that optimize the area footprint of future SiDB circuit implementations have already been identified. ...
Article
Full-text available
This article proposes a complete three-input gate library using atomic silicon quantum dots made of silicon dangling bonds.
... Rapid exploration of SiDBs outside of experimental laboratories was enabled by SiQAD 12 , a computeraided design (CAD) tool which offers design features for SiDB layouts and calibrated simulation models. Multiple binary-dot logic (BDL) logic gates and circuits have been proposed based on SiQAD verification [12][13][14][15][16] . The authors have experience designing such layouts via SiQAD 12,14 and find this to be a time consuming process which requires a significant amount of trial and error. ...
... Multiple binary-dot logic (BDL) logic gates and circuits have been proposed based on SiQAD verification [12][13][14][15][16] . The authors have experience designing such layouts via SiQAD 12,14 and find this to be a time consuming process which requires a significant amount of trial and error. Designing such layouts via SiQAD is an inherently time-consuming process that requires an understanding of the underlying physics of the technology to be able to navigate the complex, iterative process 12,14 . ...
... The authors have experience designing such layouts via SiQAD 12,14 and find this to be a time consuming process which requires a significant amount of trial and error. Designing such layouts via SiQAD is an inherently time-consuming process that requires an understanding of the underlying physics of the technology to be able to navigate the complex, iterative process 12,14 . ...
Preprint
Robust automated design tools are crucial for the proliferation of any computing technology. We introduce the first automated design tool for the silicon dangling bond quantum dot computing technology, which is an extremely versatile and flexible single-atom computing circuitry framework. The automated designer is capable of navigating the complex, hyperdimensional design spaces of arbitrarily sized design areas and truth tables by employing a tabula rasa double-deep Q-learning reinforcement learning algorithm. Robust policy convergence is demonstrated for a wide range of two-input, one-output logic circuits and a two-input, two-output half-adder, designed with an order of magnitude fewer SiDBs in several orders of magnitude less time than the only other half-adder demonstrated in the literature. We anticipate that reinforcement learning-based automated design tools will accelerate the development of the SiDB quantum dot computing technology, leading to its eventual adoption in specialized computing hardware.
... The definition of logic information relies on the concept of Quantum-dot Cellular Automata (QCA) [1]. FCN can also be realized with several physical interactions; for instance, it is possible to realize FCN computation by using magnets [2][3][4][5][6][7], or atomic silicon or metallic quantum dots [8][9][10]. ...
... The model computes the signal energy without the need for computationally expensive ab initio calculations. This enables the model to be easily integrated into CAD and simulation tools [18,19], which are gaining more and more importance in the field of FCN design [8,18,[20][21][22][23][24], enabling the analysis of signal energy in large circuits with considerable accuracy and without strongly impacting the demand of computational resources, thus favoring the design of future molecular FCN devices. The proposed model is generic and can be applied to any molecule provided it is monostable. ...
Article
Full-text available
Molecular Field-Coupled Nanocomputing (FCN) is a computational paradigm promising high-frequency information elaboration at ambient temperature. This work proposes a model to evaluate the signal energy involved in propagating and elaborating the information. It splits the evaluation into several energy contributions calculated with closed-form expressions without computationally expensive calculation. The essential features of the 1,4-diallylbutane cation are evaluated with Density Functional Theory (DFT) and used in the model to evaluate circuit energy. This model enables understanding the information propagation mechanism in the FCN paradigm based on monostable molecules. We use the model to verify the bistable factor theory, describing the information propagation in molecular FCN based on monostable molecules, analyzed so far only from an electrostatic standpoint. Finally, the model is integrated into the SCERPA tool and used to quantify the information encoding stability and possible memory effects. The obtained results are consistent with state-of-the-art considerations and comparable with DFT calculation.
... Another tool it is worth mentioning is a tool for the simulation of atomic silicon quantum-dot circuits, named Silicon Quantum Atomic Designer (SiQAD) [65], and NMLSim [66], for the simulation of NML technology. ...
Thesis
Among the technologies proposed to overextend the CMOS era, the molecular Field-Coupled Nanocomputing (FCN) is one of the most attractive technologies for future digital electronics. It encodes the information in nanometric molecules, following the Quantum-dot Cellular Automata (QCA) paradigm, permitting the realization of tiny and very dense digital devices working at ambient temperature. Furthermore, it propagates and elaborates the information through intermolecular electrostatic interaction at a very high speed. No current flow is involved in the information transport, thus minimizing the power dissipation. Notwithstanding the increased interest for molecular FCN, fueled by outstanding simulative and theoretical results, a working prototype has not yet been realized, unlike other FCN technologies such as the Nano Magnetic Logic (NML) or the Metallic QCA. Indeed, the difficulties correlated to the need for very high resolution for the nanofabrication of devices and for measuring molecule charges make the realization and the measurement of a working prototype challenging. Besides, the molecular FCN literature investigates the information encoding in molecules from a theoretical perspective and simultaneously employs the two-state approximation typical of the general QCA paradigm to study complex digital architectures. However, few attempts have been made to link the molecular characteristics to the two-state approximation models. Consequently, general QCA simulation tools scarcely consider the effective physics of the molecular interaction, preventing the assessment of molecular FCN technology as a possible candidate for future digital electronics. The literature proposes a vast amount of digital architectures which are supposed to be implemented with molecules, despite a real connection between circuits and molecular nature is still the chain missing link. This work demonstrates a methodological procedure to fill the gap between the physical molecular perspective and the circuit level. First, it analyses molecules with ab initio calculation, considering the effective molecular physics, demonstrating the encoding of the information in the static and dynamic regimes at different temperatures by considering the effect of molecular vibrations. Then, it models the molecule as an electronics device and develops the Self-Consistent Electrostatic Potential Algorithm (SCERPA): an optimized tool that permits the fast simulation of molecular FCN circuits by maintaining a solid link with molecular physics and providing results based on ab initio characterization of molecules. The tool is therefore used to analyze molecular FCN circuits and establish the physical-aware design of digital devices by considering the effective physics of the molecules. First, obtained results quantitatively describe the functioning, the stability, the crosstalk, and possible memory effects of molecular FCN devices. Secondly, results give feedback to technologists for the eventual realization of a working prototype, conceiving and demonstrating multi-lines clocked molecular devices, which favors the stability of information encoding and reduces the constraints on the resolution for the nanopatterning. This work fulfills the aim of filling the gap between the physical molecular perspective and the circuit level. It addresses and motivates the necessity of considering the molecular physics in the design of molecular circuits, intensely motivating the use of a physical-aware design tool and circumscribing the use of the general QCA tools for the design of molecular FCN circuits. Furthermore, this thesis work motivates further research on developing and validating a CAD-integrated physical-aware simulator able to provide reliable analyses of molecular devices and circuits and addresses the essential aspects of molecular FCN technology, making it promising as a candidate for future digital electronics.
Chapter
In this chapter, an extensible open-source framework for design automation of FCN circuit layouts is presented that is publicly available. The fiction framework was developed alongside the research for this book. The presented algorithms are implemented within the said framework to support open research and to make all claims reproducible. To facilitate future research in this field, fiction provides core data types needed by a multitude of design automation algorithms, e.g., logic networks, FCN layouts on different abstraction levels, clocking schemes, and gate libraries. Furthermore, file input and output functionalities are given that allow convenient exchange with logic synthesis and physical simulation tools. For experimental evaluations, fiction provides rich scripting and logging functionalities. Thus, it is providing a comprehensive sandbox for designers, researchers, and developers in the FCN domain.
Chapter
In an effort to establish this book as a stand-alone work, this chapter introduces important fundamentals and notations necessary for the comprehension of the included concepts. Boolean calculus, logic representations, and data structures form the basis for considerations throughout all the remaining chapters. Additionally, the satisfiability problems of prepositional and first-order logic together with optimized solvers for practical applications are discussed. Finally, the technology class concept Field-coupled Nanocomputing (FCN) is introduced from both a physical and a more formal point of view. FCN is the host technology for all algorithms presented in this work and thereby its focal point.
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It has been proposed that miniature circuitry will ultimately be crafted from single atoms. Despite many advances in the study of atoms and molecules on surfaces using scanning probe microscopes, challenges with patterning and limited thermal structural stability have remained. Here we demonstrate rudimentary circuit elements through the patterning of dangling bonds on a hydrogen-terminated silicon surface. Dangling bonds sequester electrons both spatially and energetically in the bulk bandgap, circumventing short-circuiting by the substrate. We deploy paired dangling bonds occupied by one moveable electron to form a binary electronic building block. Inspired by earlier quantum dot-based approaches, binary information is encoded in the electron position, allowing demonstration of a binary wire and an OR gate.
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At the atomic scale, there has always been a trade-off between the ease of fabrication of structures and their thermal stability. Complex structures that are created effortlessly often disorder above cryogenic conditions. Conversely, systems with high thermal stability do not generally permit the same degree of complex manipulations. Here, we report scanning tunneling microscope (STM) techniques to substantially improve automated hydrogen lithography (HL) on silicon, and to transform state-of-the-art hydrogen repassivation into an efficient, accessible error correction/editing tool relative to existing chemical and mechanical methods. These techniques are readily adapted to many STMs, together enabling fabrication of error-free, room-temperature stable structures of unprecedented size. We created two rewriteable atomic memories (1.1 petabits per in2), storing the alphabet letter-by-letter in 8 bits and a piece of music in 192 bits. With HL no longer faced with this trade-off, practical silicon-based atomic-scale devices are poised to make rapid advances towards their full potential.
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We report on tuning the carrier capture events at a single dangling bond (DB) midgap state by varying the substrate temperature, doping type, and doping concentration. All-electronic time-resolved scanning tunneling microscopy (TR-STM) is employed to directly measure the carrier capture rates on the nanosecond time scale. A characteristic negative differential resistance (NDR) feature is evident in the scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) measurements of DBs on both n and p-type doped samples. We find that a common model accounts for both observations. Atom-specific Kelvin probe force microscopy (KPFM) measurements confirm the energetic position of the DB's charge transition levels, corroborating STS studies. We show that under different tip-induced fields the DB can be supplied with electrons from two distinct reservoirs: the bulk conduction band and/or the valence band. We measure the filling and emptying rates of the DBs in the energy regime where electrons are supplied by the bulk valence band. We show that adding point charges in the vicinity of a DB shifts observed STS and NDR features due to Coulombic interactions.
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Using a noncontact atomic force microscope, we track and manipulate the position of single electrons confined to atomic structures engineered from silicon dangling bonds on the hydrogen terminated silicon surface. An attractive tip surface interaction mechanically manipulates the equilibrium position of a surface silicon atom, causing rehybridization that stabilizes a negative charge at the dangling bond. This is applied to controllably switch the charge state of individual dangling bonds. Because this mechanism is based on short range interactions and can be performed without applied bias voltage, we maintain both site-specific selectivity and single-electron control. We extract the short range forces involved with this mechanism by subtracting the long range forces acquired on a dimer vacancy site. As a result of relaxation of the silicon lattice to accommodate negatively charged dangling bonds, we observe charge configurations of dangling bond structures that remain stable for many seconds at 4.5 K. Subsequently, we use charge manipulation to directly prepare the ground state and metastable charge configurations of dangling bond structures composed of up to six atoms.
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We describe here a library aimed at automating the solution of partial differential equations using the finite element method. By employing novel techniques for automated code generation, the library combines a high level of expressiveness with efficient computation. Finite element variational forms may be expressed in near mathematical notation, from which low-level code is automatically generated, compiled and seamlessly integrated with efficient implementations of computational meshes and high-performance linear algebra. Easy-to-use object-oriented interfaces to the library are provided in the form of a C++ library and a Python module. This paper discusses the mathematical abstractions and methods used in the design of the library and its implementation. A number of examples are presented to demonstrate the use of the library in application code.
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