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On Efficient Concatenation of LDPC Codes With Constrained Codes

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An efficient concatenation of error correction codes with constrained codes is proposed in this paper. Generally, constrained codes are designed to match specified channels, whereas error correction coding schemes are designed to correct the channel errors. They both play important roles to ensure the integrity of data in data storage systems. In this study, we first investigate the design of k constrained codes combined with a low-density parity-check (LDPC) code, and then we extend the idea to the design of DC-free k constrained LDPC codes. Simulation results show that the proposed designs achieve an improved bit error rate (BER) performance, compared to prior art schemes. Especially, the proposed design for the DC-free k constrained codes not only fully eliminates the effect of error propagation in a reverse configuration, but also achieves significant DC suppression.
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1
On Efficient Concatenation of LDPC Codes with Constrained Codes
Chi Dinh Nguyen
1,2,3
, Kui Cai
1
, Bingrui Wang
1
, and Yan Hong
1
1
Singapore University of Technology and Design (SUTD), Singapore 487372
2
Faculty of Electrical and Electronic Engineering, Phenikaa University, Hanoi 12116, Vietnam
3
Phenikaa Research and Technology Institute (PRATI), A&A Green Phoenix Group JSC, No.167 Hoang Ngan, Trung Hoa, Cau
Giay, Hanoi 11313, Vietnam
An efficient concatenation of error correction codes with constrained codes is proposed in this paper. Generally, constrained codes
are designed to match specified channels, whereas error correction coding schemes are designed to correct the channel errors. They
both play important roles to ensure the integrity of data in data storage systems. In this study, we first investigate the design of k
constrained codes combined with a low-density parity-check (LDPC) code, and then we extend the idea to the design of DC-free k
constrained LDPC codes. Simulation results show that the proposed designs achieve an improved bit error rate (BER) performance,
compared to prior art schemes. Especially, the proposed design for the DC-free k constrained codes not only fully eliminates the effect
of error propagation in a reverse configuration, but also achieves significant DC suppression.
Index Terms— Low-density parity-check (LDPC) code, k constrained code, DC-free code, balanced codes.
I. I
NTRODUCTION
ECORDING
systems are typically designed based on a
concatenation of two separate coding schemes: an error-
correction coding (ECC) scheme and a modulation code or
constrained code. Each coding scheme realizes its own
encoding procedure to improve recording performance. The
ECC schemes attempt to correct already-occurred errors,
which can be caused by impairments of the channel, whereas
the constrained codes impose positive constraints onto the
input sequence to match specified channel characteristics, e.g.
a certain run-length constraint or a certain spectrum constraint.
The low-density parity check (LDPC) codes [1]-[3] are
currently regarded as potential candidates for the next
generation recording systems as they have been shown to have
low error floors. For a different aspect, in fact, the low code-
rate constraint codes can be easily constructed using lookup
tables. The challenge of designing high code-rate run-length
constrained codes comes from the complexity in
implementation of encoding and decoding processes [4]. The
modern constraint codes need to be designed with simple
encoders and decoders, but also high code-rates.
From the above-mentioned conditions, to design an
optimized coding scheme for recording systems, generally, the
following requirements need satisfying, 1) constrained codes
with high code-rate, low complexity, 2) ECC scheme with low
error floors, 3) non or limited error propagation.
To deal with the problem, several approaches using LDPC
codes for the ECC scheme have addressed [5]-[10]. In [5], a
user-data word was split into some portions, and then each
portion was encoded by a constrained encoder and was
formatted according to the LDPC structure so that combined
ECC-constrained codewords satisfied both the ECC structure
condition and the constrained code condition. However, this
construction was complicated and inflexible because of using
many constrained encoders and matching the output of the
constrained encoders to the LDPC structure. Moreover, a
computation of error correction syndrome from the first
constrained sequence and a first portion of the LDPC was
needed. A partial reverse concatenation was presented in [6] to
improve error-rate performance for tape drives. This
construction was quite bulky and complex since using two
ECCs at the same time. Vasic and Pedagani [7] proposed an
ECC-modulation concatenation based on flipping, whereby
selected bits in the LDPC codeword were deliberately flipped
to satisfy the constraints. A concatenation of run-length-
limited and ECC scheme based on uniform interleaving was
proposed in [8]. Han and Ryan also proposed a simple method
to concatenate a structured LDPC code and a high rate
constrained code [9]. We use the models in [9] as benchmarks
to assess the performance of the proposed designs.
In this study, we first design a configuration of k
constrained codes with LDPC codes. The k constrained codes
herein are constructed using a nibble replacement method
[10], [11], which as reported recently could achieve high code-
rates, simple encoders and decoders, and limited the error
propagation. Then, we also extend our research to design DC-
free k constrained LDPC codes. To obtain DC-free channel
sequence, our strategy is carried out twofold, 1) use guided
scrambling (GS) [4] to randomize for the user part, 2) use a
4/6 balance code to construct DC-free sequence for the parity
part. Doing this way, the error propagation is fully eliminated
before LDPC decoding and the performance of the LDPC
decoder is significantly improved accordingly.
Fig. 1. Parity error propagation in the reversed concatenation.
R
Manuscript received ... Corresponding author: Kui Cai (e-mail:
cai_kui@sutd.edu.sg).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier (inserted by IEEE).
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It is important to note that the proposed design is a reversed
concatenation, where the signal is first encoded by a
constrained code, and the constrained coded signal is then
encoded by a systematic ECCs. The parity part is reencoded
by the second constrained code. However, at the receiver, the
second modulation encoder for the parity part has no error
correction capability, and may propagate errors to the ECC
decoder. In other words, the error propagation means the error
propagation of the parity information part before decoded by
the ECC decoder herein. Fig. 1 illustrates the situation.
The rest of this paper is organized as follows. The
construction of k constrained codes based on the nibble
replacement is introduced in Section II. The proposed designs
are presented in Section III. Simulation results and discussion
are shown in Section IV. Finally, the concluding remarks are
shown in Section V.
II.
K CONSTRAINED
C
ODES
B
ASED ON
N
IBBLE
R
EPLACEMENT
The k constrained codes based on the nibble replacement
have been reported recently in [10], [11]. Basically, the
technique removes all inadmissible q-bit nibbles and replaces
them by q-bit admissible ones, where the admissible nibbles
are predefined, i.e., dec(u) ≥ w, where the function dec() refers
to the decimal representation of a binary sequence u, and w is
a predefined integer. During retrieving information, the signal
is uniquely decoded by the receiver through two
corresponding steps, de-flipping and de-replacing processes.
Detail designing of k constrained codes with w = 1 used in this
research is represented as follows,
A. Encoding of k constrained codes
The encoding procedure consists of two steps, the first step
is the nibble replacement, and the other is the nibble flipping.
For the first step, the n-1 user bits are split into a first nibble of
q-1 bits and subsequent L-1 nibbles of q bits. The first nibble
prefixed with an initial pivot bit of “1” is named as pivot
nibble. The encoder then carries out scanning for L-1
subsequent nibbles to find out all-0 nibbles (i.e. inadmissible
nibbles), whereby an all-0 nibble refers to
 
0,0,..., 0
nibble.
Once an all-0 nibble is found out, the encoder is to 1) replace
it by the pivot nibble; 2) set the pivot bit to “0”; 3) convert the
address and the decimal value of the all-0 nibble into the
binary data and then use the remaining q-1 bits of the pivot
nibble to store. The encoder continues the scanning to find and
replace the inadmissible nibbles in the rest of the user data
sequence.
The nibble flipping is then used in the second step of the
encoding process. We denote L nibbles obtained from the first
step as U
i
, i = [1, L]. The encoder first checks each of the L
nibbles with the last bit of the previous nibble, i.e. checking
{U
i
, U
i-1
(q)}. In case of U
i
is all-1 nibble, at the same time U
i-
1
(q) = 1, the encoder flips whole nibble U
i
. Otherwise, the
encoder outputs the unchanged nibble U
i
. The nibble of all-1
refers to
 
1,1,...,1
nibble.
B. Decoding of k constrained codes
At the receiver, the decoding procedure is also established
in two steps, the first is a de-flipping process, and the other is
a recursively de-replacing one. Let us denote L received
nibbles as
,
i
U
i = [1, L]. In the first step, the decoder checks
each of the L received nibbles, if
 
0,0,..., 0
i
U
then the
decoder flips
,
i
U otherwise, the decoder keeps
.
i
UDuring the
second step, the decoder checks the pivot bit of the first
nibble, if the pivot bit is equal to “1”, the user data is easily
decoded by moving the pivot bit from the received sequence.
Otherwise, the decoder will recover the information by simple
recursively de-replacing the replacement [10]. Examples of
the designed k constrained codes are shown in TABLE I.
III. P
ROPOSED
D
ESIGNS OF K CONSTRAINED
C
ODES WITH
LDPC
In this section, we first present the concatenation of k-
constraint codes and an LDPC code. Later we extend the idea
to design the DC-free k constrained LDPC codes.
(a)
TABLE
II
M
APPING
4-
BIT
D
ATA
S
EQUENCE
I
NTO
6-
BIT
B
ALANCED
S
EQUENCE
4-bit input 6-bit output 4-bit input 6-bit output
0000 010101 1000 100101
0001 000111 1001 110100
0010 010011 1010 100011
0011 010110 1011 110010
0100 001101 1100 101001
0101 001011 1101 101100
0110 001110 1110 111000
0111 011010 1111 101010
TABLE
I
D
ESIGNED K CONSTRAINED
C
ODES
n R=(n-1)/n q L=2
q-1
k=2(q-1)
12 0.9167 3 4 4
32 0.9688 4 8 6
80 0.9875 5 16 8
192 0.9948 6 32 10
448 0.9978 7 64 12
1024 0.9990 8 128 14
2304 0.9996 9 256 16
5120 0.9998 10 512 18
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(b)
Fig. 2. Block diagram of the proposed designs. (a) The 1
st
design of k
constrained LDPC codes; (b) The 2
nd
design of DC-free k constrained LDPC
codes. NRE and NRD stand for Nibble Replacement Encoder and Nibble
Replacement Decoder, respectively.
A. The design of k constrained LDPC codes
Fig. 2a shows a block diagram of the first proposed design.
The user data are first encoded using the (1023,1024) nibble
replacement encoder (NRE) as presented in Section II. The
signal is passed through the LDPC encoder. The output of
LDPC encoder is composed of two parts, the user part and the
parity part. The parity part is then encoded by the (31,32)
NRE. The encoded parity signal then is concatenated with the
user part through a multiplexer. At the receiver, a de-
multiplexer separates the received user and parity parts. The
parity part is first decoded by the (31,32) nibble replacement
decoder (NRD), and then is concatenated with the received
user and sent to the LDPC decoder. The output of the LDPC
decoder is finally decoded by the (1023,1024) NRD.
B. The design of DC-free k constrained LDPC codes
Binary codes with a spectral null at zero frequency (f = 0)
are called DC-free codes. The DC-free codes are a subclass of
spectrum shaping codes. The codes have been employed in
many applications of digital transmission and recording
systems [12]-[14]. For example, the effects of low-frequency
noise which can be caused by some scratch on the disc surface
are easily avoided using the DC-free codes in the optical
memory devices. The DC-free k constrained codes are
motivated by the need of combining the typical features of
both DC-free and k constrained codes.
Fig. 2b shows a block diagram of the second proposed
design. As shown in this figure, DC controlling is carried out
separately for the user part and the parity part. For the user
part, DC controlling is completed using the GS method [4].
During the encoding procedure, the m user bits are prefixed
with p redundant bits, it means a selection set 2
p
candidates of
(m + p) bits is generated. The signal is then scrambled with a
polynomial g(x). After scrambling, the 2
p
scrambled sequences
of (m + p) bits are encoded by the user-NRE (1023,1024). The
encoder then selects the best codeword according to the
minimum running digital sum (RDS) criterion. The DC-free k
constrained signal continues to be processed by the LDPC
encoder.
The DC controlling on the k constrained parity bits is
designed based on the concatenation of the k constrained NRE
(31,32) and a simple balance modulation code (4,6). The
parity part of the output of the LDPC encoder is first
converted into k constrained sequences, then controlled DC by
the balance code. The encoding of the balance modulation
code is a mapping 1-1 between the 4-bits input into the block
of balanced 6-bit output using a little mapping table as shown
in TABLE II. The decoding procedure is based on the
Euclidean distance concept.
At the receiver, the parity signal is first decoded by the
demodulation code. We believe that using the balance
modulation will reduce the effect of error propagation for the
parity part, and the input of the LDPC decoder is also
improved accordingly. At the output of the LDPC decoder, the
signal is decoded by the user-NRD. The untied k constrained
signal is then de-scrambled and removed the p redundant bits
to recover the original user data through the de-scrambler.
IV. S
IMULATION
R
ESULTS AND
D
ISCUSSION
The signal-to-noise ratio (SNR) is herein defined as
 
10
2 2
SNR 10 ,
log
p
n
R
V
 
where V
p
is the peak of a readback
signal,
2
n
is the noise power, and R is total code-rate. The
proposed designs are simulated over the additive white noise
(AWGN) channel as a generic data storage channel. It is
important to note that the proposed designs relax k of 14.
Moreover, since the LDPC codes of [9] are not fit-well to the
NREs in the proposed design, for applying the LDPC codes
into the proposed design, a number of added “dummy” bits are
necessary to match the input/output data of the encoders.
For the first case of k constrained LDPC codes, constructing
the k constrained LDPC code in [9], named RLL5051-LDPC
code herein, has based on the concatenation of a run-length-
limited (RLL) (50,51) code and the LDPC (4182,4592) code.
The LDPC code for the proposed design is same as that of [9].
We use a sum-product algorithm for the LDPC decoders. The
comparison between the first proposed design and the
RLL5051-LDPC code is shown in Fig. 3 in term of bit-error
rate (BER). It is straightforward to see that the BER
performance of the first proposal is better than that of [9]. The
performance gain can be explained since, one of the main
reasons, the first one has provided a higher code rate
compared to the prior-art suggested scheme of [6], the code-
rate of 0.9075 compared to that of 0.8929. In other words,
based on the SNR definition, the higher code-rate, the less
noise effect.
For case of the DC-free k constrained LDPC design, we first
investigate the spectrum of the second proposed design. Fig. 4
shows the simulated power spectrum density (PSD) of the
proposal with two different redundant-bit lengths p during the
user-GS (p = 3, g(x) = 1 + x + x
3
and p = 5, g(x) = 1 + x + x
5
.)
As shown in Fig. 4, the proposed design generates spectrum
nulls of more than -50 dB.
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Fig. 3. BER comparison in the case of k constrained LDPC codes.
Fig. 4. Simulated PSD of the proposed design according to different
redundancies for the GS.
Fig. 5. Error propagation for the second proposed design of DC-free k
constrained LDPC code.
Fig. 6. BER comparison in the case of DC-free k constrained LDPC codes.
The DC-free k constrained LDPC scheme of [9], named
DCRLL5054-LDPC code herein, has been constructed based
on a separate controlling DC on the user part and the parity
part. The DC controlling on the user part is accomplished
using a DC-free RLL code (50,54), which is a combining of
the above-introduced RLL (50,51) and a 3-bits GS. Moreover,
a purposeful selected flipping for a party of the parity bits is
used to control DC for the parity part.
There are two LDPC codes to be used in the second design,
namely, a (4428,4920) LDPC code which is same as in [9] and
a (4096,4344) LDPC code which not only matches with the
NREs/NRDs, i.e. there are no “dummy” bits, but also provide
a higher code rate. We first consider the performance of the
proposal for the effect of error propagation. As shown in Fig.
5, there is no error propagation for the parity part in the
proposed design. The result is obtained due to the advantage
of using the (4,6) balance modulation block code for
controlling DC-free for the parity part. First, the block code
does not propagate errors thanks to the independence of
encoded blocks, in general, it is always one of the most
favored choices for storage systems. Second, the balanced
codewords provide the DC suppression very well. Especially,
the balance code is extremely useful for error-correction
power because the minimum Hamming distance between
balanced codewords is always at least 2. This distance is
thoroughly exploited by many detection schemes, in the
research, for simplicity’s sake, we use the Euclidean distance
concept to detect the parity data sequence. Fig. 5 shows
enhanced BER performances of the parity part at the input of
the LDPC decoder.
Finally, we estimate the performance of the second
proposed scheme with different code-rates and compare to the
DCRLL5054-LDPC in term of BER. As shown in Fig. 6, the
proposed design with the (4096,4344) LDPC code provide the
most-effective performance, followed by the one with the
(4428,4920) LDPC code, and the DCRLL5054-LDPC,
respectively. For instance, at 10
−4
BER, the DCRLL5054-
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LDPC is about 0.4 dB and 0.7 dB worse than the proposed
design with the (4428,4920) LDPC code and with the
(4096,4344) LDPC code, respectively.
V. C
ONCLUSION
In this work, we have proposed two new methods for
concatenating the LDPC codes with the constrained codes.
The proposed designs deployed the nibble-based technique to
generate k constrained sequences. In the case of the DC-free k
constrained LDPC code, DC-free channel coded sequences
have been constructed based on the GS technique and the (4,6)
balanced modulation code. The designed DC-free k
constrained code has been further combined with the LDPC
code such that the modulation constraints were satisfied at
both the user and parity parts. The proposed designs have
achieved high code rates and avoided the effect of error
propagation with a very simple added part. The BER
performance has also been improved substantially. Moreover,
the proposed DC-free k constrained LDPC code generates
spectrum nulls of more than -50 dB at DC with reasonable
computational complexity.
A
CKNOWLEDGMENT
This work is supported by Singapore Ministry of Education Academic
Research Fund Tier 2 MOE2016-T2-2-054, SUTD-ZJU grant
ZJURP1500102, and SUTD SRG grant SRLS15095.
R
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... Channel codes in data storage devices can be categorised into two types, namely, error-correction coding (ECC) and modulation coding (MC) [7,8]. The ECCs introduce some redundancy to identify and correct already-occurred errors. ...
... Especially, soft-output Viterbi algorithm-based (SOVA-based) approaches were investigated in [12][13][14][15][16][17]. Encoding schemes to exclude 2D ISI effects were presented as well [18][19][20][21][22]. An iterative 2D SOVA (iSOVA) [13] was proposed to improve the system performance under the effect of 2D interference. ...
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This paper proposes systematic code design methods for constructing efficient spectrum shaping codes with the maximum runlength limited constraint k, which are widely used in data storage systems for digital consumer electronics products. Through shaping the spectrum of the input user data sequence, the codes can effectively circumvent the interaction between the data signal and servo signal in high-density data storage systems. In particular, we first propose novel methods to design high-rate k constrained codes in the non-return-to-zero (NRZ) format, which can not only facilitate timing recovery of the storage system, but also avoid error propagation during decoding and reduce the system complexity. We further propose to combine the Guided Scrambling (GS) technique with the k constrained code design methods to construct highly efficient spectrum shaping k constrained codes. Simulation results demonstrate that the designed codes can achieve significant spectrum shaping effect with only around 1% code rate loss and reasonable computational complexity.
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Two-dimensional magnetic recording (TDMR) is a promising technology for boosting areal densities (ADs) using sophisticated signal processing algorithms within a systems framework. The read/write channel architectures have to effectively tackle 2-D intersymbol interference (ISI), 2-D synchronization errors, media and electronic noise sources, as well as thermal asperities resulting in burst erasures. The 1-D low-density parity check (LDPC) codes are well studied to correct large 1-D burst errors/erasures. However, such 1-D LDPC codes are not suitable for correcting 2-D burst errors/erasures due to the 2-D span of errors. In this paper, we propose construction of a native 2-D LDPC code to effectively correct 2-D burst erasures. We also propose a joint detection and decoding engine based on the generalized belief propagation algorithm to simultaneously handle 2-D ISI, as well as correct bit/burst errors for TDMR channels. This paper is novel in two aspects: 1) we propose the construction of native 2-D LDPC codes to correct large 2-D burst erasures and 2) we develop a 2-D joint signal detection-decoder engine that incorporates 2-D ISI constraints, and modulation code constrains along with LDPC decoding. The native 2-D LDPC code can correct >20% more burst erasures compared with the 1-D LDPC code over a 128 × 256 2-D page of detected bits. Also, the proposed algorithm is observed to achieve a signal-to-noise ratio gain of >0.5 dB in bit error rate performance (translating to 10% increase in ADs around the 1.8 Tb/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> regime with grain sizes of 9 nm) as compared with a decoupled detector-decoder system configuration over a small 2-D LDPC code of size 16 × 16. The efficacy of our proposed algorithm and system architecture is evaluated by assessing AD gains via simulations for a TDMR configuration comprising of a 2-D generalized partial response over the Voronoi media model assuming perfect 2-D synchronization.
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Coding schemes in data-storage systems use either conventional or reverse concatenation of a modulation code and an error-correction code. A new reverse concatenation scheme, called partial reverse concatenation, is introduced to reduce the coding overhead, improve the error-rate performance and simplify implementation. The proposed concatenation scheme uses an outer error-correction code, a high-rate modulation code and an inner error-correction code. The error-rate performance of partial reverse and conventional concatenation architectures are compared using measurements from tape drive channels. It is shown that, compared with a conventional concatenation scheme, an LDPC-code-based partial reverse concatenation scheme improves the signal-to-noise ratio that is required to achieve a bit-error rate of 1×10-20 by 1.8 dB.
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In this paper, we will present coding techniques for the character-constrained channel, where information is conveyed using q-bit characters (nibbles), and where w prescribed characters are disallowed. Using codes for the character-constrained channel, we present simple and systematic constructions of high-rate binary maximum runlength constrained codes. The new constructions have the virtue that large lookup tables for encoding and decoding are not required. We will compare the error propagation performance of codes based on the new construction with that of prior art codes.
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A low-density parity-check code is a code specified by a parity-check matrix with the following properties: each column contains a small fixed number j geq 3 of l's and each row contains a small fixed number k > j of l's. The typical minimum distance of these codes increases linearly with block length for a fixed rate and fixed j . When used with maximum likelihood decoding on a sufficiently quiet binary-input symmetric channel, the typical probability of decoding error decreases exponentially with block length for a fixed rate and fixed j . A simple but nonoptimum decoding scheme operating directly from the channel a posteriori probabilities is described. Both the equipment complexity and the data-handling capacity in bits per second of this decoder increase approximately linearly with block length. For j > 3 and a sufficiently low rate, the probability of error using this decoder on a binary symmetric channel is shown to decrease at least exponentially with a root of the block length. Some experimental results show that the actual probability of decoding error is much smaller than this theoretical bound.