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A Health Factor for Process Patterns Enhancing Semiconductor Manufacturing by Pattern Recognition in Analog Wafermaps
... To provide a general framework for machine learning based process control, we define an indicator for process deviations, which is a generalization of our previous work [10]: the Health Factor for Process Control (HFPC), denoted as HF(x t ) for some observation x t ∈ D from the process at a time t, where D represents some feature space. Observations may represent sensor data or intermediate tests. ...
... This section evaluates the Health Factor for Process Patterns (HF), introduced in our prior work [10,13], and explores the applicability of the more general concepts and insights derived in this work. In a quantitative analysis, we demonstrates that the concept is applicable and yields an improvement over the domain's state-of-the-art methods. ...
... The HF [10] for semiconductor manufacturing operates on analog wafermaps and consists of preprocessing via Markov Random Fields to remove noise and background structures, a feature extraction step, and a subsequent selection of the classification method. As image features comprising the feature space D, a combination of Local Binary Pattern (LBP), Rotated Local Binary Pattern (RLBP) feature selectors (adapted for this purpose by Santos et al. [15]) and Histogram of Oriented Gradients (HOG) [16] is used. ...
Since high data volume and complex data formats delivered in modern high-end production environments go beyond the scope of classical process control systems, more advanced tools involving machine learning are required to reliably recognize failure patterns. However, currently, such systems lack a general setup and are only available as application-specific solutions. We propose a process control framework entitled Health Factor for Process Control (HFPC) to bridge the gap between conventional statistical tools and novel machine learning (ML) algorithms. HFPC comprises two main concepts: (a) pattern type to account for qualitative characteristics (error patterns) and (b) intensity to quantify the level of a deviation. While the system retains large model generality, allowing a broad scope of potential application areas, we demonstrate its favorable mathematical properties in a theoretical analysis. In a case study from the semiconductor industry, we underline that (a) our framework is of practical relevance and goes beyond conventional process control, and (b) achieves high-quality experimental results. We conclude that our work contributes to the integration of ML in real-world process control and paves the way to automated decision support in manufacturing.
... Finally, the Health Factor needs to be defined, based on the information gained from pattern recognition. This concept is presented by Schrunner et al. [18]. Resuming to the formalized problem setup presented in Section 2.4, the aim is to define a loss function V , as well as an appropriate posterior distribution P θ|d . ...
... As presented in recent work [18], it is possible to combine the three components, pattern type, pattern intensity and pattern criticality in an adequate way. Therefore, a loss function V will be specified, first. ...
... As a third aspect, the pattern type classifier consists of distinct elementary steps, hence the evaluation effort is higher than for the other components. Hence, the experiment aims to judge the quality of the pattern type classifier and extends the results presented in Schrunner et al. [18,19]. ...
Semiconductor manufacturing is a highly complex and competitive branch of industry, comprising hundreds of process steps, which do not allow any deviations from the specification. Depending on the application area of the products, the production chain is subject to strict quality requirements. While heading towards industry 4.0, automation of production workflows is required and hence, even more effort must be spent on controlling the processes accordingly. The need for data-driven indicators supporting human experts via monitoring the production process is inevitable, but lacks adequate solutions exploiting both, profound academic methodologies and
domain-specific know-how.
In many cases, process deviations cannot be detected automatically during the semiconductor frontend production. Hence, the wafer test stage at the end of frontend manufacturing plays a key role to determine whether preceding process steps were executed with the necessary precision. The analysis of these wafer test data is challenging, since process deviations can only be detected by investigating spatial dependencies (patterns) over the wafer. Such patterns become visible, if devices on the wafer violate specification limits of the product. In this work, we go one step further and investigate the automated detection of process patterns in data from analog wafer test parameters, i.e. the electrical measurements, instead of pass/fail classifications, which brings the benefit that deviations can be recognized before they result in yield loss - this aspect is a clear difference to state-of-the-art research, where merely specification violations are observed. For this purpose, an indicator for the level of concern associated with process patterns on the wafer, a so-called Health Factor for Process Patterns, is presented. The indicator combines machine learning techniques and expert knowledge.
In order to develop such a Health Factor, the problem is divided into three major components, which are investigated separately: ecognition of the pattern type, quantification of the intensity of a pattern and specification of the criticality associated with each pattern type. Since the first two components are intrinsically present in the wafer test data, machine learning systems are deployed for both, while criticality is specified by introducing expert and domain knowledge to
the concept. The proposed decision support system is semi-automated and thus, unifies pattern recognition and expert knowledge in a promising way.
The effectiveness of the proposed Health Factor is underlined by experiments conducted on simulated as well as real-world datasets. The evaluations show that the system is not only mathematically valid, but also practically applicable and fulfills the demands raised by a real-world production environment. Moreover, the indicator can be transferred to various product types or even related problem setups given a reliable training dataset.
... In the integrated circuits manufacturing industry, wafer fabrication is an essential procedure [1][2][3]. The manufacturing process of wafer is divided into two processes: front-end and back-end. ...
... The results obtained, including specification limits, x-y positions, wafer maps, etc are stored in a database as wafer data. In this experiment, we choose the WM-811 K dataset [3]. ...
Wafer Defect Classification (WDC) can be crucial to the wafer fabrication process. Engineers can quickly respond to improve the technological process, averting further defects through WDC. However, due to the complex fabrication steps, wafer defects are different in various types. This causes a severe data imbalance problem in WDC. To effectively solve the problem, this study introduces a class imbalanced wafer defect classification framework (CI-WDC) based on Variational Autoencoder Generative Adversarial Network (VAE-GAN). This framework consists of VAE-GAN and wafer defect classifier. Among them, VAE-GAN is responsible for creating new samples to solve the imbalance problem while the classifier is responsible for classifying wafer defect patterns. Specifically, VAE-GAN combines the advantage of a variational autoencoder (VAE) and generative adversarial network. VAE networks can produce subtle differences that do not affect the properties of the data when generating new images. At the same time, the proposed discriminator can help us constrain the generated images to be close to real samples and avoid irrational, feature-missing, and ambiguous samples. WM-811K dataset is utilized to verify the above method. The experimental results validate that the samples generated by VAE-GAN have a significant improvement in the performance of the WDC system.
... They focused on the recognition and assessment of known patterns in analog wafer test data. In [2], the authors proposed two feature extraction approaches to detect the pattern in wafer test data. They detected five patterns, labeled as the ring, spot, trend, two spots, and crescent, in the analog wafer test data set. ...
A wafer is a thin slice or substrate of semiconductors used for the fabrication of microelectronics devices. Thus, a large scale of precision is needed to make the microdevices work properly and to meet the requirements. Wafer test is an important step in wafer manufacturing to validate the activity of the microdevices and produces pictures of each wafer based on the electrical measurement of each of the devices on the wafer. Wafer shows different patterns while testing based on the requirement gap present on some of the devices on the wafer. To detect this error pattern manually is almost an impossible and time-consuming act. Therefore, we are presenting a wafer map pattern recognition system based on some ensemble approaches. Three (3) different ensembles including bagging, boosting, and voting approaches are implemented. Bagging performs relatively better than the others.
Multi-label learning studies the problem where each example is represented by a single instance while associated with a set of labels simultaneously. During the past decade, significant amount of progresses have been made toward this emerging machine learning paradigm. This paper aims to provide a timely review on this area with emphasis on state-of-the-art multi-label learning algorithms. Firstly, fundamentals on multi-label learning including formal definition and evaluation metrics are given. Secondly and primarily, eight representative multi-label learning algorithms are scrutinized under common notations with relevant analyses and discussions. Thirdly, several related learning settings are briefly summarized. As a conclusion, online resources and open research problems on multi-label learning are outlined for reference purposes.
Variable and feature selection have become the focus of much research in areas of application for which datasets with tells or hundreds of thousands of variables are available. These areas include text processing of internet documents, gene expression array analysis, and combinatorial chemistry. The objective of variable selection is three-fold: improving the prediction performance of the predictors, providing faster and more cost-effective predictors, and providing a better understanding of the underlying process that generated the data. The contributions of this special issue cover a wide range of aspects of such problems: providing a better definition of the objective function, feature construction, feature ranking, multivariate feature selection, efficient search methods, and feature validity assessment methods.
A decision tree is a classification algorithm that automatically derives a hierarchy of partition rules with respect to a target attribute of a large dataset. However, spatial autocorrelation makes conventional decision trees underperform for geographical datasets as the spatial distribution is not taken into account. The research presented in this paper introduces the concept of a spatial decision tree based on a spatial diversity coefficient that measures the spatial entropy of a geo-referenced dataset. The principle of this solution is to take into account the spatial autocorrelation phenomena in the classification process, within a notion of spatial entropy that extends the conventional notion of entropy. Such a spatial entropy-based decision tree integrates the spatial autocorrelation component and generates a classification process adapted to geographical data. A case study oriented to the classification of an agriculture dataset in China illustrates the potential of the proposed approach.
As manufacturing geometries continue to shrink and circuit performance increases, fast fault detection and semiconductor yield improvement is of increasing concern. Circuits must be controlled to reduce parametric yield loss, and the resulting circuits tested to guarantee that they meet specifications. In this paper, a hybrid approach that integrates the Self-Organizing Map and Support Vector Machine for wafer bin map classification is proposed. The log odds ratio test is employed as a spatial clustering measurement preprocessor to distinguish between the systematic and random wafer bin map distribution. After the smoothing step is performed on the wafer bin map, features such as co-occurrence matrix and moment invariants are extracted. The wafer bin maps are then clustered with the Self-Organizing Map using the aforementioned features. The Support Vector Machine is then applied to classify the wafer bin maps to identify the manufacturing defects. The proposed method can transform a large number of wafer bin maps into a small group of specific failure patterns and thus shorten the time and scope for troubleshooting to yield improvement. Real data on over 3000 wafers were applied to the proposed approach. The experimental results show that our approach can obtain over 90% classification accuracy and outperform back-propagation neural network.
Semiconductor manufacturing is a highly innovative branch of industry, where a high degree of automation has already been achieved. For example, devices tested to be outside of their specifications in electrical wafer test are automatically scrapped. In this work, we go one step further and analyse test data of devices still within the limits of the specification, by exploiting the information contained in the analog wafermaps. To that end, we propose two feature extraction approaches with the aim to detect patterns in the wafer test dataset. Such patterns might indicate the onset of critical deviations in the
production process. The studied approaches are: (A) classical image processing and restoration techniques in combination with sophisticated feature engineering and (B) a data-driven deep generative model. The two approaches are evaluated on both a synthetic and a real-world dataset. The synthetic dataset has been modelled based on real-world patterns and characteristics. We found both approaches to provide similar overall evaluation metrics. Our in-depth analysis helps to choose one approach over
the other depending on data availability as a major aspect, as well as on available computing power and required interpretability of the results.
Semiconductor manufacturers aim to fabricate defect-free wafers in order to improve product quality, increase yields, and reduce costs. Typically, wafer defects form spatial patterns that provide useful information, helping to identify problems and faults during the fabrication process. Machine learning (ML) methods have been used to classify these defects in order to locate the root causes of failure. This study proposes a novel deep-structured ML approach as an extension of our previous Randomized General Regression Network (RGRN) model, to identify and classify both single-defect and mixed-defect patterns. The principal motivation for this study is that a shallow-structured RGRN performs well on single-pattern defects, achieving an accuracy of 99.8%, but performs poorly when a wafer has mixed-defect patterns. The proposed approach improves RGRN performance, particularly on mixed-pattern defects, by incorporating a novel information gain (IG)-based splitter as well as deep-structured ML. A spatial filter is applied to remove random noise and reduce model bias during training. During the first detection stage, the splitter generates unique rules that are built using the IG theory and splits the defects data into single-defect and mixed-defect patterns. Single-defect patterns are then classified by RGRN, whereas mixed-defect patterns are fed into the deep-structured ML model for further classification. This combination improves the ability of the proposed approach to classify diverse defect patterns and achieve a better overall performance. Our experimental results demonstrate that the proposed approach achieves an overall detection accuracy of 86.17% on a dataset that contains real data representing both single-defect and mixed-defect patterns, as commonly found in real manufacturing scenarios, outperforming existing ML-based models.
Wafer maps contain information about defects and clustered defects that form failure patterns. Failure patterns exhibit the information related to defect generation mechanisms. The accurate classification of failure patterns in wafer maps can provide crucial information for engineers to recognize the causes of the fabrication problems. In this paper, we proposed a decision tree ensemble learning based wafer map failure pattern recognition method based on radon transform based features. Radon transform is applied on raw wafer map data to generate the new features which are exhibiting the geometric information of failure patterns in wafer map. Decision tree algorithm is applied to build decision tree ensemble and the final decision is made by aggregating the prediction results of decision trees. The effectiveness of the proposed method has been verified by using the real world wafer map data set (WM-811K). IEEE
Wafer maps provide important information for engineers in identifying root causes of die failures during semiconductor manufacturing processes. We present a method for wafer map defect pattern classification and image retrieval using convolutional neural networks (CNN). 28,600 synthetic wafer maps for 22 defect classes are generated theoretically and used for CNN training, validation and testing. The overall classification accuracy for the 6,600 test dataset is 98.2%. 1,191 real wafer maps are used for CNN performance evaluation for the same model trained by synthetic wafer maps. We demonstrate that by using only synthetic data for network training, real wafer maps can be classified with high accuracy. For image retrieval, a binary code for each wafer map is generated from an output of a fully connected layer with sigmoid activation. A retrieval error rate is 0.36% for the test dataset and 3.7% for the real wafers. Image retrieval takes 0.13 seconds per wafer map from the 18,000 wafer map library.
In semiconductor manufacturing processes, defect detection and recognition in wafer maps have received increasing attention from semiconductor industry. The various defect patterns in wafer maps provide crucial information for assisting engineers in recognizing the root causes of the fabrication problems and solving them eventually. This paper develops a manifold learning-based wafer map defect detection and recognition system. In this system, a joint local and nonlocal linear discriminant analysis (JLNDA) is proposed to discover intrinsic manifold information that provides the discriminant characteristics of the defect patterns. An unsupervised version of JLNDA (called local and nonlocal preserving projection) is further developed to provide a monitoring chart for defect detection of wafer maps. A JLNDA-based Fisher discriminant is further put forward for online defect recognition without the modeling procedure of recognizers. Comparisons with other regular methods, principal component analysis, local preserving projection, linear discriminant analysis (LDA) and local LDA, illustrate the superiority of JLNDA in wafer map defect recognition. The effectiveness of the proposed system has been verified by experimental results from a real-world data set of wafer maps (WM-811K).
Reliable semiconductor devices are of paramount importance as they are used in safety relevant applications. To guarantee the functionality of the devices, various electrical measurements are analyzed and devices outside pre-defined specification limits are scrapped. Despite numerous verification tests, risk devices (Mavericks) remain undetected. To counteract this, remedial actions are given by statistical screening methods, such as Part Average Testing and Good Die in Bad Neighborhood. For new semiconductor technologies it is expected that, due to the continuous miniaturization of devices, the performance of the currently applied screening methods to detect Mavericks will lack accuracy. To meet this challenge, new screening approaches are required. Therefore, we propose to use a data transformation which analyzes information sources instead of raw data. First results confirm that Independent Component Analysis extracts meaningful measurement information in a compact representation to enhance the detection of Mavericks.
High competitive pressure in the global manufacturing industry makes
efficient, effective and continuously improved manufacturing
processes a critical success factor. Yet, existing analytics in
manufacturing, e. g., provided by Manufacturing Execution Systems,
are coined by major shortcomings considerably limiting continuous
process improvement. In particular, they do not make use of data
mining to identify hidden patterns in manufacturing-related data. In
this article, we present indication-based and pattern-based
manufacturing process optimization as novel data mining approaches
provided by the Advanced Manufacturing Analytics Platform. We
demonstrate their usefulness through use cases and depict suitable
data mining techniques as well as implementation details.
Wafer maps can exhibit specific failure patterns that provide crucial details for assisting engineers in identifying the cause of wafer pattern failures. Conventional approaches of wafer map failure pattern recognition (WMFPR) and wafer map similarity ranking (WMSR) generally involve applying raw wafer map data (i.e., without performing feature extraction). However, because increasingly more sensor data are analyzed during semiconductor fabrication, currently used approaches can be inadequate in processing large-scale data sets. Therefore, a set of novel rotation- and scale-invariant features is proposed for obtaining a reduced representation of wafer maps. Such features are crucial when employing WMFPR and WMSR to analyze large-scale data sets. To validate the performance of the proposed system, the world's largest publicly accessible data set of wafer maps was built, comprising 811 457 real-world wafer maps. The experimental results show that the proposed features and overall system can process large-scale data sets effectively and efficiently, thereby meeting the requirements of current semiconductor fabrication.
Wafer yield is an important index of efficiency in integrated circuit (IC) production. The number and cluster intensity of wafer defects are two key determinants of wafer yield. As wafer sizes increase, the defect cluster phenomenon becomes more apparent. Cluster indices currently used to describe this phenomenon have major limitations. Causes of process variation can sometimes be identified by analyzing wafer defect patterns. However, human recognition of defect patterns can be time-consuming and inaccurate. This study presents a novel recognition system using multi-class support vector machines with a new defect cluster index to efficiently and accurately recognize wafer defect patterns. A simulated case demonstrates the effectiveness of the proposed model.
Semiconductor manufacturing involves lengthy and complex processes, and hence is capital intensive. Companies compete with each other by continuously employing new technologies, increasing yield, and reducing costs. Yield improvement is increasingly important as advanced fabrication technologies are complicated and interrelated. In particular, wafer bin maps (WBM) that present specific failure patterns provide crucial information to track the process problems in semiconductor manufacturing, yet most fabrication facility (fabs) rely on experienced engineers’ judgments of the map patterns through eye-ball analysis. Thus, existing studies are subjective, time consuming, and are also restricted by the capability of human recognition. This study proposes a hybrid data mining approach that integrates spatial statistics and adaptive resonance theory neural networks to quickly extract patterns from WBM and associate with manufacturing defects. An empirical study of WBM clustering was conducted in a fab for validation. The results showed practical viability of the proposed approach and now an expert system embedded with the developed algorithm has been implemented in a fab in Taiwan. This study concludes with a discussion on further research.
Electrical testing determines whether each die on a wafer
functions as originally designed. But these tests don't detect all the
defective dies in clustered defects on the wafer, such as scratches,
stains, or localized failed patterns. Although manual checking prevents
many defective dies from continuing on to assembly, it does not detect
localized failure patterns-caused by the fabrication process-because
they are invisible to the naked eye. To solve these problems, we propose
an automatic, wafer-scale, defect cluster identifier. This software tool
uses a median filter and a clustering approach to detect the defect
clusters and to mark all defective dies. Our experimental results verify
that the proposed algorithm effectively detects defect clusters,
although it introduces an additional 1% yield loss of electrically good
dies. More importantly, it makes automated wafer testing feasible for
application in the wafer-probing stage
A nonnegative tensor factorization approach for three-dimensional binary wafer-test data
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Device level maverick screening - detection of risk devices through independent component analysis
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