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A Novel Fault Self-Detectable Universal Quantum Reversible Circuits Array Design

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The amount of heat generated by computers is rapidly becoming one of the main problems for developing new generations of information technology. The thermodynamics of computation sets the ultimate physical bounds on heat generation. A lower bound is set by the Landauer Limit, at which computation becomes thermodynamically reversible. For classical computation there is no physical principle which prevents this limit being reached, and approaches to it are already being experimentally tested. In this paper we show that for quantum computation there is an unavoidable excess heat generation that renders it inherently thermodynamically irreversible. The Landauer Limit cannot, in general, be reached by quantum computers. We show the existence of a lower bound to the heat generated by quantum computing that exceeds that given by the Landauer Limit, give the special conditions where this excess cost may be avoided, and show how classical computing falls within these special conditions.
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Reversible logic has drawn great attention in recent years due to its emerging propagation in diverse range of areas. In this paper, we present a novel approach to unite addition and subtraction operations; circuits that perform addition/subtraction operations using fault tolerant reversible gates with fault detection capability. Adder and subtractor are basic building blocks of any Arithmetic Logic Unit; in this manner we first present the concept of merging those two circuits into one logical block. Then we introduce all possible approaches to construct fault tolerant united addition-subtraction circuit for not only reducing the number of gate but also minimizing quantum cost and garbages of circuit at a meaningful level. We demonstrate three types of half-adder/subtractor circuits and four types of full-adder/subtractor circuits. Again, we depict an algorithm based on our novel concept and we also present simulations on our proposed circuits. Besides, the comparative analysis of our proposed compact method shows our proposed circuit outperform than existing circuit as highest improvements of proposed circuits are 33.33% for garbage output, 26.66% for quantum cost and 50% for gate count. Finally, overall significance of our proposed designs is presented in conclusion. Keywords— Reversible logic, fault tolerant reversible circuits, fault tolerant gates, fault tolerant adder/subtractor circuit.
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America has the world's most developed highway network, every year for domestic automobile, motorcycle and parts and fuel oil, lubricating oil and so on final demand of the total reached 3, 84 billion (1996), It has 74000 km of the interstate highway system, plus the 180000 km of the NHS (national highway system) roads, there are more than 6.05 million km of other roads, The car ownership is expected to reach 230 million by 2000, including passenger cars accounted for 96.7%, truck accounted for 3.3%, Every year car 1.59 trillion vehicle kilometers of transport task, to the United States economic development and social improvement of living standards has an irreplaceable role. However, car accidents are killed 6 ~ 27 people in the United States the most main reason, Road traffic accident of deaths every year in more than 40000 people, plus about 3.4 million people were injured in the United States, The direct economic losses caused by road traffic accident every year a total of 1, 50 billion or more. In this paper, the highway traffic safety in recent 10 years were reviewed the latest development.
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Reversible circuits are an attractive computation alternative as they build the basis for many emerging technologies such as quantum computation or low power design. Since first physical realizations of reversible circuits have already been presented in the past, how to efficiently test such circuits became a current research topic. Consequently, several approaches for Automatic Test Pattern Generation (ATPG) have been presented in the past. However, the order in which the respective faults are targeted has a significant effect on the resulting test size. While determining good fault orderings has intensely been considered for the test of conventional circuits, according strategies for reversible circuits have not been evaluated yet. This is done in this paper. To this end, a fault ordering scheme is presented that explicitly exploits the reversibility of the underlying circuits. Experimental results show that the proposed scheme leads to improvements of up to 65% in the size of the testset.
Conference Paper
This article presents a novel technique for the generation of test set in a reversible quantum circuit. The algorithms are developed to derive the automatic test set (ATS) for the detection of all partial missing-gate faults, all single missing gate faults and multiple missing gate faults in an (n x n) reversible circuit implemented with k-CNOT gates. Experimental results on some benchmark circuits are also reported.