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THE MACRO MODELLING OF PHASE LOCKED LOOPS FOR THE
SPICE SIMULATOR
Mark Sitkowski
Design Simulation Systems Ltd
www.designsim.com.au
Abstract
The phase-locked loop has always presented several problems in terms of macro-
modelling.
A basic phase-locked loop comprises four main elements
a voltage-controlled oscillator producing a square-wave output
a phase-detector
a filter
error amplifier
Each of these, in itself, presents several problems in terms of circuit design, but the
principal difficulty is the fact that there is a vast disparity between the frequencies
involved.
The local oscillator runs at frequencies which are an order of magnitude higher than
the frequencies appearing at the output of the phase-detector. This leads to the
calculation of many data points, since the simulator sampling rate must be referred
to the highest frequency.
Most conventional approaches to phase-locked loop modelling produce macro-
models which may work in a test setup, but are unuseable in all but the most trivial
circuits, due to their complexity. This complexity is due, in part, to the inclusion of
semiconductor junctions and, also, to the use of voltage-controlled oscillators
designed by conventional electronic circuit design techniques. Simulation over
reasonable time intervals takes an unacceptably long time.
The approach described in this paper produces a macro-model which uses no
semiconductor junctions, and no regenerative feedback. The voltage-controlled
oscillator is implemented by means of a tuned circuit with infinite ‘Q’, set into
oscillation by an initial condition. To produce the square wave required by the phase-
locked loop, we use a virtual comparator, whose clipping characteristics are obtained
via an odd-order polynomial transfer function.
Performance of the complete macro-model is such that 20,000 point simulations,
corresponding to some 150 cycles of local oscillator, may be performed in around 15
seconds on an average computer.
Oscillators
Oscillators are, in themselves, problematic, due to the large number of iterations
necessary to evaluate regenerative circuits. Any attempt at modelling a controlled
oscillator using traditional oscillator circuit design techniques will lead to problems.
SPICE slows down appreciably when simulating any regenerative circuit, partly due
to the iteration count, and partly due to timestep control. Also, if the loop gain is
made high, to reduce the number of iterations, there is a risk that SPICE will fail to
converge or, if you're very unlucky, issue the error message which strikes fear into
the most stalwart: "Internal timestep too small”. Additionally, any use of
semiconductor devices will cause the simulation speed to be unacceptably slow
when simulating over practical time intervals, so it would seem that the correct
approach is to use no semiconductors, and no positive feedback.
In fact, it is best not to use an oscillator at all, but to employ the technique,
mentioned above, of an infinite ‘Q’ tuned circuit, as shown in Figure 1.
If a tuned circuit, comprising an inductor and capacitor is set into oscillation, it will
'ring' at its resonant frequency, without the need for positive feedback of any kind,
since the gain comes from the 'Q' of the circuit. The feedback mechanism, necessary
to sustain oscillations, is replaced by energy storage and transfer between the
reactive elements, which require very little effort on the part of the SPICE simulator.
The choice of series or parallel circuits is arbitrary, depending on whether a
maximum voltage oi maximum current resonance is desired or, perhaps, whether
voltage or current frequency control is desired. The control of frequency, by varying
the instantaneous value of either the inductor or the capacitor, is very simple, and
has infinite resolution, such that the frequency can be changed with zero delay,
within a half-cycle, or less.
Since the circuit elements used within SPICE are all ideal, it is a very simple matter
to design a lossless tuned circuit, set to resonate at the centre frequency of the
controlled oscillator. For a parallel tuned circuit, the drive is provided by a direct
current source connected across the circuit, as shown in Figure 1. By giving the
capacitor the property "IC=0”, SPICE will charge it up for you when the simulation
starts, thus causing the tuned circuit to oscillate. Since there is no damping, the
circuit will oscillate for ever. Well, almost. Connecting any kind of component (like a
voltage-controlled source) to the circuit will cause a small damping effect,
presumably because its input impedance is not infinite, but equal to the reciprocal of
the SPICE minimum conductance parameter, GMIN, set by default to 1E-12, and
resettable with the .OPTIONS card.
As phase-locked loops need a square-wave output, the sinusoidal waveform must
drive a comparator. Thus, if the sinusoid is made large enough, and clipped at a very
low enough level, any damping effects can be ignored. Accordingly, the source
current is set to 300 amps, to ensure a very high output voltage at resonance but, if a
constant amplitude is really important, a loose feedback loop can be incorporated, by
making the bias current dependent on the output voltage.
Voltage Controlled Oscillators
Having designed the oscillator, the next step is to make its frequency voltage-
variable. To control the oscillation frequency, it is necessary to vary the value of
either the inductor or the capacitor, in proportion to an external voltage. Although
SPICE contains voltage-variable capacitors, they are either part of a semiconductor
device, or their characteristics are controlled by a polynomial, defined in terms of the
terminal voltage. AIso, most voltage-variable capacitors described in the literature
also use the terminal voltage as the control and, accordingly, are not appropriate for
this application.
What is needed is a capacitor whose value is proportional to an external voltage,
which does not appear across the tuned circuit.
The actual implementation of a variable capacitor can be accomplished by the usual
technique of multiplying the instantaneous capacitive current by a factor and adding
it to, or subtracting it from the original current. This method owes its origins to the
hardware method of obtaining apparently large values of capacitance by placing
small capacitors between the base and collector of a transistor. The apparent
capacitance between collector and emitter would then be approximately hFE times
the true value.
However, this gives a very small range of control. The technique we have adopted, is
to insert a voltage source in series with the capacitor, whose value is the product of
the control voltage and the instantaneous voltage across the inductor. This will cause
the period of oscillation to be linearly proportional to the control voltage, giving us a
pulse-width modulator.
Figure 2 illustrates the configuration described above, and shows the parallel tuned
circuit with a voltage-variable capacitor incorporated.
The capacitive current is varied by varying the voltage across the capacitor with
voltage-controlled voltage source EIC, whose output is the product of input voltage
VIN, and the voltage across the inductor, VVCO. The last term of the polynomial
describing its transfer function is a scaling factor which effectively sets the loop gain:
POLY(2) VIN 0 VVCO 0 0 0 0 0 0.25
The nominal frequency of oscillation is, of course, set by
f = 1 / 2π
which, in our case is
1 / 6.28 = 31.83 MHz
The variation of the frequency with applied voltage is shown in Figure 3a, where the
input waveform is a series of voltage steps, varying between -3 and +3 volts. The
period of the output waveform may be seen to vary between approximately 42ns and
16ns.
The relationship between period and bias voltage is plotted in Figure 3b, and shows
the relationship to be linear, whereas the frequency is a 1/x law, as expected.
Figure 3c shows the variation with an applied 2MHz sine wave.
Comparator
There are several approaches to the design of a minimal comparator.
One which can be dismissed immediately, is that which attempts to accurately model
an integrated circuit comparator; the performance cost in terms of the number of
primitives to be evaluated is too great.
A simplified version of the integrated circuit comparator appears in traditional macro-
models, where the function is approximated by a high-gain amplifier, followed by
amplitude-limiting, via a series resistor, clamping diodes and voltage sources.
Although such an approach produces a good result, it still uses an excessive number
of primitives, which fact either causes convergence problems, or slows the
simulation.
Approaching the problem from basic principles, it may be seen that, essentially, the
ideal comparator performs the mathematical ‘signum’ function with an offset and
scaling factor. An examination of the odd-order polynomial functions, illustrated in
Figure 4, shows that they are symmetrical about the y-axis, and that the slope of the
function after the knee (which occurs for an x-axis value of unity) depends on the
actual order of the polynomial.
This function may be used to model a comparator, and the circuit is illustrated in
Figure 5.
A buffer, whose gain determines the slope of the dc transfer characteristic of the
comparator, drives a load resistor, to which it is coupled via a dependent source. The
source output is a function of the voltage across the load resistor, and is connected
so as to oppose the input voltage. Its transfer function is an 11th order polynomial.
When the load voltage is less than unity, the input waveform appears virtually
unchanged but, the nearer the load voltage gets to unity, the higher the voltage
subtracted from the input waveform, so the load voltage stays around 1.44 volts,
given the values shown.
Phase Detector
The phase detector used in many phase-locked loops is a four-quadrant analogue
multiplier. The design of this with SPICE primitives is trivial, since the multiplier is
itself a SPICE primitive. A non-linear voltage-controlled voltage source, with a
transfer function defined as:
POLY(2) FREF 0 VOUT 0 0 0 0 0 1
where FREF is the reference frequency, or input to the phase-locked loop, and
VOUT is the comparator output, performs the necessary function, and is shown in
Figure 6. Figure 7 is a plot of its output when driven by two pulse trains with periods
of 30ns and 31ns respectively.
Low-pass Filter and Error Amplifier
The low-pass filter is illustrated on the front end of the circuit in Figure 8. The two
resistors of the voltage divider should first be set so that the output of the phase
detector is limited to +/-3volts, and the capacitor value is then set to give an optimum
pull-in response. In the case of our demonstration circuit, we set the series resistor to
2000ohms, the shunt resistor to 20ohms, and the capacitor to 6000pF.
The amplifier shown is merely a voltage-controlled voltage source, with a gain of 20,
and a terminating resistor, which we set to 100ohms. Some phase-locked loops have
the facility of applying external voltages to the error amplifier, in order to perform FM
demodulation. If this is necessary then, the output of the error amplifier should drive
an adder.
Figure 9 shows the phase detector, again driven by the same two pulse trains, with
the simulated error amplifier output shown in Figure 10.
Complete PLL Circuit
The complete schematic for a phase-locked loop is shown in Figure 11, and the
SPICE netlist produced by the compiler is included below.
The simulator control statements have been left intact so that it may be tested
directly.
The performance of this PLL has not been optimised in any way, nor is it intended to
resemble any actual device.
The values of the components shown in red have been adjusted to match the output
voltage of the error amp to the input of the VCO.
The filter time constant is intentionally set to give an underdamped response, just to
illustrate the characteristics of the loop.
As a macro-model, it performs extremely well, permitting the simulation, within a
realistic time, of several hundred cycles of local oscillator. Also, since it models each
component of a phase-locked loop individually, it permits a large measure of
flexibility when attempting to apply this technique to real-world devices.
The Netlist
pll3
.tran 1n 2u 0 uic
*#iplot all
*#run
*#quit
.print tran v(5) v(2) v(3) v(4)
v1 5 0 pulse -3 3 0 1n 1n 15n 30n
x1 2 3 5 phdet
x2 4 2 erramp
x3 1 3 4 vco
** vmult:1 v1:3 v2:4
.subckt phdet 1 3 4
e1 1 0 poly(2) 3 0 4 0 0 0 0 0 1
r1 3 0 100
r2 1 0 100
r3 4 0 1g
.ends phdet
** verr:3 vphd:4
.subckt erramp 3 4
e2 3 0 1 0 20
r4 3 0 100
c1 1 0 6000p
r5 1 0 20
r6 4 1 2000
.ends erramp
** vvco:1 vout:3 vin:5
.subckt vco 1 3 5
icc 0 1 dc 300
r7 3 0 1.0
c2 1 7 50p ic=0
l1 1 0 0.5u
r8 5 6 1.0
e3 4 0 1 0 1.0
v2 6 0 dc 0
e4 4 3 poly(1) 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
e5 7 0 poly(2) 5 0 1 0 0 0 0 0 0.25
.ends vco
.end
The performance of the above netlist is shown in the simulator output in Figure 12.
Appendix
Figure 1
Figure 2
Figure 3a
Bias
Period
Freq
-3
4.23E-08
2.37E+07
-2
3.91E-08
2.56E+07
-1
3.56E-08
2.81E+07
-0.5
3.39E-08
2.95E+07
-0.2
3.27E-08
3.06E+07
0
3.15E-08
3.18E+07
0.2
3.11E-08
3.21E+07
0.5
2.97E-08
3.36E+07
1
2.78E-08
3.60E+07
2
2.25E-08
4.44E+07
3
1.59E-08
6.28E+07
Figure 3b
0.00E+00
1.00E+07
2.00E+07
3.00E+07
4.00E+07
5.00E+07
6.00E+07
7.00E+07
0.00E+00
5.00E-09
1.00E-08
1.50E-08
2.00E-08
2.50E-08
3.00E-08
3.50E-08
4.00E-08
4.50E-08
-3 -2 -1 -0.5 -0.2 0 0.2 0.5 1 2 3
Period
Freq
Figure 3c
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
