Write Disturbance Modeling and Testing for MRAM

Nat. Tsing Hua Univ., Hsinchu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.36). 04/2008; 16(3):277 - 288. DOI: 10.1109/TVLSI.2007.915402
Source: IEEE Xplore


The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C-test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-mum technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.

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Available from: Ding-Yeong Wang, Aug 22, 2014
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    ABSTRACT: As the semiconductor industry works to integrate increasingly more "non-CMOS" devices onto CMOS ICs, compact model development has become an important step in the circuit/system verification tool flow. This research focuses on the two- and three-dimensional modeling of the physical phenomena that occur in nanoscale magnetic devices. This includes the continuous time dynamics of the changing magnetization state in magnetic thin film spintronic devices such as GMR spin valves, toggle MRAM bits and magnetic tunnel junctions (MTJs). The various torques responsible for magnetization change are modeled in Verilog-A modules and have been simulated for several static and dynamic cases. Device behavior is verified using current-in-plane Oersted fields and current-perpendicular-to-plane, spin transfer torque (STT) as stimulus. All device compact models have electrical I/O and are being developed to provide accurate device terminal behavior when used in a circuit simulation environment with standard CMOS circuits. Graduation date: 2011
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