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Comprehensive Analysis of Data-Retention and Endurance Trade-Off of 40nm TaO x -based ReRAM
... Within this time at the respective operating (or storage) temperature, the HRS or LRS has to be stable enough to ensure a sufficiently large read window. Several groups investigated the retention of VCM ReRAM [30,103,[129][130][131][132][133][134][135][136][137][138][139][140][141]. As summarized in table 2.1, they typically find that the LRS read current decreases over time. ...
... In this case, E a is independent of the failure criterion. However, the reported degradation usually deviates from the ideal trend [82,129,134,141] and thus the obtained activation energy depends on the defined failure criterion. Additionally, the percentage of cells to reach the criterion affects the activation energy. ...
... The thermal stress during cycling may induce local modulations like crystallization which may increase the resistance or SET voltage [131,161]. It was furthermore demonstrated that a low power consumption of the switching operations may prolong the endurance of a system [162,163] With N moved per cycle being related to the read window, E barrier determining retention and N cycles this leads to a trade-off of read-window, retention and endurance [164] which is reported by several groups [129,139,141]. ...
For over 50 years, Moore‘s law functioned as road map for advancements in the semiconductor industry. Soon, the predicted exponential increase in the number of devices per microchip will reach physical limitations. In order to overcome these limitations, redox-based resistive switching random access memory (ReRAM) is discussed as promising candidate for future memory applications. Recently, also a potential application of ReRAM in neuro-inspired architectures is gaining a lot of attention. Among other approaches, valence change based memory (VCM) is studied intensively. Regardless of an application as classical memory or as neuronal network component, the reliability of ReRAM devices is the key attribute for industrial adaption. This dissertation addresses the three main components of the reliability VCM ReRAM devices, being variability, retention and endurance. Here, VCM ReRAM cells based on ZrO2 fabricated under laboratory conditions are characterized as well as industrial devices based on HfO2 as switching oxide. Throughout this work, a focus on large arrays instead of single cells is emphasized. The evaluation and interpretation is focused on the internal statistics rather than on the behavior of individual devices. The variability of VCM ReRAM remains one of the largest challenges for their large scale adaption in industrial applications. Whereas the stochastic nature of the switching process can be significantly reduced by appropriate programming algorithms, random fluctuations occur also between read operations. This read to read (R2R) variability is identified as key challenge in the short term stability of VCM ReRAM. It determines the intrinsic statistics of large memory arrays and effectively limits the read window between the low resistive (LRS) and high resistive state (HRS). The random R2R fluctuations are attributed to random jumps of the conduction supporting oxygen vacancies. In the HRS, these jumps lead to a log-normal read current distribution. Via an empirical model as well as kinetic Monte Carlo (KMC) methods, the most likely origin of these statistics is found to be tunneling across a normally distributed gap in HRS. Here, the exponential dependence of the read current on the tunneling gap results in the observed log-normal statistics. Investigating the long term stability or retention, the R2R variability remains a key characteristic of the investigated devices. The most critical aspect of the long term degradation of a programmed state is found to be a broadening of the whole distribution, i.e. increasing variability. The trend of the degradation is fitted by an empirical tunneling model which allows for extrapolation of data measured at higher temperatures towards the target retention time at lower operating temperature. Additionally, a statistical model based on the work of Abbaspour et al. is developed which explains the observed degradation by diffusion of oxygen vacancies from a confined filament region towards the active electrode. Finally, an algorithm is developed which increases the number of possible switching cycles, also referred to as endurance, of a device. It dynamically adjusts the programming parameters to ensure reliable switching. Since the frequency of applied adjustments determines the speed of the experiment, the algorithm dynamically adjusts this frequency to the tested cell. It therefore increases the measurement speed if a cell requires less adjustments. The algorithm is used to determine the maximum endurance for different material combinations. Thus, it is demonstrated that ohmic electrode metals with lower oxygen chemical potential ensure higher endurance which verifies the theoretical findings of Guo et al. All in all, this dissertation proposes to evaluate the reliability of VCM ReRAM for its intrinsic statistics rather than tracing single cells.
... Independent of the specific application of the ReRAMs, reliability is a major issue that has to be investigated and optimized [18]± [20]. Especially, endurance meaning the ability of huge numbers of faultless consecutive switching cycles is of great interest and will therefore be in the focus of our work [21], [22]. In the following, we present experimental results of 2 MBit VCM cells, predominantly showing great endurance. ...
In this work, we experimentally characterize the endurance of 2 Mbit resistive switching random access memories (ReRAMs) from a 16 MBit test-chip. Here, very rare failure events where the memory cells become stuck in the low-resistive state (LRS) are observed. As this failure mechanism is the limiting one concerning the endurance of this ReRAM implementation, extensive investigations are conducted and presented. The experimental findings are detailed via a voltage divider model, illustrating why memory cells can become stuck in the LRS. It is proposed, that an insufficient voltage dropping over the cell due to an unfavorable combination of cell- and transistor resistances is responsible for stuck-at-LRS bits. Furthermore, we give predictions for the origin of these suboptimal combinations. Additionally, a one-dimensional Kinetic Monte Carlo (KMC) model that allows a statistical investigation of large numbers of cells with regard to rare random events has been developed. Here, we fortify our proposed explanation for the observed failure mechanism by the simulation and evaluation of the switching process of the memory. All simulations are in very good agreement with the experimental data. Finally, based on our findings, we give suggestions for the improvement of switching algorithms.
... Due to the large variability in devices, the reliability of the platform can be significantly lower than the CMOS-based counterparts [41]. Similarly, the low endurance of a few emerging technologies can be exploited to induce fault attacks at runtime [42]. ...
Machine learning applications are characterised by the extreme amount of data movements necessary for fast training or classification, such as real-time image and speech recognition. Simultaneously, modern computing systems are predominantly based on the traditional von Neumann architecture, which involves separating the computing and memory unit, thus, connected through a data bus. This so called "von-Neumann bottleneck" limits the bandwidth and increases power consumption, which stands in stark contrast to the demands of machine learning applications. Neuromorphic computing represents a promising solution to overcome these limitations by using emerging non-volatile memory technologies. This computing paradigm overcomes the von Neumann bottleneck by shifting the computations to the memory unit, mimicking the biological brain (e.g., mammalian brain) in its capability to process a massive amount of information in a parallel fashion. Nevertheless, neuromorphic computing raises numerous open research questions and challenges. This work provides a comprehensive survey of neuromorphic computing focusing on three essential aspects. First, the latest neuromorphic system architectures are described, and the proposed enhancements over time are highlighted. Following, simulation platforms that are fundamental to investigate this new computing paradigm are reviewed from four different abstraction levels: system, architecture, circuit, and device level. In addition, hardware security threats are presented on already existing work in the CMOS domain to learn the lessons and identify the threats in neuromorphic platforms.
... Besides, several works have discussed the tradeoff between endurance and retention [71][72][73]. A better endurance can be achieved at the cost of retention degradation. ...
We provide an overview of the field of oxide-based filamentary resistive random access memory (RRAM) for deep learning neural networks (DNNs). After introducing the electrical characteristics of filamentary RRAM which are the main influences on the performance of DNNs, we show several cases focusing on the optimization of the linearity and symmetry of conductance modulation and precision. Progress in the optimization of energy efficiency and reliability of DNNs is then reviewed. Lastly, our recent work on DNNs based on analog filamentary RRAM, including the design and fabrication of the device, is introduced in detail.
Understanding the physical changes during electroformation and switching processes in transition-metal-oxide-based non-volatile memory devices is important for advancing this technology. Relatively few characteristics of these devices have been assessed in operando. In this work, we present scanning thermal microscopy measurements in vacuum on TaO x -based memory devices electroformed in both positive and negative polarities and high- and low-resistance states. The observed surface temperature footprints of the filament showed higher peak temperatures and narrower temperature distributions when the top electrode served as the anode in the electroformation process. This is consistent with a model in which a hot spot is created by a gap in the conducting filament that forms closest to the anode. A similar behavior was seen on comparing the high-resistance state to the low-resistance state, with the low-resistance footprint showing a lower peak and a larger width, consistent with the gap disappearing when the device is switched from high resistance to low resistance.
This study proposes a heterogeneous integration of precise and approximate storage in data center storage. The storage control engine allocates precise and error-tolerant applications to precise and approximate storage, respectively. The appropriate use of both precise and approximate storage is examined by applying a non-volatile memory capacity algorithm. To respond to the changes in application over time, the non-volatile memory capacity algorithm changes capacity of storage class memories (SCMs), namely the memory-type SCM (M-SCM) and storage-type SCM (S-SCM), in non-volatile memory resource. A three-dimensional triple-level cell (TLC) NAND flash is used as a large capacity memory. The results indicate that precise storage exhibits a high performance when the maximum storage cost is high. By contrast, with a low maximum storage cost, approximate storage exhibits high performance using a low bit cost approximate multiple-level cell (MLC) S-SCM.
As the limits of transistor technology are approached, feature size in integrated circuit transistors has been reduced very near to the minimum physically-realizable channel length, and it has become increasingly difficult to meet expectations outlined by Moore’s law. As one of the most promising devices to replace transistors, memristors have many excellent properties that can be leveraged to develop new types of neural and non-von Neumann computing systems, which are expected to revolutionize information-processing technology. This survey provides a comparative overview of research progress on memristors. Different memristor synaptic devices are classified according to stimulation patterns and the working mechanisms of these various synaptic devices are analyzed in detail. Crossbar-based memristors have demonstrated advantages in physically executing vector-matrix multiplication and enabling highly power-efficient and area-efficient neuromorphic system designs. The extensive uses of crossbar-based memristors cover in-memory logic, vector-matrix multiplication, and many other fundamental computing operations. Furthermore, memristor-based architectures for efficient neural network training and inference have been studied. However, memristors have non-ideal properties due to programming inaccuracies and device imperfections from fabrication, which lead to error or mismatch in computed results. To build reliable memristor-based designs, circuit-level, algorithm-level, and system-level solutions to memristor reliability issues are being studied. To this end, state-of-the-art realizations of memristor crossbars, crossbar-based designs, and peripheral circuitry are presented, which show both promising full-system inference accuracy and excellent power efficiency in multiple tasks. Memristor in-situ learning benefits from high energy efficiency and biologically-imitative characteristics, which are conducive to further realizing hardware acceleration of cognitive learning. At present, the learning and training processes of brain-like networks are complex, presenting great challenges for network design and implementation.
We investigate the impact of pulse programming conditions on data-retention of 40nm × 40nm TiN\HfO2\Hf RRAM devices, focusing on the failure of tail bits. We demonstrate that retention loss tail bit is not due to out diffusion of filament constituents but by low activation-energy (Ea~0.5eV) diffusing species, which are understood as metastable Oxygen (O)-ions in the neighborhood of the conductive-filament constriction. In order to minimize their impact, effective programming pathways are demonstrated, as the low-Ea population is better reduced by (i) using longer Write pulses rather than higher current-pulse amplitudes, and/or by (ii) using shorter reset pulse prior to Write set.
ReRAM is increasingly being developed for applications that require higher speeds and lower voltages than flash memory. We have found TaOx to have high performance and high reliability. However one of the phenomena observed in ReRAM is that each resistance after Set and Reset varies during every cycle. To stabilize resistive switching, the key is to limit these variations in resistance. In ReRAM, a conductive filament (CF) is created by the forming pulse. Resistive switching in the CF is based on reduction and oxidization using this voltage pulse. This paper reviews a hopping percolation model which we have proposed for the switching process, and this paper proposes an automatic forming circuit using our newly-developed externally-scalable forming pulse (ESF) scheme. In this CF model, conductive paths show different conductivities caused by the formation of different percolation networks that link hopping sites. Larger CFs show greater variation in resistance due to the many possible combinations of percolation networks. This makes it important to develop a forming technique that limits CFs to their optimal size. Forming is based on dielectric breakdown, so the pulse width ranges over approximately three orders. The automatic forming circuit detects, bit by bit, whether forming is over, and stops the forming pulse after a specified period. A forming pulse is then generated, using an external clock, to cover the range of pulse widths. This allows the filament size to be controlled to ensure it is uniform for all of the bits in the circuit, at the cost of only a small area overhead.
Application-aware solid-state drives (SSDs) with 2 adaptive coding schemes to improve reliability are presented. In NAND flash memory, a direct reliability trade-off exists between write/erase (W/E) cycle and data-retention (DR) time. Thus, SSDs can be used for applications that have long DR time and low W/E cycles, or short DR time with high W/E cycles. The n-out-of-8 level cell (nLC) scheme is proposed for low-cost, long-term, archive storage which is indispensable to preserve human digital data. nLC eliminates the memory states of the Triple-Level Cell (TLC) NAND flash memory from 8 to 7...4 levels. Universal asymmetric coding (UAC) is also proposed for cloud/security camera/enterprise storage environments which require high endurance but shorter DR time. Both nLC and UAC optimize coding based on the applications' required W/E cycle and DR. Bit-error rates (BERs) are improved by 79% and 52% with nLC and UAC, respectively.
We have proposed a retention degradation model based on an oxygen diffusion and percolation path cut mechanism in a filament of TaOx bipolar ReRAM. We have developed a new methodology for quantitating the conductive filament characteristics and have revealed that the retention property of ReRAMs can be explained in terms of filament characteristics, including filament size S, density of oxygen vacancies N(Vo), and density of residual oxygen N(Ox). We have improved the retention property of ReRAM under low current operation, by controlling these filament characteristics.
The retention model of a bipolar ReRAM considering the percolative paths in a conductive filament is proposed. We demonstrate, for the first time, that the control of oxygen vacancy concentration in a conductive filament is the key for ensuring data retention including tail bits. To improve the retention property under low-current operation, the size of the conductive filament must be scaled down while keeping the density of oxygen vacancy high enough. Based on this concept, we demonstrate both low-current operation and sufficient retention results exceeding 500 h at 150 degrees C, which correspond to more than 10 years at 85 degrees C.
A new oxygen diffusion reliability model for a high-density bipolar ReRAM is developed based on hopping conduction in filaments, which allows statistical predication of activation energy. The filament in the active cells is confirmed by EBAC and TEM directly for the first time. With optimized filament size, a 256-kbit ReRAM with long-term retention exceeding 10 years at 85°C is successfully demonstrated.
Highly reliable TaO<sub>x</sub> ReRAM has been successfully demonstrated. The memory cell shows stable pulse switching with endurance over 10<sup>9</sup> cycles, sufficient retention exceeding 10 years at 85degC. TaO<sub>x</sub> exhibits stable high and low resistance states based on the redox reaction mechanism, confirmed by HX-PES directly for the first time. An 8 kbit 1T1R memory array with a good operating window has been fabricated using the standard 0.18 mum CMOS process.