No full-text available
To read the full-text of this research,
you can request a copy directly from the authors.
Self-Heating Effects on Hot Carrier Degradation and Its Impact on Logic Circuit Reliability
Abstract
This paper discusses the impact of self-heating (SH) on ring-oscillator (RO) reliability and its correlation to hot carrier (HC) degradation. We show that HC degradation modulation due to SH is only significant for logic PFETs at highly accelerated DC conditions. We show that these SH effects on HC are greatly reduced at moderate acceleration. By stressing the ROs at extreme conditions, we show that the SH impact on HC does not affect RO degradation.
... Besides the study on the trap spatial distribution of high-k and ultra-thin oxide layer, charge pumping techniques based on the variation of the charge pumped with frequency and employed ring-oscillatorconnected devices are proposed in [16], [17]. According to the analysis of the trap density, some literatures have focused on revealing the physical mechanisms underlying aging in semiconductor devices [18]- [27]. ...
... According to the mechanism of single aging effect, it can be found that the traps generated by the BTI effect are distributed uniformly in the channel, while the traps generated by the HCI effect are mainly at the drain end [27]. When operating voltages are applied to both gate and drain of the transistor, the traps created by the two aging effects will work together. ...
The integration density of electronic systems is limited by the reliability of the integrated circuits. To guarantee the overall performance, the integrated circuit reliability must be modeled and analyzed at the early design stage. This paper reviews some of the most important intrinsic aging mechanisms of MOSFETs and elaborates the physical mechanism of the coupling between aging effects. Then the progress in reliability modeling under static and dynamic operational voltages is reviewed. It is found that although these models can accurately predict the degradation in short term, they are with large errors for the long-term degradation prediction. Besides, for the circuit-level reliability modeling and simulation approach, there are still problems to be solved. This article aims to provide guidance for researchers and practitioners in integrated circuit field, and highlight the challenges for reliability research. It is of great significance to the optimization of the reliability of integrated circuits.
... Since Self-heating effects is aggravated in vertical stacked GAA NS transistors comparing with prior generation FinFETs, it is critical to make accurate reliability projection with precise thermal modeling and characterization methodology. Numerous studies from academic and industrial sources have reported various characterization methodology, modeling and designs to decouple self-heating impact to HCD [55][56][57][58][59]. Self-heating effect on HCD EOL ∆Idsat% was corrected and reported with 10%~35% correction from different DOEs, process and performance [2,21]. ...
Gate-All-Around (GAA) Nanosheet (NS) transistors have been identified as the device architecture for 3 nm and beyond as they provide additional scaling benefits. The Hot Carrier (HC) effect cannot be ignored in the development of metal oxide semiconductor field effect transistors (MOSFETs). In this article, we present a comprehensive review of Hot Carrier Degradation (HCD) studies on GAA NS transistors including geometry dependencies, surface orientation impacts, corner effects, characterization methodologies, process impacts and self-heating impacts from different researchers, together with the challenges and outlook, providing an insightful and valuable HCD reliability discussion and review on the cutting-edge technology in continuous MOSFET scaling.
... Hot-carrier degradation (HCD) has been recognized as the most harmful degradation issue limiting the lifetime of modern metal-oxide semiconductor field-effect transistors (MOSFETs) [1][2][3]. As such, comprehensive and predictive modeling of HCD is crucial for enabling further development of micro/nanoelectronics. ...
We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a wide range of gate and drain voltages (Vgs and Vds, respectively). Special attention is paid to the contribution of secondary carriers (generated by impact ionization) to HCD, which was shown to be significant under stress conditions with low Vgs and relatively high Vds. Implementation of this contribution is based on refined modeling of carrier transport for both primary and secondary carriers. To validate the model, we employ foundry-quality n-channel transistors and a broad range of stress voltages {Vgs,Vds}.
In this paper, the self-heating effect for multi-finger fully depleted SOI nMOSFETs is investigated. The layout parameters of the transistor are varied, and the conductance-based method is used for the extraction of the thermal resistance. An empirical-based scalable thermal resistance model that accounts for geometrical layout parameters is developed. Further, hot carrier stress degradation is examined, and a correlation between self-heating and hot carrier degradation is established. The associated self-heating with geometrical dimension influences the amount of hot carrier degradation and should be taken into account for accurate degradation modeling. It is found that with the increase of temperature, the contribution of the parasitic bias temperature instability effect increases the drift of the threshold voltage. Improved thermal and reliability performance is achieved for the device structures where a continuous active area is divided into multiple smaller active regions.
Thermal resistance (Rth) is an important design parameter for high power integrated circuits (ICs). Evaluation of Rth is particularly complicated for FETs in CMOS silicon-on-insulator (SOI) technology. Although the buried oxide underneath FETs in CMOS ICs presents a barrier to heat flow, the interconnect metals and surrounding oxide provide additional paths for heat-sinking. This paper describes simulations of the layout-dependent Rth of FETs in a CMOS-SOI IC including the interconnect effects, and experimental measurements that support the simulated results. The simulation technique used is an adaptation of a commercial electromagnetic solver, EMX, to heat flow. Simulation results show that in representative layouts with power FETs the heat flow via interconnects accounts for 50 to 70% of the overall heat flow in representative microwave and millimeter-wave ICs. Analytical results are presented to allow estimation of various Rth contributions. Experimental measurements are reported using I-V characteristics of a p-n diode to monitor the temperature of an FET, in good agreement with the analysis. Guidelines for the reduction of Rth are discussed. A layout technique for reducing Rth of an FET is described, and demonstrated experimentally by I-V measurements. The benefit of vias through the buried oxide is highlighted.
A combination of hot-carrier degradation (HCD) and self-heating (SH) was acknowledged to be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with confined architectures, such as fin and nanowire (NW) FETs. Although the view on whether SH accelerates or inhibits HCD in n-channel devices is controversial, it is commonly accepted that in p-channel FETs HCD becomes more pronounced due to SH. Therefore, we develop a framework for modeling coupled HCD and SH and validate it against experimental data acquired in p-channel Si NWFETs. This framework incorporates a carrier transport solver linked to a solver for the lattice heat flow equation; the latter solver allows one to evaluate a non-uniform lattice temperature distribution in the device. Carrier energy distribution functions obtained considering coordinate-dependent lattice temperature are used to calculate the rates of the multiple- and single-carrier processes of SiH bond dissociation. In addition to perturbation of carrier transport by SH, elevated lattice temperature results in enhancement of the thermal contribution to the bond rupture rate and shortens vibrational lifetime of the SiH bond, thereby reducing the multiple-carrier process rate. All these three aspects are captured by our framework, importance of each of them is analyzed, and our approach was shown to accurately reproduce experimental data.
In comparison to MOSFET much superior in terms of Electrostatic properties and manufacturability. In today scenario FinFETs are acknowledged as the most promising technology for developing the low power based VLSI Circuit. Most challenging aspect in the MOSFET designing to scale down the device to below 20nm but this challenge can easily overdrive by using the FinFET for minimizing
the leakage current to enhance the performance of the VLSI circuits. In this paper, proposed a two design of FinFETs at scale of 20nm & 14nm in terms of channel length and comparative analysis done on the performance basis. In 14nm FinFETs 81% improvement observed as compared to 20nm and 81.6% improvement observed in terms of power parameter and Ion /Ioff current ratio of the 14nm FinFET is 1010 in compared to the 20nm FinFET. Switching speed of the 14nm FinFET high in comparison to 20nm.
As foreseen by Keyes in the late 1960s, the self-heating effect has emerged as an important concern for device performance, output power density, run-time variability, and reliability of modern field-effect transistors. The self-heating effect is aggravated as the device footprint scales down for higher level of integration (low-power devices) or as the devices are operated in ultrahigh voltage regimes (high-power devices). In this article, we focus on the implications of self-heating on hot carrier degradation (HCD) of modern transistors by integrating within a coherent theoretical framework a broad range of experimental data scattered in the literature. We explain why system integration exacerbates transistor self-heating, while high-frequency digital operation ameliorates it, suggesting an opportunity for co-optimization. We conclude this article by discussing the various material-device-system design strategies to reduce HCD and suggesting open problems for further research.
We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hot-carrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration Nit. These deterministic densities Nit for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible.
This paper describes three different measurement methodologies for the electrical characterization of FinFET self-heating at wafer-level. Finite element simulations of heat transport are used to interpret heater-sensor temperature gradients and validate the measurements. The different sensor types were designed to use the threshold voltage (V
T
) of an adjacent FET, the forward bias (V
D
) of an adjacent pn-junction or the gate resistance (R
G
) of the device itself. We report that self-heating is underestimated by 35% when sensed at a neighboring device. We also confirm that heat from local and surrounding sources are additive.
Self-heating is a growing concern for thin-body devices. In this paper, we discuss the impact of self-heating on TDDB using uniform and non-uniform gate dielectric stress. We show lifetime reduction with increasing drain voltages consistent with elevated temperature stress. It is also shown that the power law dependence to gate voltage is preserved at different drain voltages. Due to limited self-heating during nominal device operation TDDB lifetime is not reduced for CMOS circuits.
Device level Self-Heating (SH) is becoming a limiting factor during traditional DC Hot Carrier stresses in bulk and SOI technologies. Consideration is given to device layout and design for Self-Heating minimization during HCI stress in SOI technologies, the effect of SH on activation energy (Ea) and the SH induced enhancement to degradation. Applying a methodology for SH temperature correction of extracted device lifetime, correlation is established between DC device level stress and AC device stress using a specially designed ring oscillator.
The impact of self-heating effect (SHE) on device reliability characterization, such as BTI, HCI, and TDDB, is extensively examined in this work. Self-heating effect and its impact on device level reliability mechanisms is carefully studied, and an empirical model for layout dependent SHE is established. Since the recovery effect during NBTI characterization is found sensitive to self-heating, either changing VT shift as index or adopting μs-delay measurement system is proposed to get rid of SHE influence. In common HCI stress condition, the high drain stress bias usually leads to high power or self-heating, which may dramatically under-estimate the lifetime extracted. The stress condition Vg = 0.6~0.8Vd is suggested to meet the reasonable operation power and self-heating induced temperature rising. Similarly, drain-bias dependent TDDB characteristics are also under-estimated due to the existence of SHE and need careful calibration to project the lifetime at common usage bias.
This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.
- Vandervoorn
Vandervoorn, "Self-heat reliability considerations on Intel's 22nm Tri-Gate
technology," Reliability Physics Symposium (IRPS), 2013 IEEE International,
Anaheim,
CA,
pp.
5D.1.1-5D.1.5,
June
2013.
DOI:
10.1109/IRPS.2013.6532036.