Article

A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes

National Taiwan University, T’ai-pei, Taipei, Taiwan
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 10/2003; 50(9):589 - 601. DOI: 10.1109/TCSII.2003.816923
Source: IEEE Xplore

ABSTRACT

The coordinate rotational digital computer (CORDIC) algorithm is a well-known iterative method for the computation of vector rotation. For applications that require forward rotation (or vector rotation) only, the angle recoding (AR) technique provides a relaxed approach to speed up the operation of the CORDIC algorithm. In this paper, we further apply the concept of AR technique to extend the elementary angle set in the microrotation phase. This technique is called the extended elementary-angle set (EEAS) scheme. The proposed EEAS scheme provides a more flexible way of decomposing the target rotation angle in CORDIC operation, and its quantization error performance is better than the AR technique. Meanwhile, to solve the optimization problem encountered in the EEAS scheme, we also proposed a novel search algorithm, called the trellis-based searching (TBS) algorithm. Compared with the greedy algorithm used in the conventional AR technique, the proposed TBS algorithm yields apparent signal-to-quantization-noise ratio (SQNR) improvement. Moreover, in the scaling phase of the EEAS-based CORDIC algorithm, we suggest a novel scaling operation, called Extended Type-II (ET-II) scaling operation. The ET-II scaling operation applies the same design concepts as the EEAS scheme. It results in much smaller quantization error than conventional Type-I scaling operation in the numerical approximation of scaling factor. By combining the aforementioned new schemes, the proposed EEAS-based CORDIC algorithm can improve the overall SQNR performance by up to 25 dB compared with previous works. Also, given the same target SQNR performance, we require only about 66% iteration number in the iterative CORDIC structure, or use 66% hardware complexity in the parallel CORDIC structure compared with conventional AR technique. Hence, high-performance/low-latency CORDIC very large-scale integration architectures can be achieved without degrading the SQNR performance.

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    • "O algoritmo também pode ser utilizado em qualquer outra aplicação que requeira o processamento de sinais em tempo real, como controle e automação de dispositivos [11] [12] [13]. Uma limitação apresentada pelo algoritmo CORDIC é sua latência de cálculo; todavia isso pode ser minimizado transformando-se o algoritmo computacional em segmentos independentes e para implementar esses segmentos individuais usa-se diferentes processadores CORDIC [14]. Na seção II deste trabalho será apresentada uma análise matemática do CORDIC, passo a passo, com o método de pseudo-rotações 1 de um vetor num plano bidimensional. "

    Full-text · Article · Apr 2015
    • "Among general rotators we find numerous versions of the CORDIC algorithm. Some works combine several microrotation stages into a single stage [3], [4] in order to reduce the number of iterations of the CORDIC. The work in [5] is based on skipping and/or repeating micro-rotations. "

    No preview · Article · Jan 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    • "Using this recoding schemes the total number of iterations could be reduced to less than half of the conventional CORDIC algorithm for the same accuracy. Wu et al [7] have suggested an AR scheme based on an extended elementary-angle-set (EEAS), that provides a more flexible way of decomposing the target rotation angle. In the EEAS approach, the set S EAS of the elementary-angle set is extended further to S EEAS = "
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    ABSTRACT: Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation. But, we do not find any optimized coordinate rotation digital computer (CORDIC) design for vector-rotation through specific angles. Therefore, in this paper, we present optimization schemes and CORDIC circuits for fixed and known rotations with different levels of accuracy. For reducing the area- and time-complexities, we have proposed a hardwired pre-shifting scheme in barrel-shifters of the proposed circuits. Two dedicated CORDIC cells are proposed for the fixed-angle rotations. In one of those cells, micro-rotations and scaling are interleaved, and in the other they are implemented in two separate stages. Pipelined schemes are suggested further for cascading dedicated single-rotation units and bi-rotation CORDIC units for high-throughput and reduced latency implementations. We have obtained the optimized set of micro-rotations for fixed and known angles. The optimized scale-factors are also derived and dedicated shift-add circuits are designed to implement the scaling. The fixed-point mean-squared-error of the proposed CORDIC circuit is analyzed statistically, and strategies for reducing the error are given. We have synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-nm library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed and known angles of rotation. We find similar results of synthesis for different Xilinx field-programmable gate-array platforms.
    Full-text · Article · Feb 2013 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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