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Systolic architecture for modulo multiplication

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Abstract

With the current advances in VLSI technology, traditional algorithms for Residue Number System (RNS) based architectures should be reevaluated to explore the new technology dimensions. In this brief, we introduce A θ(log n) algorithm for large moduli multiplication for RNS based architectures. A systolic array has been designed to perform the modulo multiplication algorithm. The proposed modulo multiplier is much faster than previously proposed multipliers and more area efficient. The implementation of this multiplier is modular and is based on using simple cells which leads to efficient VLSI realization. A VLSI implementation using 3 micron CMOS technology shows that a pipelined n-bit module multiplication scheme can operate with a throughput of 30 M operation per second

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... Designing an efficient modular multiplier is, then, an important task. Many multipliers can be found in literature [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17]. ...
... However, these designs are limited to small moduli. Elleithy and Bayoumi [15] have introduced an architecture for modular multiplication. The design, which consists mainly of modular adders, is suitable for medium and large moduli. ...
... This seems to be very impractical. The third group deals with medium and large moduli [11], [12], [13], [15], [16], [17]. It uses basically arithmetic components, like binary multipliers and adders, operating in parallel, along with a few small-size ROMs or logic components. ...
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Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In realizing these multipliers, ROM-based structures are more efficient for small moduli. Due to the exponential growth of ROM sizes, implementations with arithmetic components are more suitable for medium and large moduli. This paper presents a new modular multiplier that can deal efficiently with medium and large size moduli. The design of this modular multiplier that multiplies two n bit residue digits consists, basically, of a (n×n) binary multiplier, a ((n-1-k)×k) binary multiplier (k<n), three n-bit adders, and a small-size combinational circuit. When compared with the most competitive published work, the new multiplier reduces, significantly, both time delay and hardware requirements. The design is very suitable for VLSI realization
... Combinatorial-logic-based residue arithmetic circuits can be very efficient when bases of moduli of the form or [7]- [10] are used, as the corresponding circuits resemble the simplicity of ordinary binary arithmetic, due to the carry-ignore, carry-add, and carry-subtract properties. Adder-based word-level modulo circuits are presented in [11] and [12]. In particular, in [11], a systolic architecture for modulo multiplication is presented, which consists mainly of modular adders. ...
... Adder-based word-level modulo circuits are presented in [11] and [12]. In particular, in [11], a systolic architecture for modulo multiplication is presented, which consists mainly of modular adders. The multiplier in [12] uses binary multipliers and adders as building blocks. ...
... Property 1: Let , , and be radix-digits. Then, for the operation , it holds that (9) Proof: The proof is given in Appendix A. Let the elements of the vector (10) be organized into groups of bits each, starting from the least significant position to form as follows: (11) where , , is the binary-vector representation of a radix-digit. ...
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A graph-based technique is introduced for the design of a class of residue arithmetic multipliers, as well as a family of new high-radix digit adders. A proposed design technique derives simple high-radix modulo- r <sup>n</sup> multipliers by optimally selecting among the variety of introduced digit adders the ones that compose a minimal-area multiplier. The proposed technique minimizes multiplier complexity by selecting digit adders that observe the constraints imposed on the maximum values of the various intermediate digits. The proposed technique leads to significant area and time improvements over previously published architectures for practical modulus cases.
... transform (DFT) [7]. Elleithy and Bayoumi presented an architecture for modular multiplication, which consists mainly of modular adders and is suitable for medium and large moduli [8]. Stouraitis et al. [9] introduced full-adder (FA) based architectures for RNS multiply-add operations, which adopt the carry-save array paradigm, while the same architecture has been refined by Soudris et al. in [10]. ...
... , of (7) is reduced to , which represents zero, because the bit weight is ignored in -bit two's complement addition. Therefore, in order to evaluate (5) using two's complement arithmetic, the term is encoded according to the three possible values assumed by , as if if if (8) where . Due to (5) and (8), can be computed by (9) where is a cumulative additive constant, computed as (10) and ...
... In the following, the performance of the proposed residue multiplier is compared to the adder-based architectures presented in [7], [8], and [13]. The area complexity of the pseudoRNS multiplier [7] equals the complexity of -bit multipliers and -bit adders and the overall delay is . ...
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A novel hardware algorithm, a VLSI architecture, and an optimization methodology for residue multipliers are introduced in this paper. The proposed design approach identifies certain properties of the bit products that participate in the residue product computation and subsequently exploits them to reduce the complexity of the implementation. A set of introduced theorems is used to identify the particular properties. The introduced theorems are of significant practical importance because they allow the definition of a graph-based design methodology. In addition, a bit-product weight encoding scheme is investigated in a systematic way, and exploited in order to minimize the number of bit products processed in the proposed multiplier. Performance data reveal that the introduced architecture achieves area × time complexity reduction of up to 55%, when compared to the most efficient previously reported design.
... In [14] and [16] a generic structure for modular compressing of four inputs to two outputs is presented. This structure computes the modular reduction in five steps as depicted in Figure 1(a). ...
... The first step taken to evaluate the RNS compressors was to compare the obtained results for the considered modulo {2 n − 3} and {2 n − 3} compressor structures, namely i) CSA [16] 4:2, ii) CSA-1, and iii) CSA-2. ...
... As expected from the theoretical analysis, the CSA-2 structure is the most area and delay efficient realization, as depicted in Table I and Figure 4. Units for modulo {2 n − 1} and {2 n + 1} have also been synthesized, in order to evaluate their performance, regarding circuit area (A), delay (T), and AT 2 as performance metric. Experimental results suggest that the proposed structure CSA-2 4:2 has less 33% area and achieves a reduction of the delay up to 33% compared to CSA [16] 4:2 structure. The structure CSA-I has equal delay than CSA [16] ...
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In this paper Residue Number Systems (RNS) con- version structures from Binary to RNS modulo {2 n ± 3} are proposed. These structures are based on arithmetic calcula- tions without the need for Lookup Tables as in the related art. Additionally, the required 4:2 and 3:2 Carry-Save Adders (CSA) modulo {2 n ± 3} are also proposed. Experimental results obtained for an ASIC technology suggest that the presented CSAs, needed in the conversion, improve the related art by reducing the required area resources by 33% and achieving a 1.49× speedup. Experimental results for the proposed conversion units suggest that improvements in performance up to 3 times can be achieved,while reducing the required area resources by 85%. Index Terms—Residue Number System; Conversion units; Compressor units; Arithmetic;
... Specifically, RNS has been realized in applications involving the design of adaptive coded multicarrier modulation systems [3], delta-sigma modulators [4], Discrete Fourier Transform, Number Theoretic Transform and many other applications [1,2]. This implies that designing efficient modular components like adders and multipliers is a very essential issue in implementing different RNS-based applications and processors [5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26]. ...
... Parker and Benaissa [14] introduced a serial modular multiplier. Elleithy and Bayoumi [15] proposed a systolic architecture for modulo multiplication which consists, mainly, of modular adders. Di Claudio et al. [16] presented also a multiplier based on a new pseudo-RNS and utilized, basically, arithmetic components. ...
... Substituting (8) into (15) leads to: ...
... A number of techniques have been proposed by researchers for the implementation of =ldtip&cation h RNS. Look-up tables have been the main modules in constructing RNS multipliers [2]- [5]. Memory-based structures a e efficient €or small modnli sizes. ...
... Memory-based structures a e efficient €or small modnli sizes. For medium and large moduli, bitlevel structures a r e more efficient [5]. ...
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The design of Residue Number System (RNS) multipliers has received considerable attention in the last few years. This paper presents a new approach for designing modular multipliers using a combinational logic technique. The idea is based on constructing a truth table whose inputs are the bits of the multiplicand and the multiplier. The outputs are the bits of the modular product. Realizing any minimized Boolean function is achieved using two levels of gates. Compared to most recent developed approach, our new technique requires less integrated circuit area and operates at a higher speed
... The multiplier introduced in [13] is efficient, for large moduli, when compared with ROM-based implementations. The multipliers in [14]- [15] use binary multipliers and adders as building blocks. Similarly, the newly proposed multiplier in [16] uses similar components. ...
... While the binary-to-residue conversion does not pose a serious threat to the high speedRNS operations, the residue-to-binary conversion can be a bottleneck. Chinese Remainder Theorem (CRT) [6] is considered the main algorithm for the conversion process. Several implementations of the residue decoder have been reported [2,5,7-101. ...
Data
Designing an optimal Residue Number System (RNS) processor in terms of area and speed depends on the choice of the system moduli. In this paper an optimal algorithm for choosing the system moduli is presented. The algorithm takes into consideration several constraints imposed by the problem definition. The problem is formalized as an integer programming problem to optimize an aredtime objective function.
... While the binary-to-residue conversion does not pose a serious threat to the high speedRNS operations, the residue-to-binary conversion can be a bottleneck. Chinese Remainder Theorem (CRT) [6] is considered the main algorithm for the conversion process. Several implementations of the residue decoder have been reported [2,5,7-101. ...
Data
Designing an optimal Residue Number System (RNS) processor in terms of area and speed depends on the choice of the system moduli. In this paper an optimal algorithm for choosing the system moduli is presented. The algorithm takes into consideration several constraints imposed by the problem definition. The problem is formalized as an integer programming problem to optimize an aredtime objective function.
... Each cell contains a multiplier and an adder. In a high-complexity system, area restriction is very crucial, thus leads to a need for a systolic array-based implementation of the area -consuming operator such as multiplier678. The multiplier in each cell of the systolic array for convolution is a natural candidate for systolization and should be implemented using systolic array as is proposed in this paper. ...
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... for . Restriction (3) is necessary to assure that every integer , , can be uniquely represented as an -tuple (4) where denotes the residue of modulo . The main benefit of adopting RNS to perform arithmetic operations is that it allows for the totally parallel addition, subtraction, and multiplication of operands expressed as -tuples of the form (4). ...
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... At first, emphasis should be on efficient implementations of modular multipliers . If we look at modular multipliers, many designs have been proposed in the literature, ranging from look-up table based structures for small moduli [42] [23] [32] [15], to devices restricted to specific moduli [33] [44] [22], to architectures suitable for medium and large moduli and using only arithmetic and logic components [16] [1] [45] [2] [22]. ...
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... Therefore, designing an efficient residue adder is an important task in realizing different RNS-based applications [1], [2], [3]. Moreover, residue adders are very important components in building residue-based multipliers [2], [3], [4], [5], [6], [21], 22], [23], residue to binary converters, generators, and other arithmetic operations [7], [8], [9], [10], [11], [12], [13], [20]. ...
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... The use of RNS has been adopted in several digital signal processing applications 6,7,8,9,10,11 . Finally, modular adders are essential building blocks for modular multipliers 12,13 , residue to binary converters 14,15 and other modular operations 16,17 . ...
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A technique for multiplying numbers, modulo a prime number, using look-up tables stored in read-only memories is discussed. The application is in the computation of number theoretic transforms implemented in a ring which is isomorphic to a direct sum of several Galois fields, parallel computations being performed in each field. The look-up table technique uses the addition of indexes within a ring that contains at least twice as many elements as the field. Specific examples are given for multiplication modulo 19 using ROM arrays, and multiplication modulo 13 using an 8048 single chip microcomputer.
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Modulo Pi multipliers are implemented by look-up tables when Pi is small (5 bits or less) and by index calculus if Pi is larger (6 bits or more). However, index calculus only works for prime moduli Pi. In this letter, we introduce a new square-law multiplier that is useful for modulo Pi multiplication where Pi is any modulus. It is expected that this will have important applications in RNS arithmetic computing hardware. Copyright © 1980 by the Institute of Electrical and Electronics Engineers, Inc.
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Digital systems structured into residue arithmetic units may play an important role in ultra-speed, dedicated, real-time systems that support pure parallel processing of integer-valued data. It is a 'carry-free' system that performs addition, subtraction, and multiplication as concurrent (parallel) operations, side-stepping one of the principal arithmetic delays - managing carry information. This article develops some of the fundamental properties of this branch of mathematics and presents the state of the RNS art and some potential applications.
A custom-designed integrated circuit for the realization of residue number digital filters A high-speed low-cost modulo pz multiplier with RNS arithmetic application
  • W Jenkins
  • E Davidson
W. Jenkins and E. Davidson, " A custom-designed integrated circuit for the realization of residue number digital filters, " in Proc. ICASSP 1985, Mar. 1985, pp. 22G223. 161 M. A. Soderstrand and C. Vernia, " A high-speed low-cost modulo pz multiplier with RNS arithmetic application, " Proc. IEEE, vol. 68, pp. 529-532, Apr. 1980.
On bit-parallel processing for modulo arithmetic
  • K M Elleithy
K. M. Elleithy, " On bit-parallel processing for modulo arithmetic, " VLSI
A high speed VLSI complex digital signal processor based on quadratic residue number system
  • M A Bayoumiin