IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 3, MARCH 1998 259
Propagation Delay and Short-Circuit Power
Dissipation Modeling of the CMOS Inverter
Labros Bisdounis, Student Member, IEEE, Spiridon Nikolaidis, Member, IEEE,
and Odysseas Koufopavlou, Member, IEEE
Abstract— This paper introduces a new, accurate analytical
model for the evaluation of the delay and the short-circuit power
dissipation of the CMOS inverter. Following a detailed analysis
of the inverter operation, accurate expressions for the output
response to an input ramp are derived. Based on this analysis
improved analytical formulae for the calculation of the propa-
gation delay and short-circuit power dissipation, are produced.
Analytical expressions for all inverter operation regions and
input waveform slopes are derived, which take into account the
influences of the short-circuit current during switching, and the
gate-to-drain coupling capacitance. The effective output transi-
tion time of the inverter is determined in order to map the real
output voltage waveform to a ramp waveform for the model to
be applicable in an inverter chain. The final results are in very
good agreement with SPICE simulations.
devoted for the extraction of accurate, analytical expressions
for timing models of basic circuits. These expressions can be
incorporated in switch-level and logic simulators, optimizing
the design verification procedure. Much of past research has
addressed the development of delay models for CMOS circuits.
In some of these models – RC circuit approaches were
used in order to map the transistors to equivalent resistors.
However, switch-level simulators based on RC models tend to
model the average circuit behavior only, since the nonlinear
behavior of the transistors is not well represented by linear
and constant resistors.
Macromodeling approaches in order to achieve efficient de-
lay modeling have been proposed. Brocco et al.  presented
an approach based on look-up tables which are generated
via precharacterization using SPICE simulations. The methods
which are based on tables with presimulation results are
time consuming and incorporate interpolation errors. Other
approaches derived delay expressions which take into ac-
count the slope of the input waveform. However they use
approximations for the load currents by assuming mean charge
conservation across the CMOS structure , or use pseu-
doempirical factors obtained from SPICE simulations in order
WITCHING-SPEED is one of the most critical perfor-
mance parameters in VLSI circuits. Much effort has to be
Manuscript received March 22, 1996; revised January 29, 1997. This paper
was recommended by Associate Editor T. Noll.
L. Bisdounis and O. Koufopavlou are with VLSI Design Laboratory,
Department of Electrical and Computer Engineering, University of Patras,
26500 Patras, Greece.
S. Nikolaidis is with the Electronics and Computers Division, Department
of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece.
Publisher Item Identifier S 1057-7122(98)01410-X.
to evaluate delays in CMOS structures controlled by slowly
varying input signals .
Deriving expressions for accurately describing the propaga-
tion delay is difficult even though these are for simple gates.
One of the goals of this paper is the analytical evaluation of the
propagation delay in a CMOS inverter. To do this, analytical
expressions of the output waveform are derived, directly from
the differential equation describing the temporal evolution of
the inverter output. It is important to have an accurate model
for the CMOS inverter operation, since several fast methods
for reducing a CMOS gate to an equivalent inverter have
been proposed , . By using these so-called “collapsing”
techniques the output response and the propagation delay of
a gate can be computed quickly and accurately without the
complications associated with trying to generalize the inverter-
based model to complex gates.
The first closed-form delay expression based on the output
response which was obtained directly from the differential
equation describing the CMOS inverter operation was derived
in  for a step input. Analytical expressions for the output
waveform and the propagation delay, including the effect of
the input waveform slope, were presented by Hedenstierna
and Jeppson . In this the influences of the short-circuit
current and the gate-to-drain coupling capacitance were ne-
glected. These output waveform expressions was extended by
Kayssi et al.  for the case of exponential input waveform.
More recently in , the differential equation describing
the discharge of the load capacitor was solved for a rising
input ramp considering the current through both transistors
and the coupling capacitance. However, in the case where the
PMOS device is in the linear region, the quadratic term of the
current through the PMOS device was neglected. Moreover,
it was not mentioned how the integration constant between
the linear and the saturation regions of the PMOS device is
calculated for fast inputs. For slow inputs least-square fitting
techniques are used. Vemuru and Thorbjornsen  derived
an expression for the output waveform, which includes the
previously mentioned quadratic term of the PMOS current but
ignored the influence of the coupling capacitance. A power
series was used to approximate the solution of the differential
equation. However, only the first five terms of the series were
considered, and a recursion form for the calculation of higher
order terms in order to obtain better accuracy was not given.
Sakurai and Newton ,  presented closed-form delay
expressions for the CMOS inverter, based on the
power in ) law MOS model which includes the carriers’
-power ( -
1057–7122/98$10.00 1998 IEEE
260 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 3, MARCH 1998
velocity saturation effect. However, this model requires the
extraction of the empirical velocity saturation index (
) from the static device characteristics for each transistor
width. For the derivation of the output expression in ,
both the short-circuit current and the coupling capacitance are
neglected. In , in order to approximate the CMOS inverter
by an NMOS circuit, a fictitious input ramp is used which is
clamped to ground for ramp voltages less than the switching
voltage. This approximation is exact only for extreme cases
of input ramps. An extension in the delay expression of 
for the case of very lightly loaded inverter and/or slow input
signals is presented in . In this, a table of coefficients
produced from SPICE simulations is used but still neglecting
the short-circuit current. The delay model presented in 
-power MOS model taking into account the short-
circuit current of the inverter, but the output voltage and the
currents through both transistors are assumed to be piecewise
In this paper analytical expressions for the CMOS in-
verter output response to an input voltage ramp are derived.
The proposed method overcomes the deficiencies of previous
works. Based on these derived expressions, accurate analytical
formulas for the evaluation of the propagation delay and the
output transition time of the inverter for all the cases of input
ramp slopes are produced. The derived timing model takes into
account the complete expression of the short-circuit current,
and the input–output coupling capacitance. This is achieved
without using empirical approaches based on simulation results
or approximations for the transistor currents as in previous
works. The simplified bulk-charge MOS model  has been
chosen. However, the experience derived from the results
using this model could be expanded to more accurate and
The second goal of this paper is the derivation of an analyt-
ical expression for the CMOS short-circuit power dissipation.
This is very important because the growing demand for low-
power portable systems has made power dissipation a critical
parameter in chip design . During the output transition in
a static CMOS structure, a direct path from power supply to
ground is created, resulting in a short-circuit power dissipation.
The first work on the evaluation of the short-circuit power
dissipation was presented in . A zero load capacitance
and current waveform which is mirror symmetric about a
central vertical axis (at the half of the input transition time)
were assumed. Also, it is considered that the transistor, which
is switched from cutoff to saturation, remains in saturation
during the entire time when short-circuit current is conducted.
More recently, in  and  an expression for the short-
circuit energy dissipation of the CMOS inverter without the
simplifications of  was derived. However, as mentioned
above the expression of the output waveform, was derived
without consideration of the short-circuit current and the gate-
to-drain coupling capacitance. A closed-form expression for
the evaluation of the short-circuit power dissipation based
on an expression for the output waveform which considers
the current through both transistors was presented in .
Sakurai and Newton  presented a formula for the short-
circuit energy dissipation during one switching cycle which is
a direct extension of the formula presented in . The only
difference is the use of the
-power law MOS model instead
of the square-law MOS model. Recently, in  a substitution
of the input transition time as given in  into the formula
for the short-circuit dissipation also presented in , was
proposed. This results in an expression for the short-circuit
dissipation including the load capacitance which is not agreed
with the initial assumption of zero load capacitance. Vemuru
and Scheinberg  proposed a formula for the evaluation of
the short-circuit power dissipation based on the
model. In this work, the expression of the output waveform
does not include the influences of the short-circuit current and
the gate-to-drain capacitive coupling. A formulation of the
short-circuit power dissipation through an equivalent short-
circuit capacitance is presented in , where a rough linear
approximation of the output waveform is used. Recently, in
 the short-circuit current waveform was approximated with
a piecewise linear function of time, in order to estimate the
short-circuit energy dissipation. However, the energy of the
reverse current due to the gate-to-drain coupling capacitance
is subtracted from the short-circuit energy dissipation resulting
in an underestimation.
In this paper, a formula for the evaluation of the short-
circuit power dissipation for the CMOS inverter, based on
analytical expressions of the output waveform is derived. It
takes into account the currents through both transistors without
making simplifying assumptions. In order to achieve better
accuracy and to avoid an overestimation of the short-circuit
power dissipation, the influence of the gate-to-drain coupling
capacitance is considered. The derived expression clearly
shows the influences of the inverter design characteristics, the
load capacitance and the slope of the input waveform driving
the inverter on the short-circuit power dissipation.
The rest of the paper is organized as follows. In Section II,
analytical expressions of the CMOS inverter output wave-
form for all the cases of input voltage ramps, are derived.
Also, in this section a detailed analysis of all the inverter
operation regions is given. Closed-form expressions, results
and comparisons with SPICE simulations and previous works
of the propagation delay and the output transition time are
given in Sections III and IV, respectively. Our approach for
the evaluation of the CMOS short-circuit power dissipation,
results and comparison with previous works are presented in
Section V. Finally, we conclude in Section VI.
II. INVERTER OUTPUT WAVEFORM ANALYSIS
The following derivations presented are for a rising input
input ramp is similar. Taking into account the gate-to-drain
, the differential equation which
describes the discharge of the load capacitance
CMOS inverter (Fig. 1), is derived from the application of the
is the input rise time. The analysis for a falling
BISDOUNIS et al.: PROPAGATION DELAY AND SHORT-CIRCUIT POWER DISSIPATION MODELING OF THE CMOS INVERTER269
Case D: In this case, the NMOS device is entered in its
linear region, before the input voltage ramp reaches the value
. Thus, the short-circuit energy dissipation during
the falling output transition is given by
device is entering the saturation region. Using (35) for the
PMOS current in the first integral and the current equation of
the PMOS device in saturation (8) in the second integral, the
short-circuit energy dissipation is given by
is the normalized time value in which the PMOS
is the normalized output voltage value in which the PMOS
device is entering the saturation region and
Similarly, the short-circuit energy dissipation during a rising
output transition is
is given by (38).
value in which the end of the output voltage undershoot occurs
is the normalized time value in which the NMOS
device is entering the saturation region.
In Fig. 12, the short-circuit energy dissipation percentage
of the capacitive energy dissipation in one switching cycle, is
plotted as a function of
. The results have been derived for
an inverter with equal PMOS and NMOS device gain factors
Volts, with an output load of 0.5 pF, and
input rise time from 0.2 ns
can be observed in Fig. 12, the percentage of the short-circuit
energy dissipation increases when the input waveform is slow
compared with the output waveform (high values of
Hence, the contribution of the short-circuit current to the total
energy increases when the input transition time is increased
and the capacitive load is reduced. SPICE measurements have
been obtained by using the powermeter subcircuit proposed
in  and . Also, results using the approaches for the
evaluation of the short-circuit energy dissipation presented in
,  and  are given. The proposed approach gives
results closer to those derived from SPICE simulations than
the other methods. This occurs because our model includes
the influences of the short-circuit current and the gate-to-
drain coupling capacitance on the expression of the inverter
is now the input fall time, is the normalized time
to 4 ns. As
dissipation, derived from SPICE simulations and from analytical expressions.
Short-circuit energy dissipation percentage of the capacitive energy
output waveform. Also, a quite accurate method is used for the
determination of the time where the short-circuiting transistor
changes from the linear region to the saturation. The models
for the evaluation of the short-circuit dissipation presented
in  and  give inaccurate results, because zero load
capacitance is assumed. For example, in an inverter with
identical input and output transition times
short-circuit energy dissipation in one switching cycle which
is evaluated using (36) and (39) is about 9.5% of the value as
calculated in , and 8.5% of the value as calculated in .
The validity of the proposed approach has been also examined
for the case of the inverter chain. In the example shown in
Fig. 10 the discrepancy between the analytical calculated value
and that produced from SPICE measurements is about 7.5%.
In this paper an accurate analytical method for the eval-
uation of the propagation delay and the short-circuit power
dissipation in a CMOS inverter, has been presented. In order to
achieve that, analytical expressions of the inverter output ramp
response for all the cases of input ramps, have been derived.
These expressions take into account the influences of the short-
circuit current and the gate-to-drain coupling capacitance.
In addition, the effective transition time of the inverter is
evaluated in order to make the ramp model applicable to real
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Englewood Cliffs, NJ:
Labros Bisdounis (S’95) was born in Agrinio,
Greece, in 1970. He received the Diploma degree
in electrical engineering from the Department of
Electrical and Computer Engineering, University of
Patras, Greece, in 1992. He is currently pursuing the
Ph.D. degree at the VLSI Design Laboratory of the
His main research interest is on various aspects of
CMOS VLSI design such as circuit timing analysis,
power dissipation modeling, low power and high
speed CMOS digital design.
Spiridon Nikolaidis (S’89–M’93) was born in
Kavala, Greece, in 1965. He received the Diploma
and Ph.D. degrees in electrical engineering from
Patras University, Greece, in 1988 and 1994,
Since September 1996 he has been with the
Department of Physics of the Aristotle University
of Thessaloniki, Greece, as a Lecturer in VLSI
design. His research interests include CMOS
gate propagation delay and power consumption
modeling, high speed and low power CMOS circuit
techniques, and high speed and low power DSP architectures.
Odysseas Koufopavlou (S’89–M’90) was born in
Athienou, Cyprus, in 1959. He received the Diploma
of electrical engineering in 1983 and the Ph.D.
degree in electrical engineering in 1990, both from
University of Patras, Greece.
From 1990 to 1994 he was with the IBM Thomas
J. Watson Research Center, Yorktown Heights, NY.
Since 1994, he has been an Assistant Professor at
the Department of Electrical and Computer Engi-
neering, University of Patras. His research interests
include VLSI, low power design, and high perfor-
mance communication subsystems architecture and implementation. He has
several publications and inventions.
Dr. Koufopavlou is a member of Technical Chamber of Greece.