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... A common-mode equivalent is shown in Fig. 6(b). Since the input and output currents from C RES must be equal (I AMP+ = I AMP− ), the common-mode current flowing into the integration capacitor I X,CM is forced to be 0, thus achieving a constant output common-mode voltage without a dedicated CMFB circuit , . ...
... The simulated CLK-Q delay in the comparator versus C RES is shown in Fig. 11(a), and larger C RES leads to faster preamplification, which increases the comparator speed. Although the theoretical energy efficiency (FoM) is independent of C RES , as indicated by (21), in reality, they are still correlated, as shown in Fig. 11(b). If C RES is too small, the preamplification gain is not large enough to suppress the latch stage noise, causing the degradation of comparator precision. ...
This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting
and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46-
input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge.
This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4x gain, it achieves -100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26x compared with that of state-of-the-art high-linearity amplifiers.
An oversampled continuous-time (CT) pipeline ADC clocked at 9 GHz achieving 1.125-GHz bandwidth and -164 dBFS/Hz average small-signal noise density is presented. In contrast to traditional discrete-time (DT) pipeline ADCs, the system processes the signals in CT form throughout all the pipeline stages and thus sampling-induced artifacts such as aliasing and high-peak ADC driving current are mitigated. Despite the oversampled nature of the ADC, its digitization bandwidth is on par with that of traditional non-interleaved DT pipeline ADCs since CT signal processing is not constrained by settling time requirements. The ADC was fabricated in a 28-nm CMOS process technology and consumes 2.3 W.
This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17 μW, the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator's energy efficiency.
The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution . Consisting of two low-resolution charge-redistribution SARADCs coupled by a residue amplifier, a SAR-assisted pipeline ADC relaxes the noise requirements of the second stage and enhances the overall ADC speed while maintaining excellent power efficiency [1-4]. However, designs reported in [1,2] rely on power-hungry telescopic amplifiers that also limit the available inter-stage residue gain due to low output swing. A lower-power alternative is a dynamic amplifier, which operates as an open-loop time-domain integrator [3,4]. Although time-domain integration provides the benefit of noise filtering, the calibration required to achieve an accurate residue gain increases design complexity and test cost, and limits robustness. We introduce an uncalibrated fully differential ring-amplifier-based 13b 50MS/s rail-to-rail input swing SAR-assisted pipeline ADC with Waiden and Schreier (SNDR) FoMs of 6.9fJ/conversion-step and 174.9dB, respectively. We also present an improved DAC switching technique that further reduces the first DAC energy consumption and also reduces the DAC errors.
Autonomous wireless sensor nodes for cloud networks require ultra-low-power electronics. In particular, sensor readout interfaces need low-speed high-precision ADCs for capturing, e.g., bio-potential signals, environmental information, or interactive multimedia. For these applications, state-of-the-art SAR ADCs can provide highly power-efficient solutions (<;10fJ/conversion-step) but with limited accuracy (SNDR <;63dB) [1,2]. Alternatively, ΔΣ ADCs offer higher precision at the cost of lower efficiency (e.g. 84dB SNDR with 54fJ/conversion-step ). This work bridges the existing performance gap by extending the accuracy of low-power SAR ADCs to SNDRs in the order of 70-to-80dB. Feedback-controlled data-driven noise reduction , oversampling, chopping  and dithering  techniques are combined to increase both SNR and linearity in a power-efficient way. Various ADC modes are supported by making these techniques individually programmable, thereby extending the application range.
Two continuous-time input pipeline ADC architectures are introduced. The continuous-time input approach overcomes many of the challenges associated with a pure switched-capacitor architecture. The resistive input load of the two new architectures provides a benign interface to external drive circuitry. The switched-capacitor sampling function is moved to the second stage input which greatly eases the sampling distortion requirements and obviates the need for an explicit front-end sample-and-hold function. The second ADC presented additionally provides inherent anti-alias filtering, allowing the possibility of eliminating costly anti-alias filters. This second architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. Measured results obtained from two proof of concept test chips fabricated in a 0.18 μm CMOS process validate the effectiveness of the proposed techniques.
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure