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Reconfigured VLSI Architecture for Discrete Wavelet Transform: Proceedings of ICSCSP 2018, Volume 2
... This indicates that their design's operating frequency is only 10 MHz which is not at all acceptable for many real-time applications. Another significant and most recent DWT architecture was presented in the work of [22]. In the paper [22], a dual-memory controller-based 2D DWT architecture had been presented with a focus on real-time image processing. ...
... Another significant and most recent DWT architecture was presented in the work of [22]. In the paper [22], a dual-memory controller-based 2D DWT architecture had been presented with a focus on real-time image processing. The memory requirement of the design had been claimed to be optimized to facilitate real-time image processing. ...
... This PSNR calculation is also performed in host PC using Python on PyCharm IDE. In Table 7, we have compared the accuracy of our prototype 2D DWT designs implemented using both Spartan-6 and Zynq UltraScale + MPSoC, in terms of PSNR, with the latest notable existing designs of [14,19,22] for real-time image decomposition for some popular test images (256 × 256). This performance comparison is performed using both 32 bit fixed point (24 bit for the integer part and 8 bit for the fractional part) as well as 32 bit normalized floating-point representation (IEEE-754 format). ...
In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bit-parallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures. Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs. The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by ‘peak signal-to-noise ratio’ and ‘computation time’, where our proposed design outperforms other similar kind of software- and hardware-based implementations.
... Therefore, the innovative exploration and application research of its network-related technology has gradually developed into the key research content of academic work in recent years. Therefore, the combination of LDPC and Polar codes has become the mainstream direction of the two technologies in the 5G scenario [4]. This has further inspired and prompted a large number of researchers and scholars to start exploring and researching the two [5]. ...
In recent years, the application and development needs of the 5G mobile communication Internet have prompted people to gradually increase their understanding and requirements for 5G mobile communication networks in the future. Therefore, the importance of the key technology of 5G mobile communication networks will also be fully reflected. In this article, we have conducted an effective analysis of the structural issues in the background of the 5G mobile communication network and then promote the changes in the technical background of the 5G mobile communication network, which will better adapt to the needs of social development. China has a long history and traditional national culture has a long history of development. Traditional arts and craft forms occupy an important position in the development of traditional Chinese national culture and are an important manifestation of the crystallization of Chinese history and culture. The content of Chinese traditional culture is very rich and diverse in form and has certain characteristics of the Chinese nation. In the process of analyzing modern art design, we need to understand the relationship between traditional cultural elements and modern art design, analyze the connotation of traditional arts and crafts culture and Its Enlightenment to the development of modern design, so as to make better use of traditional arts and crafts for the design and creation of modern art works, and finally form characteristic art works. This article mainly studies the transformation of traditional arts and crafts in modern art design and considers the modern transformation of traditional arts and crafts, so that it can better meet the actual development of the market demand.
... Hence, memory has extensive in this architectural design. In the work of Naik et al. [17], they presented a dual memory controller based 2D DWT design with the spotlight of the real-time image processing. This design requires memory to assist the real-time image processing. ...
Due to the low compression performance of traditional compression models, we have developed a new HOA based Fractional KCA with 2D-DWT for improving the multispectral image quality. In this paper, we present a novel multispectral image compression method for improving the complexity by maintaining quality reconstruction and also reducing the size of the storage of multispectral images. Initially, Karhunen–Loeve transform (KLT) is used to remove the spatial redundancies. In the second stage, 2D DWT is used to eliminate the intraband spatial redundancies. In the third stage, Fractional KCA (FKCA) is applied to improve the post-transformation process. FKCA is connected to the band of all wavelet sub-bands to minimize the spatial redundancy between intra sub-bands. Finally, the Hybrid Optimal algorithm (HOA) based FKCA is used to eliminate the residual and information redundancy among the neighboring bands. The experimental analysis of proposed 2D-DWT based Fractional KCA shows that the model improves the performance of compression data in terms of PSNR, MSSI, and VIF. Also, the multispectral image dataset shows the proposed compression model outperforms the existing compression models such as FKLT + PCA, ADWT + OADL, and DWT + DCT
... These have been implemented for image processing [527,1582,1583], pattern recognition [476,1584], real-time processing [671,1477,1585], melanoma cancer detection [510,511,1586,1587], speech recognition [1587,1588] and so forth. Digital signal processing techniques implementations in FPGAs covers FFT [537,[1589][1590][1591][1592][1593], DWT [597,[1594][1595][1596][1597], time-to-digital converters [1598][1599][1600][1601][1602], DCT [580,[1603][1604][1605] and digital filters like FIR filter [56,612,[1606][1607][1608], Kalman filter [620,[1609][1610][1611], median filter [1612,1613], LMS [1614][1615][1616] and others. ...
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.
The hotel uses modern information technology to establish a customer data group, which contains information about the customer's information on space configuration, color design, etc., and uses scientific operation methods to accelerate the rapid, transformation and upgrading of the hotel. The rapid development of information technology represented by the big intelligent mobile cloud has a lot of functions, can meet the needs of different customers and diversified characteristics at the same time, and provides a complete, stable and accurate information integration platform for hotel system management. The main research directions of DASH include client adaptive algorithm design, multi-client fairness and resource utilization issues, client improvement under multiple servers, and server load balancing. The development and application of scientific and technological information has broken through the development path of the hotel management system, providing new development space and opportunities for the improvement of the hotel management system, but at the same time it will also face more new challenges. Therefore, this article focuses on the characteristics of the tourism accommodation management system under the big data environment, and analyzes the development of the hotel management system under the network environment. The purpose is to provide some reference and reference significance.
Dedicated hardware realisation of ‘Discrete Wavelet Transform’ (DWT) is highly demanded for real-time multimedia operations in any handheld gadgets, as DWT is a popular transform domain mathematical tool widely employed for many applications. Several DWT techniques exist in the literature assisting the software based DWT realizations which are inappropriate for any real-time operation. There also exists several hardware based solutions for DWT. But most of the VLSI architectures of DWT fails to offer balanced performance, i.e., such architectures show good performance with respect to certain metrics while sacrificing other performance metrics. In this article, a convolutional DWT based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented. Our proposed architecture is designed with an ardent focus of maintaining balanced performance. The presented design, which blends the merits of convolutional and lifting DWT while dumping their demerits, is prepared area and memory efficient by employing ‘Distributed Arithmetic’ (DA) in our own ingenious method. Comparative experimental results justify the superiority of our proposed design regarding 30% area reduction, memory saving, remarkable clock frequency attainment and acceptable computation time. Our proposed 2D DWT architecture is applied for real-time image decomposition. The outcomes of such real-time on-board testing prove the practicability of the presented work regarding accuracy, memory and power consumption.
In this paper we have discussed the design constraints of a computer vision based mobile robot and processing the real time video received from the mobile robot. The focus is on applying DWT algorithm on the real time video so that memory size required for storage is reduced. The mobile robot which feeds in the live steaming of video of surrounding area is of low quality, which has to be processed preciously. Storage of video with respect to memory is also another issue which is addressed. Memory controller is also used as an interface between memory and the processing element.
This paper deals with the video encoding techniques using Spatial and Temporal DWT (Discrete Wavelet transform). Here we will discuss about two video encoding mechanisms and their performance at different levels of DWT. Memory is the major criteria for any video processing algorithm. So, in this paper we will focus on the efficient utilization of the system memory at increased level of spatial and temporal DWT. Out of these two mechanisms, one of the mechanism implements multi resolution analysis in temporal axis. In these mechanisms dynamic (automatic) DWT level selection and manual level selection is implemented. Here we also discuss about implementing the different DWT level in spatial and temporal domain. In this paper, Haar wavelet is taken as the reference.
In this paper we are going to discuss about video encoding and decoding techniques which are applied on videos before compression and after decompression respectively. Here we are using Spatial and Temporal Discrete Wavelet Transform (DWT) to encode and decode the videos. In this paper we are comparing 4 different video encoding and decoding mechanisms on the basis of time taken for encoding and decoding, system memory usage and the mean square error (MSE) obtained after reconstruction. As we are applying these mechanisms before and after the video compression they may be called as pre/post processing techniques. Here, we also discuss about Multi-Resolution Analysis (MRA) on video in temporal axis. In this paper Haar wavelet is taken as the reference due to its ease of implementation.
Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology.
In this paper, we have proposed a design strategy for the derivation of memory-efficient architecture for multilevel 2-D DWT. Using the proposed design scheme, we have derived a convolution-based generic architecture for the computation of three-level 2-D DWT based on Daubechies (Daub) as well as biorthogonal filters. The proposed structure does not involve frame-buffer. It involves line-buffers of size 3(K-2)M/4 which is independent of throughput-rate, where K is the order of Daubechies/biorthogonal wavelet filter and M is the image height. This is a major advantage when the structure is implemented for higher throughput. The structure has regular data-flow, small cycle period TM and 100% hardware utilization efficiency. As per theoretical estimate, for image size 512 × 512, the proposed structure for Daub-4 filter requires 152 more multipliers and 114 more adders, but involves 82 412 less memory words and takes 10.5 times less time to compute three-level 2-D DWT than the best of the existing convolution-based folded structures. Similarly, compared with the best of the existing lifting-based folded structures, proposed structure for 9/7-filter involves 93 more multipliers and 166 more adders, but uses 85 317 less memory words and requires 2.625 times less computation time for the same image size. It involves 90 (nearly 47.6%) more multipliers and 118 (nearly 40.1%) more adders, but requires 2723 less memory words than the recently proposed parallel structure and performs the computation in nearly half the time of the other. Inspite of having more arithmetic components than the lifting-based structures, the proposed structure offers significant saving of area and power over the other due to substantial reduction in memory size and smaller clock-period. ASIC synthesis result shows that, the proposed structure for Daub-4 involves 1.7 times less area-delay-product (ADP) and consumes 1.21 times less energy per image- (EPI) than the corresponding best available convolution-based structure. It involves 2.6 times less ADP and consumes 1.48 times less EPI than the parallel lifting-based structure.
With the emergence of visual sensor networks (VSN), low power wavelet-based coder (WBC) is becoming increasingly mandatory. This makes the selection of the appropriate wavelet, among many competitors, not an easy task. In our context, the appropriate wavelet is that one which dissipates low energy during image decomposition, while having an adequate quality of the reconstructed image at the reception. In this paper, a comparative study is investigated between different wavelet filters. Two versions of DWT implementation are considered following their emergence: the classical convolutional-based wavelets and the relatively new lifting-based wavelets.
Wavelet coding has been shown to achieve better compression than DCT coding and moreover allows scalability. 2D DWT can be easily extended to 3D and thus applied to video coding. However, 3D subband coding of video suffers from two drawbacks. The first is the amount of memory required for coding large 3D blocks; the second is the lack of temporal quality due to the sequence temporal splitting. In fact, 3D block-based video coders produce jerks. They appear at blocks temporal borders during video playback. In this paper, we propose a new temporal scan-based wavelet transform method for video coding combining the advantages of wavelet coding (performance, scalability) with acceptable reduced memory requirements, no additional CPU complexity, and avoiding jerks. We also propose an efficient quality allocation procedure to ensure a constant quality over time.
The conventional implementation of multi-dimensional wavelet transform (e.g. 3D wavelet) requires either a high amount of "in access" memory or a continual access to slow memory of a processor which makes it infeasible for most applications. In this paper, we propose a novel algorithm for computation of an nD discrete wavelet transform (DWT) based on a lifting scheme. In addition to the benefits of the lifting scheme (which causes a major reduction in computational complexity and performs the total computations in the time domain), our real-time approach computes the coefficients for all kinds of 1<sup>st</sup> and 2<sup>nd</sup> generation wavelets with short delay and optimized utilization of the slow and fast memories of a processor.
An optimal three-dimensional (3-D) coefficient tree structure for 3-D zerotree wavelet video coding is considered in this paper. The 3-D zerotree wavelet video coding is inspired by the success of the two-dimensional (2-D) zerotree wavelet image coding. Existing 3-D zerotree wavelet video codecs use the either symmetric or symmetric-alike 3-D tree structure, which is a straightforward extension of the symmetric 2-D tree structure in the zerotree wavelet image coding. In this paper, we show that the 3-D zerotree coding does not need to be applied symmetrically along all the directions, as the 2-D zerotree image coding does. We find that an asymmetric 3-D tree structure working with a more flexible asymmetric 3-D wavelet transform can produce a higher compression ratio than traditional symmetric approaches. The new 3-D tree structure can be used to improve the rate-distortion performance of many existing 3-D zerotree wavelet video codecs without sacrificing other features such as scalability and computational efficiency. The new tree structure is applied to the 3-D set partitioning in hierarchical trees method and receives convincing peak signal-to-noise ratio improvements in experiments.
Embedded zerotree wavelet (EZW) coding, introduced by J. M. Shapiro, is a very effective and computationally simple technique for image compression. Here we offer an alternative explanation of the principles of its operation, so that the reasons for its excellent performance can be better understood. These principles are partial ordering by magnitude with a set partitioning sorting algorithm, ordered bit plane transmission, and exploitation of self-similarity across different scales of an image wavelet transform. Moreover, we present a new and different implementation, based on set partitioning in hierarchical trees (SPIHT), which provides even better performance than our previosly reported extension of the EZW that surpassed the performance of the original EZW. The image coding results, calculated from actual file sizes and images reconstructed by the decoding algorithm, are either comparable to or surpass previous results obtained through much more sophisticated and computationally complex methods. In addition, the new coding and decoding procedures are extremely fast, and they can be made even faster, with only small loss in performance, by omitting entropy coding of the bit stream by arithmetic code.
This paper presents a high-speed memory efficient VLSI architecture for three dimensional (3-D) discrete wavelet transform. A major strength of the proposed architecture lies in reducing the number and period of clock cycles for the computation of wavelet transform. This five stage pipelined architecture shares the partial load of the next stage with the present stage to reduce computational load at the next stage and critical path delay (CPD). The proposed architecture has replaced the multiplications by optimized shift and add operations to reduce the CPD. Implementation results show that the proposed architecture benefits from the features of reduced memory, low power consumption, low latency, and high throughput over several existing designs.
This chapter deals with the video encoding techniques using Spatial and Temporal Discrete Wavelet transform (DWT). It discusses about two video encoding mechanisms and their performance at different levels of DWT. Memory is the major criteria for any video processing algorithm, so in this chapter focus on the efficient utilization of the system memory at increased level of spatial and temporal DWT is presented. Out of these two mechanisms, one of the mechanism implements multi resolution analysis in temporal axis. Here the chapter also discuss about implementing the different DWT level in spatial and temporal domain. In this chapter, the Haar wavelet is taken as the reference. Finally, the compression of the videos is achieved by using the standard embedded zero wavelet tree (EZW) mechanism. The performance of the EZW based compression in terms of the PSNR and compression ratio is shown for various videos in this chapter.
This paper deals with the application of Spatial and Temporal DWT (Discrete Wavelet transform) on the videos. Here we will discuss about three mechanisms and their performance on videos at increased DWT level. In any video processing algorithm, memory is the major criteria. In these three mechanisms dynamic (automatic) DWT level selection and manual level selection is implemented. Here we will also discuss about implementation of different DWT level in spatial and temporal domain. In this paper Haar wavelet is taken as the reference as it has its inherent properties and ease of implementation.
In this paper, a hardware efficient lifting based parallel 3-D Discrete Wavelet Transform (DWT) architecture for infinite group of pictures is proposed. Two parallel spatial and temporal DWT modules of the proposed 3-D DWT architecture give high throughput of 4 results per clock cycle. 1-D DWT blocks are employed for the spatial and temporal processing, respectively. Two parallel spatial processors reduce the requirement of frame memory for temporal transformation. Higher throughput reduces the working clock cycles which leads to low power design. A novel dual scanning in Z-fashion is utilized to reduce the internal transpose buffer requirement and waiting time of both the column and the temporal processors. The comparison results show that the internal memory requirement of the proposed 3-D DWT architecture is smaller than other familiar architectures. The Register Transfer Logic (RTL) of the proposed design is described using VHDL and synthesized for the Xilinx Virtex-IV series field programmable gate array (FPGA). The RTL of the proposed design is also synthesized using UMC 180 nm technology CMOS standard cell library for Application Specific Integrated Circuit (ASIC) design.
This article is essentially tutorial in nature. We show how any discrete wavelet transform or two band subband filtering with finite filters can be decomposed into a finite sequence of simple filtering steps, which we call lifting steps but that are also known as ladder structures. This decomposition corresponds to a factorization of the polyphase matrix of the wavelet or subband filters into elementary matrices. That such a factorization is possible is well-known to algebraists land expressed by the formula SL(n; R[z, z(-1)]) = E(n; R[z, z(-1)])); it is also used in linear systems theory in the electrical engineering community. We present here a self-contained derivation, building the decomposition from basic principles such as the Euclidean algorithm, with a focus on applying it to wavelet filtering. This factorization provides an alternative for the lattice factorization, with the advantage that it can also be used in the biorthogonal, i.e., non-unitary case. Like the lattice factorization, the decomposition presented here asymptotically reduces the computational complexity of the transform by a factor two. Ir has other applications, such as the possibility of defining a wavelet-like transform that maps integers to integers.
An architecture for the lifting-based two-dimensional dis-crete wavelet transform is presented. The architecture is easily scaled to accommodate different numbers of lifting steps. The architecture has regular data flow and low control complexity, and achieves 100% hardware utilization. Sym-metric extension of the image to be transformed is handled in a way that does not require additional computations or clock cycles. The architecture is investigated in terms of hardware parameters such as memory size and number of ports, number of memory accesses, latency, and through-put. The proposed architecture achieves higher throughput and uses less embedded memory than architectures based on convolutional filter banks.
This paper presents an architecture of the lifting-based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-D-DWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The proposed architecture has been successfully implemented on Xilinx Virtex-IV series field-programmable gate array, offering a speed of 321 MHz, making it suitable for real-time compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7).
We propose a novel, content adaptive method for motion-compensated three-dimensional wavelet transformation (MC 3-D DWT) of video. The proposed method overcomes problems of ghosting and nonaligned aliasing artifacts which can arise in regions of motion model failure, when the video is reconstructed at reduced temporal or spatial resolutions. Previous MC 3-D DWT structures either take the form of MC temporal DWT followed by a spatial transform ("t+2D"), or perform the spatial transform first ("2D + t"), limiting the spatial frequencies which can be jointly compensated in the temporal transform, and hence limiting the compression efficiency. When the motion model fails, the "t + 2D" structure causes nonaligned aliasing artifacts in reduced spatial resolution sequences. Essentially, the proposed transform continuously adapts itself between the "t + 2D" and "2D + t" structures, based on information available within the compressed bit stream. Ghosting artifacts may also appear in reduced frame-rate sequences due to temporal low-pass filtering along invalid motion trajectories. To avoid the ghosting artifacts, we continuously select between different low-pass temporal filters, based on the estimated accuracy of the motion model. Experimental results indicate that the proposed adaptive transform preserves high compression efficiency while substantially improving the quality of reduced spatial and temporal resolution sequences.
In this paper a real-time 3-D DWT algorithm and its architecture realization is proposed. Reduced buffer and low wait-time are the salient features which makes it fit for bidirectional videoconferencing applications mostly in real-time biomedical applications. The proposed algorithm updates the coefficients in the temporal direction with every two new frames. In the architectural implementation, the memory requirement is minimal due to low buffering requirement. The reduced hardware complexity and 100% hardware utilization is ensured in this design. Time area product for the spatial DWT is 1.5 at. This architecture implemented on 0.25 μ BiCMOS technology. At a operating frequency of 100 MHz the power consumption is appreciably lower compared to those reported.
A real-time 3D sub-band coding (SBC) technique using a discrete wavelet transform is proposed. The main advantages of the proposed scheme lie in the reduction of wait time and diminution of buffer size in 3D SBC. The major delay which is due to the group of frames (GOF) generation in the temporal direction is decreased by dynamic updating of the transform coefficients. The dynamic updating handles much a lower dimension of data compared to 3D SBC, and thus facilitates better hardware utilisation with lower overhead. A data-folding architecture is used in unison with the CORDIC-based QMF lattice filters for realisation of 2D DWTs using a 4-tap Daubechies filter. The data scanning pattern for the spatial domain signal results in a low-complexity control circuit. The multiplierless DWT architecture operating at 100 MHz is implemented on 0.25 μm BiCMOS technology and found to have much lower power dissipation compared to the multiplier-based structures for FIR realisation. The optimised design of the DWT filter using data-folding architecture resulted in an appreciable low memory budget of N<sup>2</sup>/4 + 2N for 2D DWT and O(N N<sup>2</sup>/M) time required for temporal direction decomposition. Hardware utilisation in the proposed architecture is 100%.
In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most important advantages of CMOS image sensors over CCDs is the ability to integrate sensing with analog and digital processing down to the pixel level. Finally, we focus on recent developments and future research directions that are enabled by pixel-level processing, the applications of which promise to further improve CMOS image sensor performance and broaden their applicability beyond current markets.
Image compression using wavelet transform compression ratio and Psnr calculation
- K Sureshraju
- V R Satpute
- A G Keskar
- K D Kulat