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Reconfigured VLSI Architecture for Discrete Wavelet Transform: Proceedings of ICSCSP 2018, Volume 2

Authors:
  • K C College of Engineering and Management Studies and Research, Thane(E) 400607
  • K.L.E. Dr. M.S.Sheshgiri College of Engineering & Technology
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... This indicates that their design's operating frequency is only 10 MHz which is not at all acceptable for many real-time applications. Another significant and most recent DWT architecture was presented in the work of [22]. In the paper [22], a dual-memory controller-based 2D DWT architecture had been presented with a focus on real-time image processing. ...
... Another significant and most recent DWT architecture was presented in the work of [22]. In the paper [22], a dual-memory controller-based 2D DWT architecture had been presented with a focus on real-time image processing. The memory requirement of the design had been claimed to be optimized to facilitate real-time image processing. ...
... This PSNR calculation is also performed in host PC using Python on PyCharm IDE. In Table 7, we have compared the accuracy of our prototype 2D DWT designs implemented using both Spartan-6 and Zynq UltraScale + MPSoC, in terms of PSNR, with the latest notable existing designs of [14,19,22] for real-time image decomposition for some popular test images (256 × 256). This performance comparison is performed using both 32 bit fixed point (24 bit for the integer part and 8 bit for the fractional part) as well as 32 bit normalized floating-point representation (IEEE-754 format). ...
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In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bit-parallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures. Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs. The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by ‘peak signal-to-noise ratio’ and ‘computation time’, where our proposed design outperforms other similar kind of software- and hardware-based implementations.
... Therefore, the innovative exploration and application research of its network-related technology has gradually developed into the key research content of academic work in recent years. Therefore, the combination of LDPC and Polar codes has become the mainstream direction of the two technologies in the 5G scenario [4]. This has further inspired and prompted a large number of researchers and scholars to start exploring and researching the two [5]. ...
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In recent years, the application and development needs of the 5G mobile communication Internet have prompted people to gradually increase their understanding and requirements for 5G mobile communication networks in the future. Therefore, the importance of the key technology of 5G mobile communication networks will also be fully reflected. In this article, we have conducted an effective analysis of the structural issues in the background of the 5G mobile communication network and then promote the changes in the technical background of the 5G mobile communication network, which will better adapt to the needs of social development. China has a long history and traditional national culture has a long history of development. Traditional arts and craft forms occupy an important position in the development of traditional Chinese national culture and are an important manifestation of the crystallization of Chinese history and culture. The content of Chinese traditional culture is very rich and diverse in form and has certain characteristics of the Chinese nation. In the process of analyzing modern art design, we need to understand the relationship between traditional cultural elements and modern art design, analyze the connotation of traditional arts and crafts culture and Its Enlightenment to the development of modern design, so as to make better use of traditional arts and crafts for the design and creation of modern art works, and finally form characteristic art works. This article mainly studies the transformation of traditional arts and crafts in modern art design and considers the modern transformation of traditional arts and crafts, so that it can better meet the actual development of the market demand.
... Hence, memory has extensive in this architectural design. In the work of Naik et al. [17], they presented a dual memory controller based 2D DWT design with the spotlight of the real-time image processing. This design requires memory to assist the real-time image processing. ...
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Due to the low compression performance of traditional compression models, we have developed a new HOA based Fractional KCA with 2D-DWT for improving the multispectral image quality. In this paper, we present a novel multispectral image compression method for improving the complexity by maintaining quality reconstruction and also reducing the size of the storage of multispectral images. Initially, Karhunen–Loeve transform (KLT) is used to remove the spatial redundancies. In the second stage, 2D DWT is used to eliminate the intraband spatial redundancies. In the third stage, Fractional KCA (FKCA) is applied to improve the post-transformation process. FKCA is connected to the band of all wavelet sub-bands to minimize the spatial redundancy between intra sub-bands. Finally, the Hybrid Optimal algorithm (HOA) based FKCA is used to eliminate the residual and information redundancy among the neighboring bands. The experimental analysis of proposed 2D-DWT based Fractional KCA shows that the model improves the performance of compression data in terms of PSNR, MSSI, and VIF. Also, the multispectral image dataset shows the proposed compression model outperforms the existing compression models such as FKLT + PCA, ADWT + OADL, and DWT + DCT
... These have been implemented for image processing [527,1582,1583], pattern recognition [476,1584], real-time processing [671,1477,1585], melanoma cancer detection [510,511,1586,1587], speech recognition [1587,1588] and so forth. Digital signal processing techniques implementations in FPGAs covers FFT [537,[1589][1590][1591][1592][1593], DWT [597,[1594][1595][1596][1597], time-to-digital converters [1598][1599][1600][1601][1602], DCT [580,[1603][1604][1605] and digital filters like FIR filter [56,612,[1606][1607][1608], Kalman filter [620,[1609][1610][1611], median filter [1612,1613], LMS [1614][1615][1616] and others. ...
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Chapter
This chapter deals with the video encoding techniques using Spatial and Temporal Discrete Wavelet transform (DWT). It discusses about two video encoding mechanisms and their performance at different levels of DWT. Memory is the major criteria for any video processing algorithm, so in this chapter focus on the efficient utilization of the system memory at increased level of spatial and temporal DWT is presented. Out of these two mechanisms, one of the mechanism implements multi resolution analysis in temporal axis. Here the chapter also discuss about implementing the different DWT level in spatial and temporal domain. In this chapter, the Haar wavelet is taken as the reference. Finally, the compression of the videos is achieved by using the standard embedded zero wavelet tree (EZW) mechanism. The performance of the EZW based compression in terms of the PSNR and compression ratio is shown for various videos in this chapter.
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In this paper a real-time 3-D DWT algorithm and its architecture realization is proposed. Reduced buffer and low wait-time are the salient features which makes it fit for bidirectional videoconferencing applications mostly in real-time biomedical applications. The proposed algorithm updates the coefficients in the temporal direction with every two new frames. In the architectural implementation, the memory requirement is minimal due to low buffering requirement. The reduced hardware complexity and 100% hardware utilization is ensured in this design. Time area product for the spatial DWT is 1.5 at. This architecture implemented on 0.25 μ BiCMOS technology. At a operating frequency of 100 MHz the power consumption is appreciably lower compared to those reported.
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A real-time 3D sub-band coding (SBC) technique using a discrete wavelet transform is proposed. The main advantages of the proposed scheme lie in the reduction of wait time and diminution of buffer size in 3D SBC. The major delay which is due to the group of frames (GOF) generation in the temporal direction is decreased by dynamic updating of the transform coefficients. The dynamic updating handles much a lower dimension of data compared to 3D SBC, and thus facilitates better hardware utilisation with lower overhead. A data-folding architecture is used in unison with the CORDIC-based QMF lattice filters for realisation of 2D DWTs using a 4-tap Daubechies filter. The data scanning pattern for the spatial domain signal results in a low-complexity control circuit. The multiplierless DWT architecture operating at 100 MHz is implemented on 0.25 μm BiCMOS technology and found to have much lower power dissipation compared to the multiplier-based structures for FIR realisation. The optimised design of the DWT filter using data-folding architecture resulted in an appreciable low memory budget of N<sup>2</sup>/4 + 2N for 2D DWT and O(N N<sup>2</sup>/M) time required for temporal direction decomposition. Hardware utilisation in the proposed architecture is 100%.
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In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most important advantages of CMOS image sensors over CCDs is the ability to integrate sensing with analog and digital processing down to the pixel level. Finally, we focus on recent developments and future research directions that are enabled by pixel-level processing, the applications of which promise to further improve CMOS image sensor performance and broaden their applicability beyond current markets.
Image compression using wavelet transform compression ratio and Psnr calculation
  • K Sureshraju
  • V R Satpute
  • A G Keskar
  • K D Kulat