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Boosting Ge-epi N-well Mobility with Sn Implantation and P-well Mobility with Cluster-C Implantation
Abstract
We investigated the effects of Sn, Si and cluster-C implantation into both P-well and N-well doped regions of 100nm Ge-epilayer on Si wafers after RTA annealing. For the P-well case a 7.3x increase in bulk drift mobility to 3384cm 2 /V-s with cluster-C implant and for the N-well case a 2.8x increase in bulk drift mobility to 1256cm2/V-s with Sn implant. Measuring layer mobility depth profiles shows mobility in the top 10-20nm of the surface can be up to 7Kcm2/V-s for N-well and 45Kcm2/V-s for P-well.
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Ultra-shallow n+ ion implanted junctions with high dopant activation in high mobility thin Ge epilayer was realized by rapid and controlled Ge melt depth using 308nm Excimer laser annealing. Extremely high Sb activation of 1E21/cm3 for 10nm USJ is > 3x higher than best P activation level of 3E20/cm3 for a 10nm USJ. High level of surface Sb also induced surface tensile strain-Ge which degraded electron mobility while Sn induced surface compressive strain-Ge improving Sb electron mobility by 2x but degraded P electron mobility by 3x. Differential Hall layer mobility depth plots shows Sn implant improved the mobility uniformity in the top 30nm surface. Controlled Ge melt depth can be extended to 7nm n+ USJ using sub-keV ultra-low energy implantation and results will be shown in the future with n+ activation of 1E21/cm3.
3-D bulk-FinFET at 22nm node uses (551) 8 o tapered Fin sidewall with 45 o high tilt implantation for doping, eSiGe S/D for PMOS channel compressive strain and amorphous implant SPC (solid phase crystallization) dislocation defects for NMOS channel tensile strain. For 14nm node taller Fins with vertical sidewalls and partial recess embedded n+ S/D was added. 7/10nm node will use direct high mobility channel materials 50% SiGe to 100% Ge. To avoid CVD Ge or SiGe epi defects liquid phase crystallization (LPC) by laser melt annealing is an alternative using amorphous-Ge dose control deposition by ion implantation and at 5nm node gate-all-around (GAA) nano-wire. Residual implant damage into Ge material creates high level of acceptors up to 7E19/cm ³ requiring high temperature annealing above 600 o C to annihilate and establish stable p+ or n+ dopant activation for ultra-shallow junctions. For USJ n+ junctions in Ge, melt controlled junction depth using Sb dopant results in highest dopant activation >1E21/cm ³ at sub-10nm junction depth. Si-capping layer offers lowest n+ Ge junction leakage and Sn co-implantation enables surface strain-Ge engineering for higher channel mobility.
Ge-epi on Si wafers contain >1E7/cm2 TDD which degrades junction leakage and potentially also degrade mobility. Therefore we investigated using Ge-Cz wafers as an alternative free of Ge-epi TDD and observed that surface Sn implantation up to 16% can induce surface tensile strain-Ge measured by XRD enhancing top 30nm n-well surface layer mobility (µe) by 2.5x from 500cm2/Vs up to 1250cm2/Vs but the surface tensile strain-Ge degraded top 30nm p-well surface layer mobility (µh) by 73% from 3000cm2/Vs to 800cm2/Vs and surface bulk mobility by 74% from 1850cm2/Vs to 480cm2/Vs.
This paper will review strain-Si and strain-Ge formation by ion implantation and advanced annealing to form localized tensile and compressive strain channel for improved electron and hole mobility in Group IV materials. Carbon implant was used to reduce the surface Si lattice constant forming Si+C material for localized compressive strain-Si channel. Ge implant was used to increase the surface Si lattice constant forming Si+Ge material for localized tensile strain-Si channel and Sn implant to increase the surface Ge lattice constant forming Ge+Sn material for localized tensile strain-Ge channel. Use of ion implant and advanced annealing for strain formation resulted in tensile strain-Si+Ge improving hole mobility by 4x and electron mobility by 1.5x while tensile strain-Ge+Sn improved electron mobility by 2-2.5x.
The resistivity and mobility data of GaAs at 300°K have been analyzed by least-square method and plotted as a function of the impurity concentration. The measured impurity levels in GaAs have been presented in graphical form for the most accurate and up-to-date values. For convenient reference the published results for Ge and Si are also presented.RésuméLes données de mobilité et de résistivité de AsGa à 300°K ont été analysées par la méthode du moindre carré et tracées en fonction de la concentration d'impuretés. Les niveaux d'impuretés mesurés dans le AsGa ont été présentés en forme graphique pour les valeurs les plus récentes et les plus exactes. Pour une référence convenable, les résultats publiés pour le germanium et le silicium sont aussi présentés.ZusammenfassungDaten des spezifischen Widerstands und der Beweglichkeit für GaAs bei 300°K wurden nach der Methode kleinster Abweichungsquadrate analysiert und als Funktion der Störstellenkonzentration aufgetragen. Die gemessenen Störstellenniveaus in GaAs wurden unter Verwendung der genauesten und neuesten Werte in Kurvenform dargestellt. Zu Vergleichszwecken sind die veröffentlichten Ergebnisse für Ge und Si ebenfalls angegeben.
presentation material slide #59
- J Borland
J. Borland, presentation material slide #59, ECS Symposium on ULSI
Process Integration 9, Oct 2015, ECS Transactions, vol. 69, no. 10, p.11.
- J Borland
J. Borland, ECS Symposium on High Purity and High Mobility
Semiconductors 14, Oct 2016, ECS Transactions, vol.75, no.4, p 199.