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A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC

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For low-power hearing aid device application, a fully integrated optimized hearing aid SoC structure is proposed in this paper. The SoC consists of high-resolution, low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit, charge pump, digital signal processing (DSP) platform, and Class-D amplifier. A novel peak-statistical algorithm is proposed to track signal amplitude and adjust automatic gain control loop gain precisely. A comparative DWA is applied to break the correlation of in-band tone and sequential selection scheme, which realizes second-order noise shaping and suppresses harmonic effectively. The SoC has been implemented with 0.13 µm CMOS process. By measurement, it shows that the peak signal-to-noise ratio (SNR) of AFE is 82.6 dB and peak SNR of Class-D amplifier is 79.8 dB. Also, three main algorithms of wide dynamic range compression, noise reduction, and feedback cancelation are executed through DSP platform. With 1 V supply voltage, total SoC power is 1.1 mW and core area is 9.3 mm2. Based on our SoC, a hearing aid device prototype is produced that shows its great potential for mass manufacture in the future.
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Circuits, Systems, and Signal Processing (2019) 38:2893–2909
https://doi.org/10.1007/s00034-018-1002-6
A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC
Chengying Chen1·Liming Chen1
Received: 14 July 2018 / Revised: 4 December 2018 / Accepted: 4 December 2018 /
Published online: 11 December 2018
© Springer Science+Business Media, LLC, part of Springer Nature 2018
Abstract
For low-power hearing aid device application, a fully integrated optimized hearing
aid SoC structure is proposed in this paper. The SoC consists of high-resolution,
low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit,
charge pump, digital signal processing (DSP) platform, and Class-D amplifier. A novel
peak-statistical algorithm is proposed to track signal amplitude and adjust automatic
gain control loop gain precisely. A comparative DWA is applied to break the correlation
of in-band tone and sequential selection scheme, which realizes second-order noise
shaping and suppresses harmonic effectively. The SoC has been implemented with
0.13 µm CMOS process. By measurement, it shows that the peak signal-to-noise ratio
(SNR) of AFE is 82.6 dB and peak SNR of Class-D amplifier is 79.8 dB. Also, three
main algorithms of wide dynamic range compression, noise reduction, and feedback
cancelation are executed through DSP platform. With 1 V supply voltage, total SoC
power is 1.1 mW and core area is 9.3 mm2. Based on our SoC, a hearing aid device
prototype is produced that shows its great potential for mass manufacture in the future.
Keywords Hearing aid ·Low power ·Analog front-end ·DSP
1 Introduction
As an important field of intelligent sensing system, health care has been paid more
and more attention in recent years. As we know, hearing health as the basic guarantee
of human speech communication is one of the important symbols of the development
of people’s physical and mental health. In 2017, more than 466 million people in the
world are affected by hearing impairment, of which nearly 10% are children [25].
BChengying Chen
chenchengying363@163.com
Liming Chen
2017000002@xmut.edu.cn
1School of Opto-electronic and Communication Engineering, Xiamen University of
Technology, Xiamen 361024, China
Content courtesy of Springer Nature, terms of use apply. Rights reserved.
... Digital signal processors (DSPs) are programmable, but it is essential to reduce their power consumption by hardware customizations and optimizations. The integration of application-specific instruction-set processors (ASIPs) in hearing aid devices is a current research topic [7][8][9][10][11][12]. Their advantages are high flexibility and programmability. ...
... The processor architectures are designed and optimized to efficiently execute particular hearing aid algorithms listed in Table 2.1. The architectures of these processors can be grouped [32] Beamforming (BMF) [8,33] 1984 [34] Speech enhancement (SE) [11] 1985 [35] Noise reduction (NR) [19] 1995 [36] Noise reduction (NR) [8] 1996 [37] Speech enhancement (SE) [8] 1997 [38] Voice activity detector (VAD) [39] 1997 [40] Feedback cancellation (FBC) [41] 1999 [42] Feedback cancellation (FBC) [19,43] 2001 [44] Adaptive directional microphone (ADM) [45] 2001 [46] Digital filter [13,15,39,[47][48][49] 2001 [50] Noise reduction (NR) [11] 2002 [51] Adaptive SNR Monitor [49] 2002 [52] Voice activity detector (VAD) [53] 2002 [54] Noise reduction (NR) [19,41,43] 2002 [55] Beamforming (BMF) [56] 2005 [57] Dynamic range compression (DRC) [8] 2005 [58] Speech enhancement (SE) [56] 2006 [59] Noise reduction (NR) [19,43] 2007 [60] Noise reduction (NR) [53] 2008 [61] Dynamic range compression (DRC) [62] 2008 [63] Feedback cancellation (FBC) [11] 2008 [63] Dynamic range compression (DRC) [11,19,41,43] 2008 [63] Adaptive directional microphone (ADM) [11] 2011 [27] Sound source localization (SSL) [56] 2013 [64] Speech enhancement (SE) [33] 2013 [65] Feedback cancellation (FBC) [8] 2016 [26] Speech enhancement (SE) [7,12] 2017 [66] Speech enhancement (SE) [25] 2019 [24] Speech recognition (SR) [56] into three main classes: hard-wired with dedicated processing blocks, ASIPs, and ASIPs with hardware accelerators. ...
... The processor architectures are designed and optimized to efficiently execute particular hearing aid algorithms listed in Table 2.1. The architectures of these processors can be grouped [32] Beamforming (BMF) [8,33] 1984 [34] Speech enhancement (SE) [11] 1985 [35] Noise reduction (NR) [19] 1995 [36] Noise reduction (NR) [8] 1996 [37] Speech enhancement (SE) [8] 1997 [38] Voice activity detector (VAD) [39] 1997 [40] Feedback cancellation (FBC) [41] 1999 [42] Feedback cancellation (FBC) [19,43] 2001 [44] Adaptive directional microphone (ADM) [45] 2001 [46] Digital filter [13,15,39,[47][48][49] 2001 [50] Noise reduction (NR) [11] 2002 [51] Adaptive SNR Monitor [49] 2002 [52] Voice activity detector (VAD) [53] 2002 [54] Noise reduction (NR) [19,41,43] 2002 [55] Beamforming (BMF) [56] 2005 [57] Dynamic range compression (DRC) [8] 2005 [58] Speech enhancement (SE) [56] 2006 [59] Noise reduction (NR) [19,43] 2007 [60] Noise reduction (NR) [53] 2008 [61] Dynamic range compression (DRC) [62] 2008 [63] Feedback cancellation (FBC) [11] 2008 [63] Dynamic range compression (DRC) [11,19,41,43] 2008 [63] Adaptive directional microphone (ADM) [11] 2011 [27] Sound source localization (SSL) [56] 2013 [64] Speech enhancement (SE) [33] 2013 [65] Feedback cancellation (FBC) [8] 2016 [26] Speech enhancement (SE) [7,12] 2017 [66] Speech enhancement (SE) [25] 2019 [24] Speech recognition (SR) [56] into three main classes: hard-wired with dedicated processing blocks, ASIPs, and ASIPs with hardware accelerators. ...
Thesis
Full-text available
The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements.
... The detailed parameters are summarized in Table 5. Table 6 presents the four types of HA: conventional HA [49], a wireless binaural HA [50], a smartphone-based HA system [27], and the proposed structure. [49] was a mixed-signal system, and the rest are based on digital circuit design. ...
... Table 6 presents the four types of HA: conventional HA [49], a wireless binaural HA [50], a smartphone-based HA system [27], and the proposed structure. [49] was a mixed-signal system, and the rest are based on digital circuit design. The [27], [49] is a monaural HA, and the rest are binaural HAs. ...
... [49] was a mixed-signal system, and the rest are based on digital circuit design. The [27], [49] is a monaural HA, and the rest are binaural HAs. Speech signal processing is done on the HA side for the other systems, but for the architecture we proposed, it was done on the smartphone. ...
Article
Full-text available
This paper presents a smartphone-based binaural hearing aid architecture for improving the speech intelligibility of hearing aid users. The proposed system consists of an earpiece, a smartphone and an application that performs real-time speech enhancement. The speaker’s voice, which is picked up by the microphone of the earpiece that is worn on the ear, is transmitted to the smartphone via wireless technology. After the speech intelligibility is improved in real time by the deep learning speech enhancement application, it is returned to the earpiece and generates sound. Deep learning speech enhancement algorithms can be used without performing burdensome calculations on the processors in the hearing aid. The results showed that the average usage of the central processing unit in the smartphone was approximately 26%, and the signal-to-noise ratios improve by at least 20%. The presented objective and subjective results show that the proposed method achieves comparatively more noise suppression without distorting the audio.
... The main focus of hearing aid researches are applicationspecific instruction set processor (ASIP) architectures [3]- [10]. ...
... Furthermore, the already presented framework in [19] was adapted so that Matlab fixed-point code can easily be ported onto the SoC while using hardware-aware intrinsics. These advances drastically the reduce hearing aid [4], [10] without this support. Fig. 2 depicts the SoC-Layout of the fabricated chip. ...
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To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.
... They also developed a fully integrated hearing aid SoC [16] which consisted of high-resolution, low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit, charge pump, digital signal processing (DSP) platform, and class-D amplifier. Here, the signal amplitude was tracked and the gain control loop gain was adjusted automatically by using a peak-statistical algorithm. ...
... The hearing aid SoC should provide higher SNR value ([ 80 dB) to process the high quality speech signals. Figure 12 shows that, the proposed hearing aid SoC achieves an SNR of 89.24 dB whereas, the hearing aid SoC that is proposed by Chen et al. [16] achieved SNR of only 79.8 dB. This proves that the proposed hearing aid SoC can process high-quality speech signals. ...
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... In addition, the framework first presented in [11] has been modified through the use of hardware-extensible intrinsics to enable seamless porting of MATLAB fixed-point code to the SoC. Compared to other recently presented hearing aid processors without similar support, e.g., [12], these advances significantly reduce the development and implementation time of hearing aid algorithms. After power-on, the audio core of the SmartHeaP SoC controls all necessary interfaces to the other systems and initializes the whole platform. ...
... However, the complicated calibration is always needed for the capacitor mismatch [6,9,13,24]. Compared with SAR ADC, the delta-sigma ADC based on the dynamic amplifier is more competitive in terms of the silicon area and power [3][4][5]32]. ...
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... Several readout circuits and topologies have been proposed over the decades to acquire better performances in hearing aids system. Majority of the commercial hearing aids readout topologies is composed of capacitor array filter to achieve the filter characteristic for a bandwidth of voice [4][5][6][7]. Common issues with those topologies are limited noise performance and consuming large area due to capacitor's inheritance property which is stumble to meet modern trend requiring high performance with compact size. There is another topology which contains automatic gain control preamplifier which applied MOS-Resistive-Feedback (MRF) structure [8][9][10][11]. ...
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