ArticlePublisher preview available

A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC

Authors:
Chengying Chen
Chengying Chen
Chengying Chen
  • This person is not on ResearchGate, or hasn't claimed this research yet.
Liming Chen
Liming Chen
Liming Chen
  • This person is not on ResearchGate, or hasn't claimed this research yet.
Read publisher preview
Download citation
To read the full-text of this research, you can request a copy directly from the authors.

Abstract and Figures

For low-power hearing aid device application, a fully integrated optimized hearing aid SoC structure is proposed in this paper. The SoC consists of high-resolution, low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit, charge pump, digital signal processing (DSP) platform, and Class-D amplifier. A novel peak-statistical algorithm is proposed to track signal amplitude and adjust automatic gain control loop gain precisely. A comparative DWA is applied to break the correlation of in-band tone and sequential selection scheme, which realizes second-order noise shaping and suppresses harmonic effectively. The SoC has been implemented with 0.13 µm CMOS process. By measurement, it shows that the peak signal-to-noise ratio (SNR) of AFE is 82.6 dB and peak SNR of Class-D amplifier is 79.8 dB. Also, three main algorithms of wide dynamic range compression, noise reduction, and feedback cancelation are executed through DSP platform. With 1 V supply voltage, total SoC power is 1.1 mW and core area is 9.3 mm2. Based on our SoC, a hearing aid device prototype is produced that shows its great potential for mass manufacture in the future.
Figures - available from: Circuits Systems and Signal Processing
This content is subject to copyright. Terms and conditions apply.
A preview of this full-text is provided by Springer Nature.
Learn more
Content available from Circuits Systems and Signal Processing
This content is subject to copyright. Terms and conditions apply.
Circuits, Systems, and Signal Processing (2019) 38:2893–2909
https://doi.org/10.1007/s00034-018-1002-6
A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC
Chengying Chen1·Liming Chen1
Received: 14 July 2018 / Revised: 4 December 2018 / Accepted: 4 December 2018 /
Published online: 11 December 2018
© Springer Science+Business Media, LLC, part of Springer Nature 2018
Abstract
For low-power hearing aid device application, a fully integrated optimized hearing
aid SoC structure is proposed in this paper. The SoC consists of high-resolution,
low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit,
charge pump, digital signal processing (DSP) platform, and Class-D amplifier. A novel
peak-statistical algorithm is proposed to track signal amplitude and adjust automatic
gain control loop gain precisely. A comparative DWA is applied to break the correlation
of in-band tone and sequential selection scheme, which realizes second-order noise
shaping and suppresses harmonic effectively. The SoC has been implemented with
0.13 µm CMOS process. By measurement, it shows that the peak signal-to-noise ratio
(SNR) of AFE is 82.6 dB and peak SNR of Class-D amplifier is 79.8 dB. Also, three
main algorithms of wide dynamic range compression, noise reduction, and feedback
cancelation are executed through DSP platform. With 1 V supply voltage, total SoC
power is 1.1 mW and core area is 9.3 mm2. Based on our SoC, a hearing aid device
prototype is produced that shows its great potential for mass manufacture in the future.
Keywords Hearing aid ·Low power ·Analog front-end ·DSP
1 Introduction
As an important field of intelligent sensing system, health care has been paid more
and more attention in recent years. As we know, hearing health as the basic guarantee
of human speech communication is one of the important symbols of the development
of people’s physical and mental health. In 2017, more than 466 million people in the
world are affected by hearing impairment, of which nearly 10% are children [25].
BChengying Chen
chenchengying363@163.com
Liming Chen
2017000002@xmut.edu.cn
1School of Opto-electronic and Communication Engineering, Xiamen University of
Technology, Xiamen 361024, China
Content courtesy of Springer Nature, terms of use apply. Rights reserved.
... Digital signal processors (DSPs) are programmable, but it is essential to reduce their power consumption by hardware customizations and optimizations. The integration of application-specific instruction-set processors (ASIPs) in hearing aid devices is a current research topic [7][8][9][10][11][12]. Their advantages are high flexibility and programmability. ...
... The processor architectures are designed and optimized to efficiently execute particular hearing aid algorithms listed in Table 2.1. The architectures of these processors can be grouped [32] Beamforming (BMF) [8,33] 1984 [34] Speech enhancement (SE) [11] 1985 [35] Noise reduction (NR) [19] 1995 [36] Noise reduction (NR) [8] 1996 [37] Speech enhancement (SE) [8] 1997 [38] Voice activity detector (VAD) [39] 1997 [40] Feedback cancellation (FBC) [41] 1999 [42] Feedback cancellation (FBC) [19,43] 2001 [44] Adaptive directional microphone (ADM) [45] 2001 [46] Digital filter [13,15,39,[47][48][49] 2001 [50] Noise reduction (NR) [11] 2002 [51] Adaptive SNR Monitor [49] 2002 [52] Voice activity detector (VAD) [53] 2002 [54] Noise reduction (NR) [19,41,43] 2002 [55] Beamforming (BMF) [56] 2005 [57] Dynamic range compression (DRC) [8] 2005 [58] Speech enhancement (SE) [56] 2006 [59] Noise reduction (NR) [19,43] 2007 [60] Noise reduction (NR) [53] 2008 [61] Dynamic range compression (DRC) [62] 2008 [63] Feedback cancellation (FBC) [11] 2008 [63] Dynamic range compression (DRC) [11,19,41,43] 2008 [63] Adaptive directional microphone (ADM) [11] 2011 [27] Sound source localization (SSL) [56] 2013 [64] Speech enhancement (SE) [33] 2013 [65] Feedback cancellation (FBC) [8] 2016 [26] Speech enhancement (SE) [7,12] 2017 [66] Speech enhancement (SE) [25] 2019 [24] Speech recognition (SR) [56] into three main classes: hard-wired with dedicated processing blocks, ASIPs, and ASIPs with hardware accelerators. ...
... The processor architectures are designed and optimized to efficiently execute particular hearing aid algorithms listed in Table 2.1. The architectures of these processors can be grouped [32] Beamforming (BMF) [8,33] 1984 [34] Speech enhancement (SE) [11] 1985 [35] Noise reduction (NR) [19] 1995 [36] Noise reduction (NR) [8] 1996 [37] Speech enhancement (SE) [8] 1997 [38] Voice activity detector (VAD) [39] 1997 [40] Feedback cancellation (FBC) [41] 1999 [42] Feedback cancellation (FBC) [19,43] 2001 [44] Adaptive directional microphone (ADM) [45] 2001 [46] Digital filter [13,15,39,[47][48][49] 2001 [50] Noise reduction (NR) [11] 2002 [51] Adaptive SNR Monitor [49] 2002 [52] Voice activity detector (VAD) [53] 2002 [54] Noise reduction (NR) [19,41,43] 2002 [55] Beamforming (BMF) [56] 2005 [57] Dynamic range compression (DRC) [8] 2005 [58] Speech enhancement (SE) [56] 2006 [59] Noise reduction (NR) [19,43] 2007 [60] Noise reduction (NR) [53] 2008 [61] Dynamic range compression (DRC) [62] 2008 [63] Feedback cancellation (FBC) [11] 2008 [63] Dynamic range compression (DRC) [11,19,41,43] 2008 [63] Adaptive directional microphone (ADM) [11] 2011 [27] Sound source localization (SSL) [56] 2013 [64] Speech enhancement (SE) [33] 2013 [65] Feedback cancellation (FBC) [8] 2016 [26] Speech enhancement (SE) [7,12] 2017 [66] Speech enhancement (SE) [25] 2019 [24] Speech recognition (SR) [56] into three main classes: hard-wired with dedicated processing blocks, ASIPs, and ASIPs with hardware accelerators. ...
KAVUAKA - A Low-Power Application-Specific Processor Architecture for Digital Hearing Aids
Thesis
Full-text available
  • Mar 2021
The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements.
View
... The detailed parameters are summarized in Table 5. Table 6 presents the four types of HA: conventional HA [49], a wireless binaural HA [50], a smartphone-based HA system [27], and the proposed structure. [49] was a mixed-signal system, and the rest are based on digital circuit design. ...
... Table 6 presents the four types of HA: conventional HA [49], a wireless binaural HA [50], a smartphone-based HA system [27], and the proposed structure. [49] was a mixed-signal system, and the rest are based on digital circuit design. The [27], [49] is a monaural HA, and the rest are binaural HAs. ...
... [49] was a mixed-signal system, and the rest are based on digital circuit design. The [27], [49] is a monaural HA, and the rest are binaural HAs. Speech signal processing is done on the HA side for the other systems, but for the architecture we proposed, it was done on the smartphone. ...
A Smart Binaural Hearing Aid Architecture Leveraging a Smartphone APP With Deep-Learning Speech Enhancement
Article
Full-text available
  • Mar 2020
This paper presents a smartphone-based binaural hearing aid architecture for improving the speech intelligibility of hearing aid users. The proposed system consists of an earpiece, a smartphone and an application that performs real-time speech enhancement. The speaker’s voice, which is picked up by the microphone of the earpiece that is worn on the ear, is transmitted to the smartphone via wireless technology. After the speech intelligibility is improved in real time by the deep learning speech enhancement application, it is returned to the earpiece and generates sound. Deep learning speech enhancement algorithms can be used without performing burdensome calculations on the processors in the hearing aid. The results showed that the average usage of the central processing unit in the smartphone was approximately 26%, and the signal-to-noise ratios improve by at least 20%. The presented objective and subjective results show that the proposed method achieves comparatively more noise suppression without distorting the audio.
View
... The main focus of hearing aid researches are applicationspecific instruction set processor (ASIP) architectures [3]- [10]. ...
... Furthermore, the already presented framework in [19] was adapted so that Matlab fixed-point code can easily be ported onto the SoC while using hardware-aware intrinsics. These advances drastically the reduce hearing aid [4], [10] without this support. Fig. 2 depicts the SoC-Layout of the fabricated chip. ...
SmartHeaP - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI
Conference Paper
  • Sep 2022
To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.
View
... They also developed a fully integrated hearing aid SoC [16] which consisted of high-resolution, low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit, charge pump, digital signal processing (DSP) platform, and class-D amplifier. Here, the signal amplitude was tracked and the gain control loop gain was adjusted automatically by using a peak-statistical algorithm. ...
... The hearing aid SoC should provide higher SNR value ([ 80 dB) to process the high quality speech signals. Figure 12 shows that, the proposed hearing aid SoC achieves an SNR of 89.24 dB whereas, the hearing aid SoC that is proposed by Chen et al. [16] achieved SNR of only 79.8 dB. This proves that the proposed hearing aid SoC can process high-quality speech signals. ...
Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction
Article
Full-text available
  • Oct 2020
  • ANALOG INTEGR CIRC S
Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced by the use of a high resolution digital-to-time converter with its range and duty cycle calibration in background. Also, the nonlinearity of the analog front-end circuit in the proposed hearing aid SoC is reduced by introducing a switching block based dynamic element matching process. Furthermore, an improved noise reduction algorithm is proposed based on pitch based voice activity detector and multiband complex spectral subtraction to improve the performance of the proposed hearing Aid SoC. The proposed hearing aid SoC is designed in an 180 nm CMOS technology. The simulation results show that, integrated jitter of the proposed structure is reduced to 0.9 psrms and it achieves a signal to noise ratio of 89.24 dB. The total power consumption of this hearing aid is only 996 μW for 1.2 V supply that shows the superiority of the proposed work than existing works.
View
... In addition, the framework first presented in [11] has been modified through the use of hardware-extensible intrinsics to enable seamless porting of MATLAB fixed-point code to the SoC. Compared to other recently presented hearing aid processors without similar support, e.g., [12], these advances significantly reduce the development and implementation time of hearing aid algorithms. After power-on, the audio core of the SmartHeaP SoC controls all necessary interfaces to the other systems and initializes the whole platform. ...
View
... However, the complicated calibration is always needed for the capacitor mismatch [6,9,13,24]. Compared with SAR ADC, the delta-sigma ADC based on the dynamic amplifier is more competitive in terms of the silicon area and power [3][4][5]32]. ...
A Low-Power Common-Mode Detector with PVT-Compensation Technique for Dynamic Amplifier in Delta-Sigma Modulator
Article
Full-text available
  • Feb 2023
  • CIRC SYST SIGNAL PR
A low-power common-mode detector (LPCMD) with process, supply voltage and temperature (PVT)-compensation technique for the dynamic amplifier in delta-sigma modulator (DSM) is proposed. By adopting the varying supply voltages to compensate the variation of the transistors’ threshold voltage, the proposed LPCMD improves the robustness of the dynamic amplifier (DA). Additionally, the auxiliary circuit providing the varying supply voltages is realized by the low-power regulator, which has the advantage of low power and low complexity. To demonstrate the feasibility of the proposed LPCMD with the PVT-compensation technique, a second-order 2-bit quantization-based DSM is designed in 180 nm CMOS technology and the postlayout simulation is performed. The DSM achieves a signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic range (SFDR) of 93 dB and 95 dB at the sampling frequency of 204.8 kHz, respectively, with the power consumption of 11 µW, leading to a 171.6 dB SNDR-based Schreier figure-of-merit (FoMSNDR). Furthermore, the SNDR degradation of the DSM under all process corner and temperature from − 40 to 125 ℃ is less than 3 dB. The postlayout simulation result of the DSM verifies the feasibility and effectiveness of the proposed LPCMD and PVT-compensation technique.
View
... They significantly improved the total harmonic distortion (THD) by digital gain control. A low power, high performance analog front-end (AFE) circuit for digital hearing aid SoC presented in [6]. It adopts digital feedback gain control (DFGC) for accurate amplification. ...
A fast configurable AGC for front-end of digital hearing aids
Article
Full-text available
  • Nov 2021
  • ANALOG INTEGR CIRC S
This paper presents a fast configurable automatic gain control (AGC) with strong focus on fast acting control and low power consumption. This AGC includes two paths, main amplification path and gain adjusting path. Using the gain adjusting path through an extra amplifier provides a way for tracking and comparing the input signal with four adjusted thresholds to be judged for selecting the appropriate gain value for main amplification path. This mechanism of gain control is done by reorganization of input level and changing the resistance of feedback in main amplification path to generate smooth variation gain, without any interruption or delay in signal flow through the variable gain amplifier. Moreover, in order to protect the user from intense transients in variations of the input signal level, output level of variable gain amplifier is directly monitored using optimum threshold to reduce the overall gain using feedback control mechanism. The minimum power is consumed by gain adjusting path has almost no considerable on power consumption, it greatly improves hearing quality. Meanwhile, using a large size PMOS differential pair at the input improved the noise performance. Proposed AGC designed and simulated in TSMC 130-nm CMOS process. The post layout simulation results the maximal SNR is 84.6 dB in 100 Hz–19.6 kHz band-width and the total consumption power of this AGC is 78 μW at 1 V supply voltage. In addition, its gain is varied smoothly between 20 to 57 dB. Achieved results demonstrate that designed AGC meet the requirement of analog front end of hearing aids.
View
... Several readout circuits and topologies have been proposed over the decades to acquire better performances in hearing aids system. Majority of the commercial hearing aids readout topologies is composed of capacitor array filter to achieve the filter characteristic for a bandwidth of voice [4][5][6][7]. Common issues with those topologies are limited noise performance and consuming large area due to capacitor's inheritance property which is stumble to meet modern trend requiring high performance with compact size. There is another topology which contains automatic gain control preamplifier which applied MOS-Resistive-Feedback (MRF) structure [8][9][10][11]. ...
An analog correlator based CMOS analog front end with digital gain control circuit for hearing aid devices
Article
Full-text available
  • Nov 2020
  • ANALOG INTEGR CIRC S
In this paper, an analog correlator based analog front end with gain control circuit for hearing aid devices is designed and fabricated with 0.18 μm CMOS process. The proposed analog front end consists of an analog correlator comprised of a multiplier, an integrator, and a mixed mode variable gain amplifier. The analog correlator is utilized to ensure the low input referred noise. A gain control circuit is implemented in variable gain amplifier. Based on the output of piezoelectric microphone, designed gain control circuit automatically sets the gain. The investigated analog front end offers lower noise and wider dynamic range with compact size compared to conventional architecture. It achieves a 42 nVrms input referred noise and 84 dB signal to noise ratio. The total area of the designed analog front end circuit is 386 μm× 569 μm. Designed circuit is interfaced with a sensor model of piezoelectric microphone and its performance is successfully verified against simulation results.
View
View
View
A 0.5-V R-MOSFET-C filter design using subthreshold R-MOSFET resistors and OTAs with cross-forward common-mode cancellation technique
Article
Full-text available
  • Nov 2012
A 0.5-V fully integrated R-MOSFET-C filter with low power, good linearity, and wide frequency tunability is demonstrated. It relies upon the operational transconductance amplifier using the cross-forward common-mode cancellation and the linear sub-threshold R-MOSFET resistor-both employ subthreshold operation of the transistors. A fifth-order Chebyshev low-pass filter using regular transistors with a 0.5-V threshold voltage in a 0.18-μm triple-well CMOS process is implemented for a 0.5-V supply. The filter's bandwidth can be tuned from 91 to 268 kHz, which is almost a 3-to-1 tuning ratio. At a nominal bandwidth of 135 kHz automatically set by the on-chip PLL circuit, the dynamic range is at 61.0 dB for 1% total harmonic distortion, while the spurious-free dynamic range under two-tone signals is at 53.7 dB. The total current and power consumptions including bias circuits are 1.2 mA and 0.6 mW, respectively.
View
A MEMS-based power-scalable hearing aid analog front end
Article
Full-text available
  • Jul 2011
A dual-channel directional digital hearing aid front end using microelectromechanical-systems microphones, and an adaptive-power analog processing signal chain are presented. The analog front end consists of a double differential amplifier-based capacitance-to-voltage conversion circuit, 40-dB variable gain amplifier (VGA) and a power-scalable continuous time sigma delta analog-to-digital converter (ADC), with 68-dB signal-to-noise ratio dissipating 67 μ W from a 1.2-V supply. The MEMS microphones are fabricated using a standard surface micromachining technology. The VGA and power-scalable ADC are fabricated on a 0.25-μ m complementary metal-oxide semciconductor TSMC process.
View
View
PIPELINED 5-MSAMPLE/S 9-BIT ANALOG-TO-DIGITAL CONVERTER.
Article
  • Dec 1987
A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3- mu m CMOS technology. It requires 8500 mil**2, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.
View
A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications
Article
  • Jan 2015
  • MICROELECTRON J
A low-distortion feed-forward MASH24b-24b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18 μm CMOS process with single 1.8 V supply voltage, the converter achieves a peak SNDR of 85.4 dB over a 10 MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94 dB for a 1.25 MHz@–6dBFS input signal at 160 MHz sampling frequency. The occupied area is 0.44 mm2 and dissipation power 23.4 mW.
View
A 1-V, 1.2-mA fully integrated SoC for digital hearing aids
Article
  • Jan 2015
  • MICROELECTRON J
Both power and size are very important design issues for hearing aids. This paper proposes a fully integrated low-power SoC for today׳s digital hearing aids. The SoC integrates all the audio processing elements on single chip, including the analog front-end, digital signal processing (DSP) platform and class-D amplifier. Also, the low-dropout voltage regulators and internal clock generator are both integrated to minimize the system overall size. The 24-bit DSP platform comprises an application-specific instruction-set processor and several dedicated accelerators to achieve a trade-off between flexibility and power efficiency. Three critical hearing-aid algorithms (wide dynamic range compression, noise reduction and feedback cancellation) are performed by the low-power accelerators. The proposed SoC has been fabricated in SMIC 130 nm CMOS technology. The measurement results show that the analog front-end has up to 88 dB signal-to-noise ratio. And the DSP platform consumes about 0.86 mA current at 8 MHz clock frequency when executing the three algorithms. The total current consumption of SoC is only 1.2 mA at 1 V supply. In addition, the acoustic test results indicate that the SoC is one promising candidate for hearing-aid manufacturers.
View
A low power hearing aid computing platform using lightweight processing elements
Conference Paper
  • May 2012
This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.
View
A 1.2 V 285μA analog front end chip for a digital hearing aid in 0.13 μm CMOS
Conference Paper
  • Nov 2013
We describe a low power analog front-end for a digital hearing aid, designed and fabricated in a 0.13μm CMOS process. The IC accepts inputs from a microphone or telecoil, amplifies and digitizes it for processing by a DSP, accepts digital data from the DSP, converts it to analog form using a pulse width modulated class D amplifier, and drives the earpiece, all over a 10kHz bandwidth. The programmable gain amplifier uses current sharing in the input stage to obtain low noise with low power consumption. The single-bit continuous-time ΔΣ ADC and the closed loop class-D amplifier use assisted opamp integrators to reduce power dissipation. An on chip ring oscillator provides the clock to the digital parts of the chip and to the digital signal processor (DSP). The chip has an input referred noise of 2.1μV, a dynamic range of 106 dB, an output THD of 0.006% and a peak output SNR of 79dB. It occupies 2.3 mm2 and consumes 285μA from a 1.2V supply.
View
View
A 0.964mW digital hearing aid system
Conference Paper
  • Mar 2011
This paper concerns the design and optimization of a digital hearing aid application. It aims to show that a suitably adapted ASIP can be constructed to create a highly optimized solution for the wide variety of complex algorithms that play a role in this domain. These algorithms are configurable to fit the various hearing impairments of different users. They pose significant challenges to digital hearing aids, having strict area and power consumption constraints. First, a typical digital hearing aid application is proposed and implemented, comprising all critical parts of today's products. Then a small area and ultra low-power 16-bit processor is designed for the application domain. The resulting hearing aid system achieves a power reduction of >; 56 × over the RISC implementation and can operate for >; 300 hours on a typical battery.
View